Renesas H8S/2318 series, Hardware Manual

Page: 1113 / 1121

Rev. 5.00, 12/03, page 1083 of 1088
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
Software
Standby Mode Bus-Released
State
Program Execution
State
Sleep Mode
PG1/
CS3
/
CS6
/
IRQ7
4 to 6 T T
[
CSS36
· CS25E +
CSS36 · CS167E
= 0]
kept
[
CSS36
· CS25E ·
DDR
= 1]
T
[CSS36 · CS167E ·
DDR
= 1]
T
[
CSS36
· CS25E ·
DDR ·
OPE
= 1]
T
[CSS36 · CS167E ·
DDR ·
OPE
= 1]
T
[
CSS36
· CS25E ·
DDR · OPE = 1]
H
[CSS36 · CS167E ·
DDR · OPE = 1]
H
[
CSS36
· CS25E +
CSS36 · CS167E
= 0]
kept
[
CSS36
· CS25E +
CSS36 · CS167E
= 1]
T
[
CSS36
· CS25E +
CSS36 · CS167E
= 0]
I/O port
[
CSS36
· CS25E ·
DDR
= 1]
Input port
[CSS36 · CS167E ·
DDR
= 1]
Input port
[
CSS36
· CS25E ·
DDR = 1]
CS3
[CSS36 · CS167E ·
DDR = 1]
CS6
7 T T kept kept I/O port
PG0/
ADTRG
/
IRQ6
4 to 7 T T kept kept I/O port
Legend:
H:
High level
L: Low level
T: High impedance
kept: Input port becomes high-impedance, output port retains state
DDR: Data direction register
OPE: Output port enable
WAITE: Wait input enable
BRLE: Bus release enable
BREQOE: BREQO pin enable
AnE: Address n enable (n = 23 to 20)
ASOD: AS output disable
CS167E: CS167 enable
CS25E: CS25 enable
CSS36: CS36 select
CSS17: CS17 select
PF1CS5S: Port F1 chip select 5 select
PF0CS4S: Port F0 chip select 4 select
LWROD:
LWR output disable
DAOEn: D/A output enable n (n = 0, 1)