Renesas H8S/2318 series, Hardware Manual

Page: 416 / 1121

Rev. 5.00, 12/03, page 386 of 1088
10.2 Register Descriptions
10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1)
TCNT0 TCNT1
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated
from an internal or external clock source. This clock source is selected by clock select bits CKS2
to CKS0 in TCR. The CPU can read or write to TCNT0 and TCNT1 at all times.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by a word
transfer instruction.
TCNT0 and TCNT1 can be cleared by an external reset input or by a compare match signal.
Which signal is to be used for clearing is selected by clock clear bits CCLR1 and CCLR0 in TCR.
When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1.
TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode.
10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1)
TCORA0 TCORA1
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA0 and TCORA1 are 8-bit readable/writable registers. TCORA0 and TCORA1 comprise a
single 16-bit register so they can be accessed together by a word transfer instruction.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFA flag in TCSR is set. Note, however, that comparison is disabled during the
T
2
state of a TCOR write cycle.
The timer output can be freely controlled by these compare match signals and the settings of bits
OS1 and OS0 in TCSR.