Renesas H8S/2318 series, Hardware Manual

Page: 774 / 1121

Rev. 5.00, 12/03, page 744 of 1088
The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
(4) Bit rate
Peripheral operating clock (
φ
), bit rate (B), clock select (CKS) in the serial mode register (SMR).
The error as calculated by the method below is checked to ensure that it is less than 4%. When it
is 4% or more, a bit-rate selection error is generated.
Error (%) = {[ ]
−
1}
*
100
(N+1)
*
B
*
64
*
2
(2
*
n
−
1)
φ *
10
6
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation H'06
•
Confirmation, H'06, (1 byte): Confirmation of a new bit rate
Response H'06
•
Response, H'06, (1 byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 17-85.
Host
Boot program
Setting a new bit rate
H'06 (ACK)
Waiting for one-bit period
at the specified bit rate
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
Setting a new bit rate Setting a new bit rate
Figure 17-85 New Bit-Rate Selection Sequence