Renesas H8S/2318 series, Hardware Manual

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Rev. 5.00, 12/03page 770 of 1088
18.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR. Table 18-1 shows the register configuration.
Table 18-1 Clock Pulse Generator Register
Name Abbreviation R/W Initial Value Address
*
System clock control register SCKCR R/W H'00 H'FF3A
Note: * Lower 16 bits of the address.
18.2 Register Descriptions
18.2.1 System Clock Control Register (SCKCR)
Bit : 7 6 5 4 3 2 1 0
PSTOP — DIV — — SCK2 SCK1 SCK0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W — — R/W R/W R/W
SCKCR is an 8-bit readable/writable register that controls
φ
clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—
φφφφ
Clock Output Disable (PSTOP): Controls
φ
output.
Description
Bit 7
PSTOP
Normal Operation Sleep Mode
Software
Standby Mode Hardware
Standby Mode
0
φ
output (Initial value)
φ
output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is
disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to
the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the
division ratio. As the frequency of
φ
changes, the following points must be noted.