Renesas H8S/2318 series, Hardware Manual

Page: 318 / 1121

Rev. 5.00, 12/03, page 288 of 1088
8.12.2 Register Configuration
Table 8-21 shows the port G register configuration.
Table 8-21 Port G Registers
Name Abbreviation R/W Initial Value
*
1
Address
*
2
Port G data direction register PGDDR W H'10/H'00
*
3
H'FEBF
Port G data register PGDR R/W H'00 H'FF6F
Port G register PORTG R Undefined H'FF5F
Port function control register 1 PFCR1 R/W H'0F H'FF45
Port function control register 2 PFCR2 R/W H'30 H'FFAC
Notes: 1. Value of bits 4 to 0.
2. Lower 16 bits of the address.
3. Initial value depends on the mode.
Port G Data Direction Register (PGDDR)
Bit : 7 6 5 4 3 2 1 0
— — — PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 4 and 5
Initial value : Undefined Undefined Undefined 1 0 0 0 0
R/W : — — — W W W W W
Modes 6 and 7
*
Initial value : Undefined Undefined Undefined 0 0 0 0 0
R/W : — — — W W W W W
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read.
The PGDDR is initialized by a reset and in hardware standby mode, to H'10 (bits 4 to 0) in modes
4 and 5, and to H'00 (bits 4 to 0) in modes 6 and 7*. It retains its prior state after in software
standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain
their output state or become high-impedance when a transition is made to software standby mode.
Note: * Modes 6 and 7 are not available in the ROMless versions.