Renesas H8S/2318 series, Hardware Manual

Page: 1063 / 1121

Rev. 5.00, 12/03, page 1033 of 1088
TMDR0—Timer Mode Register 0 H'FFD1 TPU0
7

1

6

1

5
BFB
0
R/W
4
BFA
0
R/W
3
MD3
0
R/W
0
MD0
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
1
TGRB Buffer Operation
TGRB operates normally
0
1
TGRA Buffer Operation
TGRA operates normally
0
1
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4

Mode
0
1
×
0
1
0
1
×
0
1
0
1
0
1
0
1
×
Notes: 1.
2.
MD3 is a reserved bit. In a write, it
should always be written with 0.
Phase counting mode cannot be
set for channels 0 and 3. In this
case, 0 should always be written to
MD2.
×
: Don't care
Bit
Initial value
Read/Write
:
:
:
TGRA and TGRC used together
for buffer operation
TGRB and TGRD used together
for buffer operation