Renesas H8S/2318 series, Hardware Manual

Page: 396 / 1121

Rev. 5.00, 12/03, page 366 of 1088
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the TCNT input clock is generated.
Figure 9-36 shows output compare output timing.
TGR
TCNT
TCNT
input clock
φ
N
N N+1
Compare
match signal
TIOC pin
Figure 9-36 Output Compare Output Timing
Input Capture Signal Timing: Figure 9-37 shows input capture signal timing.
TCNT
Input capture
input
φ
N N+1 N+2
N N+2
TGR
Input capture
signal
Figure 9-37 Input Capture Input Signal Timing