Renesas H8S/2318 series, Hardware Manual

Page: 190 / 1121

Rev. 5.00, 12/03, page 160 of 1088
6.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D
15
to D
8
) of the data bus is used.
The
LWR
pin is fixed high. Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D
15
to D
8
Valid
D
7
to D
0
Invalid
Read
HWR
LWR
D
15
to D
8
Valid
D
7
to D
0
High impedance
Write
Note: n = 0 to 7
High
Figure 6-6 Bus Timing for 8-Bit 2-State Access Space