Renesas H8S/2318 series, Hardware Manual

Page: 1052 / 1121

Rev. 5.00, 12/03, page 1022 of 1088
TSTR—Timer Start Register H'FFC0 TPU
7

0

6

0

5
CST5
0
R/W
4
CST4
0
R/W
3
CST3
0
R/W
0
CST0
0
R/W
2
CST2
0
R/W
1
CST1
0
R/W
Counter Start
0
1
TCNTn count operation is stopped
TCNTn performs count operation
Note:
(n = 5 to 0)
If 0 is written to the CST bit during operation with the TIOC pin designated for output,
the counter stops but the TIOC pin output compare output level is retained. If TIOR is
written to when the CST bit is cleared to 0, the pin output level will be changed to the
set initial output value.
Bit
Initial value
Read/Write
:
:
:
TSYR—Timer Synchro Register H'FFC1 TPU
7

0

6

0

5
SYNC5
0
R/W
4
SYNC4
0
R/W
3
SYNC3
0
R/W
0
SYNC0
0
R/W
2
SYNC2
0
R/W
1
SYNC1
0
R/W
Timer Synchronization
0
1
TCNTn operates independently (TCNT presetting/
clearing is unrelated to other channels)
(n = 5 to 0)
Notes: To set synchronous operation, the SYNC bits for at least two channels must
be set to 1.
To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR2 to CCLR0 in TCR. 1.
2.
Bit
Initial value
Read/Write
:
:
:
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible