Renesas H8S/2318 series, Hardware Manual

Page: 10 / 1121

Rev. 5.00, 12/03, page x of xxx
Item Page Revision (See Manual for Details)
“Advanced” deleted from Mnemonic column
Instruc-
tion
Fetch Branch
Address
Read Stack
Opera-
tion Byte
Data
Access Word
Data
Access Internal
Opera-
tion
Instruction Mnemonic I J K L M N
BSR BSR d:8 2 2
BSR d:16 2 2 1
JMP JMP @ERn 2
JMP @aa:24 2 1
JMP @@aa:8 2 2 1
JSR JSR @ERn 2 2
JSR @aa:24 2 2 1
JSR @@aa:8 2 2 2
RTE RTE 2 2/3
*
1
1
RTS RTS 2 2 1
TRAPA TRAPA #x:2 2 2 2/3
*
1
2
A.4 Number of States
Required for Instruction
Execution 895, 897,
901, 902
Table A-5 Number of
Cycles in Instruction
Execution 903 Note 1 amended
The number of state cycles is 2 when EXR is invalid, and 3 when EXR is
valid.
“Advanced” deleted from Instruction column
Instruction 1 2 3 4 5 6 7 8 9
BSR d:8 R:W NEXT R:W EA W:W:M
stack(H) W:W
stack(L)
BSR d:16 R:W 2nd Internal
operation,
1 state R:W EA W:W:M
stack(H) W:W
stack(L)
JMP
@@aa:8 R:W NEXT R:W:M aa:8 R:W: aa:8 Internal
operation,
1 state R:W EA
JSR @ERn R:W NEXT R:W EA W:W:M
stack(H) W:W
stack(L)
JSR @aa:24 R:W 2nd Internal
operation,
1 state R:W EA W:W:M
stack(H) W:W
stack(L)
JSR
@@aa:8 R:W NEXT R:W:M aa:8 R:W aa:8 W:W:M
stack(H) W:W
stack(L) R:W EA
RTS R:W NEXT W:W:M
stack(H) R:W
stack(L) Internal
operation,
1 state R:W *
4
TRAPA #x:2 R:W NEXT Internal
operation,
1 state W:W
stack(L) W:W
stack(H) W:W
stack(EXR) R:W:M VEC R:W
VEC+2 Internal
operation,
1 state R:W *
7
Reset
exception
handling R:W VEC R:W
VEC+2 Internal
operation,
1 state R:W *
5
Interrupt
exception
handling R:W *
6
Internal
operation,
1 state W:W
stack(L) W:W
stack(H) W:W
stack(EXR) R:W:M VEC R:W
VEC+2 Internal
operation,
1 state R:W *
7
A.5 Bus States during
Instruction Execution
Table A-6 Instruction
Execution Cycles
909, 911,
915, 916,
917