Renesas H8S/2318 series, Hardware Manual

Page: 204 / 1121

Rev. 5.00, 12/03, page 174 of 1088
Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH
is set to 1, an idle cycle is inserted at the start of the write cycle.
Figure 6-17 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output
floating time
Data
collision
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
I
T
1
Bus cycle B
T
2
HWR HWR
CS
(area A)
CS
(area B)
CS
(area A)
CS
(area B)
(a) Idle cycle not inserted
(ICIS0 = 0)
(b) Idle cycle inserted
(ICIS0 = 1 (initial value))
Figure 6-17 Example of Idle Cycle Operation (2)