Renesas H8S/2318 series, Hardware Manual

Page: 104 / 1121

Rev. 5.00, 12/03, page 74 of 1088
Bit 0
RAME
Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Versions Only)
Bit : 7 6 5 4 3 2 1 0
— — — — FLSHE — — —
Initial value : 0 0 0 0 0 0 0 0
R/W : — — — — R/W — — — (R/W)
*
Note:
*
R/W in the H8S/2319 F-ZTAT.
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0, and cannot be modified.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2 in the case of the H8S/2319 F-
ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT;
FCCS, FPCS, FECS, FKEY, FMATS, FTDAR, FVARC, FVADRR, FVADRE, FVADRH, and
FVADRL in the case of the H8S/2319C F-ZTAT). For details, see section 17, ROM.
Bit 3
FLSHE
Description
0 H8S/2319 F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and
H8S/2314 F-ZTAT
•
Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
(Initial value)
H8S/2319C F-ZTAT
•
Flash control registers are not selected for addresses H'FFFFC4 to H'FFFFCF
1 H8S/2319 F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and
H8S/2314 F-ZTAT
•
Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
H8S/2319C F-ZTAT
•
Flash control registers are selected for addresses H'FFFFC4 to H'FFFFCF