Renesas H8S/2318 series Hardware Manual Download Page 391

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Rev. 5.00, 12/03, page 361 of 1088

TCNT1

TCNT0

Channel 1

TGR1A

(speed period capture)

TGR0A (speed control period)

TGR1B

(position period capture)

TGR0C

(position control period)

TGR0B (pulse width capture)

TGR0D (buffer operation)

Channel 0

TCLKA

TCLKB

Edge

detection

circuit

−

Figure 9-33 Phase Counting Mode Application Example

Summary of Contents for H8S/2318 series

Page 1: ...Bit Single Chip Microcomputer H8S Family H8S 2300 Series Rev 5 00 The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revisions and additi...

Page 2: ......

Page 3: ...Renesas 16 Bit Single Chip Microcomputer H8S Family H8S 2300 Series H8S 2319 Group H8S 2318 Group Hardware Manual REJ09B0089 0500O...

Page 4: ...he information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inac...

Page 5: ...ialization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on...

Page 6: ...Rev 5 00 12 03 page vi of xxx...

Page 7: ...pplication systems Members of this audience are expected to understand the fundamentals of electrical circuits logical circuits and microcomputers Objective This manual was written to explain the hard...

Page 8: ...S 2000 Series Programming Manual ADE 602 083 Users manuals for development tools Manual Title ADE No C C Compiler Assembler Optimized Linkage Editor User s Manual ADE 702 247 Simulator Debugger for Wi...

Page 9: ...ions in Each Operating Mode Table 1 2 Pin Functions in Each Operating Mode 13 to 16 Table amended Pin No Type Symbol TFP 100B TFP 100G FP 100A 1 3 3 Pin Functions Table 1 3 Pin Functions 17 to 23 17 1...

Page 10: ...R W NEXT R W EA W W M stack H W W stack L BSR d 16 R W 2nd Internal operation 1 state R W EA W W M stack H W W stack L JMP aa 8 R W NEXT R W M aa 8 R W aa 8 Internal operation 1 state R W EA JSR ERn R...

Page 11: ...B HD6432317STF 100 pin TQFP TFP 100G Mask ROM version HD64F2317SF 100 pin QFP FP 100A HD64F2317 HD64F2317VTE 100 pin TQFP TFP 100B HD64F2317VTF 100 pin TQFP TFP 100G F ZTAT version HD64F2317VF 100 pin...

Page 12: ...Rev 5 00 12 03 page xii of xxx...

Page 13: ...2 4 1 Overview 32 2 4 2 General Registers 33 2 4 3 Control Registers 34 2 4 4 Initial Register Values 35 2 5 Data Formats 36 2 5 1 General Register Data Formats 36 2 5 2 Memory Data Formats 38 2 6 In...

Page 14: ...2 Mode 2 H8S 2319 F ZTAT and H8S 2319C F ZTAT Only 75 3 3 3 Mode 3 H8S 2319 F ZTAT and H8S 2319C F ZTAT Only 75 3 3 4 Mode 4 Expanded Mode with On Chip ROM Disabled 75 3 3 5 Mode 5 Expanded Mode with...

Page 15: ...egister Descriptions 112 5 2 1 System Control Register SYSCR 112 5 2 2 Interrupt Priority Registers A to K IPRA to IPRK 113 5 2 3 IRQ Enable Register IER 114 5 2 4 IRQ Sense Control Registers H and L...

Page 16: ...rol Register L BCRL 150 6 3 Overview of Bus Control 152 6 3 1 Area Partitioning 152 6 3 2 Bus Specifications 153 6 3 3 Memory Interfaces 154 6 3 4 Advanced Mode 155 6 3 5 Chip Select Signals 156 6 4 B...

Page 17: ...RA 189 7 2 6 DTC Transfer Count Register B CRB 190 7 2 7 DTC Enable Registers DTCER 190 7 2 8 DTC Vector Register DTVECR 191 7 2 9 Module Stop Control Register MSTPCR 192 7 3 Operation 192 7 3 1 Overv...

Page 18: ...t B 254 8 7 1 Overview 254 8 7 2 Register Configuration 255 8 7 3 Pin Functions 257 8 7 4 MOS Input Pull Up Function 259 8 8 Port C 260 8 8 1 Overview 260 8 8 2 Register Configuration 261 8 8 3 Pin Fu...

Page 19: ...r Counters TCNT 330 9 2 7 Timer General Registers TGR 330 9 2 8 Timer Start Register TSTR 331 9 2 9 Timer Synchro Register TSYR 331 9 2 10 Module Stop Control Register MSTPCR 332 9 3 Interface to Bus...

Page 20: ...OVF Setting 396 10 3 5 Operation with Cascaded Connection 397 10 4 Interrupts 398 10 4 1 Interrupt Sources and DTC Activation 398 10 4 2 A D Converter Activation 398 10 5 Sample Application 399 10 6 U...

Page 21: ...2 1 3 Pin Configuration 424 12 1 4 Register Configuration 425 12 2 Register Descriptions 426 12 2 1 Receive Shift Register RSR 426 12 2 2 Receive Data Register RDR 426 12 2 3 Transmit Shift Register T...

Page 22: ...iew 517 14 1 1 Features 517 14 1 2 Block Diagram 518 14 1 3 Pin Configuration 519 14 1 4 Register Configuration 520 14 2 Register Descriptions 521 14 2 1 A D Data Registers A to D ADDRA to ADDRD 521 1...

Page 23: ...peration 553 17 4 Overview of Flash Memory H8S 2318 F ZTAT H8S 2317 F ZTAT H8S 2315 F ZTAT H8S 2314 F ZTAT 557 17 4 1 Features 557 17 4 2 Overview 558 17 4 3 Flash Memory Operating Modes 559 17 4 4 On...

Page 24: ...7 Status Read Mode 604 17 11 8 Status Polling 605 17 11 9 Programmer Mode Transition Time 606 17 11 10 Notes on Memory Programming 606 17 12 Flash Memory Programming and Erasing Precautions 607 17 13...

Page 25: ...RAM Overlap 648 17 19 Interrupt Handling when Programming Erasing Flash Memory 649 17 20 Flash Memory Programmer Mode 650 17 20 1 Programmer Mode Setting 650 17 20 2 Socket Adapters and Memory Map 65...

Page 26: ...ad Mode 727 17 28 4 Auto Program Mode 727 17 28 5 Auto Erase Mode 728 17 28 6 Status Read Mode 728 17 28 7 Status Polling 729 17 28 8 Time Taken in Transition to PROM Mode 729 17 28 9 Notes on Using P...

Page 27: ...19 7 2 Hardware Standby Mode Timing 790 19 8 Clock Output Disabling Function 791 Section 20 Electrical Characteristics 793 20 1 Electrical Characteristics of Mask ROM Versions H8S 2319 H8S 2318 H8S 2...

Page 28: ...ristics 844 20 4 7 Usage Note Internal Voltage Step Down for the H8S 2319C F ZTAT 844 20 5 Usage Note 845 Appendix A Instruction Set 847 A 1 Instruction List 847 A 2 Instruction Codes 871 A 3 Operatio...

Page 29: ...Rev 5 00 12 03 page xxix of xxx Appendix D Pin States 1078 D 1 Port States in Each Mode 1078 Appendix E Product Lineup 1084 Appendix F Package Dimensions 1086...

Page 30: ...Rev 5 00 12 03 page xxx of xxx...

Page 31: ...8 300L or H8 300H Series On chip supporting functions required for system configuration include data transfer controller DTC bus masters ROM and RAM memory a 16 bit timer pulse unit TPU 8 bit timer wa...

Page 32: ...manipulation instructions CPU operating mode Advanced mode 16 Mbyte address space Bus controller Address space divided into 8 areas with bus specifications settable independently for each area Chip se...

Page 33: ...an mode selectable Sample and hold circuit A D conversion can be activated by external trigger or timer trigger D A converter Resolution 8 bits Output 2 channels I O ports 71 input output pins 8 input...

Page 34: ...F ZTAT H8S 2317 F ZTAT H8S 2315 F ZTAT H8S 2314 F ZTAT External Data Bus Mode CPU Operating Mode Description On Chip ROM Initial Value Maximum Value 1 2 3 4 Advanced Disabled 16 bits 16 bits 5 On chip...

Page 35: ...boot mode in the H8S 2319C F ZTAT For user boot mode in the H8S 2319C F ZTAT see table 17 52 in section 17 24 On Board Programming Modes 2 Boot mode in the H8S 2319 F ZTAT and H8S 2319C F ZTAT For bo...

Page 36: ...he current lineup Notes 1 Ta 40 C to 85 C wide range specifications is not available for condition C 2 In planning 3 The on chip debug function can be used with the E10 A emulator E10 A compatible ver...

Page 37: ...C F ZTAT both have 512 kbytes of on chip flash memory However the method for controlling the flash memory is different for the two LSIs When the on chip flash memory is enabled the registers parameter...

Page 38: ...OCB5 T M O 1 P10 TIOCA0 A 2 0 P11 TIOCB0 A 2 1 P12 TIOCC0 TCLKA A22 P13 TIOCD0 TCLKB A23 P14 TIOCA1 P15 TIOCB1 TCLKC P16 TIOCA2 P17 TIOCB2 TCLKD PG4 CS0 PG3 CS1 CS7 PG2 CS2 PG1 CS3 IRQ7 CS6 PG0 ADTRG...

Page 39: ...MD2 WDTOVF FWE EMLE V CL P23 TIOCD3 TMCI0 MD1 MD0 P22 TIOCC3 TMRI0 P21 TIOCB3 P20 TIOCA3 PA3 A19 PA2 A18 PA1 A17 PA0 A16 VSS PB7 A15 PB6 A14 PB5 A13 PB4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 VCC PC7 A7 P...

Page 40: ...74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB7 A15 PB6 A14 PB5 A13 PB4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 VCC PC7 A7 PC6 A6 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 VSS P...

Page 41: ...4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 VCC PC7 A7 PC6 A6 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 VSS PD7 D15 PD6 D14 PD5 D13 PD4 D12 PD3 D11 PF0 BREQ IRQ0 CS4 AVCC Vref P40 AN0 P41 AN1 P42 AN2 P43 AN3...

Page 42: ...CC PC7 A7 PC6 A6 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 VSS PD7 D15 PD6 D14 P40 AN0 P41 AN1 P42 AN2 P43 AN3 P44 AN4 P45 AN5 P46 AN6 DA0 P47 AN7 DA1 AVSS VSS P24 TIOCA4 TMRI1 P25 TIOCB4 TMCI1 P26 TI...

Page 43: ...OCA2 P16 TIOCA2 P16 TIOCA2 NC 6 8 P17 TIOCB2 TCLKD P17 TIOCB2 TCLKD P17 TIOCB2 TCLKD P17 TIOCB2 TCLKD NC 7 9 VSS VSS VSS VSS VSS 8 10 P30 TxD0 P30 TxD0 P30 TxD0 P30 TxD0 NC 9 11 P31 TxD1 P31 TxD1 P31...

Page 44: ...A9 PB1 A9 PB1 A9 43 45 A10 A10 PB2 A10 PB2 A10 44 46 A11 A11 PB3 A11 PB3 A11 45 47 A12 A12 PB4 A12 PB4 A12 46 48 A13 A13 PB5 A13 PB5 A13 47 49 A14 A14 PB6 A14 PB6 A14 48 50 A15 A15 PB7 A15 PB7 A15 49...

Page 45: ...PF2 IRQ2 VCC 75 77 PF1 BACK IRQ1 CS5 PF1 BACK IRQ1 CS5 PF1 BACK IRQ1 CS5 PF1 IRQ1 VSS 76 78 PF0 BREQ IRQ0 CS4 PF0 BREQ IRQ0 CS4 PF0 BREQ IRQ0 CS4 PF0 IRQ0 VSS 77 79 AVCC AVCC AVCC AVCC VCC 78 80 Vref...

Page 46: ...2 PG2 CS2 PG2 CS2 PG2 NC 96 98 PG3 CS1 CS7 PG3 CS1 CS7 PG3 CS1 CS7 PG3 NC 97 99 PG4 CS0 PG4 CS0 PG4 CS0 PG4 NC 98 100 VCC VCC VCC VCC VCC 99 1 P10 TIOCA0 A20 P10 TIOCA0 A20 P10 TIOCA0 A20 P10 TIOCA0 N...

Page 47: ...pply 0 V Internal voltage step down pin VCL 1 60 62 Output An external capacitor should be connected between this pin and GND 0 V Do not connect it to VCC Clock XTAL 66 68 Input Connects to a crystal...

Page 48: ...de The relation between the settings of pins MD2 to MD0 and the operating mode is shown below These pins should not be changed while the H8S 2319 and H8S 2318 Groups are operating H8S 2318 F ZTAT H8S...

Page 49: ...set STBY 64 66 Input Standby When this pin is driven low a transition is made to hardware standby mode BREQ 76 78 Input Bus request Used by an external bus master to issue a bus request to the H8S 231...

Page 50: ...e pins constitute a bidirectional data bus Bus control CS7 to CS0 94 to 97 75 76 96 to 99 77 78 Output Chip select Signals for selecting areas 7 to 0 AS 70 72 Output Address strobe When this pin is lo...

Page 51: ...CB3 TIOCC3 TIOCD3 54 to 56 59 56 to 58 61 I O Input capture output compare match A3 to D3 The TGR3A to TGR3D input capture input or output compare output or PWM output pins TIOCA4 TIOCB4 89 90 91 92 I...

Page 52: ...put This is the power supply pin for the A D converter and D A converter When the A D converter and D A converter are not used this pin should be connected to the system power supply VCC AVSS 87 89 In...

Page 53: ...32 to 25 I O Port D 7 An 8 bit I O port Input or output can be designated for each bit by means of the port D data direction register PDDDR PE7 to PE0 22 to 19 17 to 14 24 to 21 19 to 16 I O Port E A...

Page 54: ...Rev 5 00 12 03 page 24 of 1088...

Page 55: ...00H object programs General register architecture Sixteen 16 bit general registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty five basic instructions 8 16 32 bit arithmetic...

Page 56: ...ion 2 1 2 Differences between H8S 2600 CPU and H8S 2000 CPU The differences between the H8S 2600 CPU and the H8S 2000 CPU are as shown below Register configuration The MAC register is supported only b...

Page 57: ...ned multiply and divide instructions have been added Two bit shift instructions have been added Instructions for saving and restoring multiple registers have been added A test and set instruction has...

Page 58: ...s selected by the mode pins of the microcontroller Advanced Mode Address Space Linear access is provided to a 16 Mbyte maximum address space architecturally a maximum 16 Mbyte program area and a maxim...

Page 59: ...eset exception vector Reserved for system use Reserved Exception vector 1 Reserved H 00000010 H 00000008 H 00000007 Figure 2 1 Exception Vector Table Advanced Mode The memory indirect addressing mode...

Page 60: ...the stack in exception handling they are stored as shown in figure 2 2 When EXR is invalid it is not pushed onto the stack For details see section 4 Exception Handling a Subroutine Branch b Exception...

Page 61: ...of the H8S 2000 CPU The H8S 2000 CPU provides linear access to a maximum 16 Mbyte 4 Gbyte architecturally address space in advanced mode Advanced Mode H 00000000 H FFFFFFFF H 00FFFFFF Data area Progra...

Page 62: ...7L General Registers Rn and Extended Registers En Control Registers CR Legend Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition code register Interrupt ma...

Page 63: ...registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These regis...

Page 64: ...2 to I0 Bit 7 Trace Bit T Selects trace mode When this bit is cleared to 0 instructions are executed in sequence When this bit is set to 1 a trace exception is generated each time an instruction is ex...

Page 65: ...ORC instructions Bit 3 Negative Flag N Stores the value of the most significant bit sign bit of data Bit 2 Zero Flag Z Set to 1 to indicate zero data and cleared to 0 to indicate non zero data Bit 1 O...

Page 66: ...nd data The DAA and DAS decimal adjust instructions treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 7 shows the data formats in general registers 7 6 5 4 3...

Page 67: ...Rn General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Legend ERn En Rn RnH RnL MSB LSB 0 MSB LSB 15 Longword d...

Page 68: ...s but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches 7 6 5 4 3 2 1 0 7 0 MSB LSB MSB LSB MSB LSB Data...

Page 69: ...OT BWL 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR BWL 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control...

Page 70: ...control Block data transfer Shift Bit manipulation Branch Legend Size refers to the operand size B Byte W Word L Longword Notes 1 Cannot be used in the H8S 2319 and H8S 2318 Groups 2 Only register ER0...

Page 71: ...ion operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter...

Page 72: ...Cannot be used in the H8S 2357 Series MOVTPE B Cannot be used in the H8S 2357 Series POP W L SP Rn Pops a register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L S...

Page 73: ...y 1 or 2 Byte operands can be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal ad...

Page 74: ...ta and sets CCR bits according to the result NEG B W L 0 Rd Rd Takes the two s complement arithmetic complement of data in a general register EXTU W L Rd zero extension Rd Extends the lower 8 bits of...

Page 75: ...n a general register and another general register or immediate data NOT B W L Rd Rd Takes the one s complement of general register contents Shift operations SHAL SHAR B W L Rd shift Rd Performs an ari...

Page 76: ...ied bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND BIAND B...

Page 77: ...e bit number is specified by 3 bit immediate data BLD BILD B B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag bit No of EAd C Transfers the inverse...

Page 78: ...BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater...

Page 79: ...formed between them and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory Although CCR and EXR are 8 bit registers word size trans...

Page 80: ...else next Transfers a data block according to parameters set in general registers R4L or R4 ER5 and ER6 R4L or R4 size of block bytes ER5 starting source address ER6 starting destination address Exec...

Page 81: ...ive address extension and condition field op cc EA disp BRA d 16 etc Figure 2 9 Instruction Formats Examples 1 Operation Field Indicates the function of the instruction the addressing mode and the ope...

Page 82: ...Register indirect with pre decrement ERn ERn 5 Absolute address aa 8 aa 16 aa 24 aa 32 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 1 Register Direct R...

Page 83: ...ransfer instruction or 4 for longword transfer instruction For word or longword transfer instruction the register value should be even 5 Absolute Address aa 8 aa 16 aa 24 or aa 32 The instruction code...

Page 84: ...0 The PC value to which the displacement is added is the address of the first byte of the next instruction so the possible branching range is 126 to 128 bytes 63 to 64 words or 32766 to 32768 bytes 16...

Page 85: ...st significant bit is regarded as 0 causing data to be accessed or instruction code to be fetched at the address preceding the specified address For further information see section 2 5 2 Memory Data F...

Page 86: ...perand is general register contents Register indirect ERn 2 Register indirect with displacement d 16 ERn or d 32 ERn 3 Register indirect with pre decrement ERn 4 General register contents General regi...

Page 87: ...6 xx 32 31 0 8 7 Operand is immediate data No Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA aa 24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op...

Page 88: ...16 PC 8 Memory indirect aa 8 Advanced mode No Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA 23 23 0 31 8 7 0 disp abs H 000000 31 0 24 23 31 0 24 23 op dis...

Page 89: ...pped Exception handling state A transient state in which the CPU changes the normal processing flow in response to a reset interrupt or trap instruction Program execution state The CPU executes progra...

Page 90: ...chdog timer overflows From any state a transition to hardware standby mode occurs when STBY goes low SLEEP instruction with SSBY 0 SLEEP instruction with SSBY 1 Interrupt request End of bus request Bu...

Page 91: ...hronized with clock Exception handling starts immediately after a low to high transition at the RES pin or when the watchdog timer overflows Trace End of instruction execution or end of exception hand...

Page 92: ...o 0 and trace mode is cleared Interrupt masks are not affected The T bit saved on the stack retains its value of 1 and when the RTE instruction is executed to return from the trace exception handling...

Page 93: ...PU halts There is one other bus master in addition to the CPU the data transfer controller DTC For further details refer to section 6 Bus Controller 2 8 6 Power Down State The power down state include...

Page 94: ...their existing states 3 Hardware Standby Mode A transition to hardware standby mode is made when the STBY pin goes low In hardware standby mode the CPU and clock halt and all MCU operations stop The...

Page 95: ...nternal write signal Internal data bus Bus cycle T1 Address Read data Write data Read access Write access Figure 2 14 On Chip Memory Access Cycle Bus cycle T1 Unchanged Address bus AS RD HWR LWR Data...

Page 96: ...nding on the particular internal I O register being accessed Figure 2 16 shows the access timing for the on chip supporting modules Figure 2 17 shows the pin states Bus cycle T1 T2 Address Read data W...

Page 97: ...6 bit data bus width in a two state or three state bus cycle In three state access wait states can be inserted For further details refer to section 6 Bus Controller 2 10 Usage Note 2 10 1 TAS Instruct...

Page 98: ...Rev 5 00 12 03 page 68 of 1088...

Page 99: ...in table 3 1 Table 3 1 lists the MCU operating modes Table 3 1 MCU Operating Mode Selection H8S 2318 F ZTAT H8S 2317 F ZTAT H8S 2315 F ZTAT and H8S 2314 F ZTAT MCU CPU External Data Bus Operating Mode...

Page 100: ...0 11 14 and 15 are boot modes and user program modes in which the flash memory can be programmed and erased For details see section 17 ROM The H8S 2318 F ZTAT H8S 2317 F ZTAT H8S 2315 F ZTAT and H8S 2...

Page 101: ...s for information on user program mode 3 Only modes 4 and 5 are provided in the ROMless versions The CPU s architecture allows for 4 Gbytes of address space but the Mask ROM ROMless version H8S 2319 F...

Page 102: ...ons In the mask ROM and ROMless versions this register will return an undefined value if read and cannot be modified 3 2 Register Descriptions 3 2 1 Mode Control Register MDCR Bit 7 6 5 4 3 2 1 0 MDS2...

Page 103: ...of interrupts by I bit Initial value 1 Setting prohibited 1 0 2 Control of interrupts by I2 to I0 bits and IPR 1 Setting prohibited Bit 3 NMI Edge Select NMIEG Selects the valid edge of the NMI inter...

Page 104: ...isters FLMCR1 FLMCR2 EBR1 and EBR2 in the case of the H8S 2319 F ZTAT H8S 2318 F ZTAT H8S 2317 F ZTAT H8S 2315 F ZTAT and H8S 2314 F ZTAT FCCS FPCS FECS FKEY FMATS FTDAR FVARC FVADRR FVADRE FVADRH and...

Page 105: ...tion in this mode is the same as in advanced expanded mode with on chip ROM enabled 3 3 3 Mode 3 H8S 2319 F ZTAT and H8S 2319C F ZTAT Only This is a flash memory boot mode See section 17 ROM for detai...

Page 106: ...an access a 16 Mbyte address space in advanced mode The on chip ROM is enabled Pins P13 to P10 ports A B and C function as input ports immediately after a reset These pins can be set to output address...

Page 107: ...nd H8S 2314 F ZTAT Only Modes 12 and 13 are not supported in the H8S 2319 and H8S 2318 Groups and must not be set 3 3 12 Mode 14 H8S 2318 F ZTAT H8S 2317 F ZTAT H8S 2315 F ZTAT and H8S 2314 F ZTAT Onl...

Page 108: ...F3 P C 1 P C 1 P C 1 P PF5 PF4 C C C PF2 to PF0 P 1 C P 1 C P 1 C Legend P I O port T Timer I O A Address bus output D Data bus I O C Control signals clock I O Notes 1 After reset 2 Not used on ROMles...

Page 109: ...registers External address space H 000000 H 000000 H 080000 H FF7400 H FF7400 H FFDC00 H FFDC00 H FFFBFF H FFFFFF H FFFE50 H FFFF07 H FFFF28 On chip ROM external address space 1 H 010000 H 010000 H 0...

Page 110: ...access the reserved area in addresses H FF7400 to H FFDBFF 5 Do not access the reserved area Internal I O registers On chip ROM On chip ROM reserved area 2 5 External address space External address sp...

Page 111: ...E bit in SYSCR to 0 4 Do not access the reserved areas On chip ROM On chip ROM reserved area 2 4 External address space Internal I O registers External address space Internal I O registers Internal I...

Page 112: ...E bit in SYSCR to 0 4 Do not access the reserved areas Internal I O registers On chip ROM On chip ROM reserved area 2 4 External address space External address space Internal I O registers External ad...

Page 113: ...SCR to 0 5 Do not access the reserved area Internal I O registers On chip ROM On chip ROM reserved area 3 5 External address space External address space Internal I O registers External address space...

Page 114: ...sters External address space H 000000 H 000000 H 040000 H 03FFFF H FFDC00 H FFFBFF H FFFFFF H FFFE50 H FFFF07 H FFFF28 On chip ROM external address space 1 H 010000 H 010000 H FFDC00 H FFFC00 H FFFE50...

Page 115: ...I O registers External address space H 000000 H 000000 H 040000 H 03FFFF H FFDC00 H FFFBFF H FFFFFF H FFFE50 H FFFF07 H FFFF28 On chip ROM external address space 1 H 010000 H 010000 H FFDC00 H FFFC00...

Page 116: ...isters On chip ROM On chip ROM reserved area 2 4 External address space External address space Internal I O registers External address space On chip RAM 3 On chip RAM Internal I O registers External a...

Page 117: ...00 H 040000 H FFDC00 H FFDC00 H FFFBFF H FFFFFF H FFFE50 H FFFF07 H FFFF28 On chip ROM external address space 1 Reserved area 4 Reserved area 4 external address space 1 H 010000 H 010000 H 020000 H 02...

Page 118: ...00 H 040000 H FFDC00 H FFDC00 H FFFBFF H FFFFFF H FFFE50 H FFFF07 H FFFF28 On chip ROM external address space 1 Reserved area 4 Reserved area 4 external address space 1 H 010000 H 010000 H 020000 H 02...

Page 119: ...al I O registers On chip ROM Reserved area 3 External address space External address space Internal I O registers External address space On chip RAM 2 On chip RAM Internal I O registers External addre...

Page 120: ...ss the reserved area in addresses H 060000 to H 07FFFF 5 Do not access the reserved area Internal I O registers On chip ROM On chip ROM reserved area 2 5 External address space External address space...

Page 121: ...space Internal I O registers Internal I O registers H 000000 H 000000 H FFFC00 H FFDC00 H FFFFFF H 080000 H 060000 H 060000 H 010000 H FFFBFF H FFDC00 H FFFFFF H FFFF08 H FFFE50 H FFFF07 H FFFF28 H F...

Page 122: ...address space Internal I O registers Internal I O registers H 000000 H 000000 H FFFC00 H FFDC00 H FFFFFF H 080000 H 060000 H 060000 H 010000 H FFFBFF H FFDC00 H FFFFFF H FFFF08 H FFFE50 H FFFF07 H FF...

Page 123: ...n addresses H 060000 to H 07FFFF 5 Do not access the reserved areas Internal I O registers On chip ROM On chip ROM reserved area 2 5 External address space External address space Internal I O register...

Page 124: ...O registers Internal I O registers H 000000 H 000000 H FFFC00 H FFEC00 H FFFFFF H 080000 H 060000 H 060000 H 010000 H FFFBFF H FFEC00 Reserved area 5 H FFDC00 H FFDC00 H FFFFFF H FFFF08 H FFFE50 H FF...

Page 125: ...ternal I O registers Internal I O registers H 000000 H 000000 H FFFC00 H FFEC00 Reserved area 5 H FFDC00 H FFFFFF H 080000 H 060000 H 060000 H 010000 H FFFBFF H FFEC00 H FFFFFF H FFFF08 H FFFE50 H FFF...

Page 126: ...area 3 External address space External address space Internal I O registers External address space On chip RAM 2 On chip RAM Reserved area 3 Internal I O registers External address space Internal I O...

Page 127: ...ed area 4 Reserved area 4 Reserved area 4 External address space External address space Internal I O registers External address space On chip RAM 3 On chip RAM Reserved area 4 Internal I O registers E...

Page 128: ...Rev 5 00 12 03 page 98 of 1088...

Page 129: ...tion or exception handling ends if the trace T bit is set to 1 Interrupt Starts when execution of the current instruction or exception handling ends if an interrupt request has been issued 2 Low Trap...

Page 130: ...NMI IRQ7 to IRQ0 Internal interrupts interrupts from on chip supporting modules Figure 4 1 Exception Sources In modes 6 and 7 the on chip ROM available for use after a power on reset is the 64 kbyte a...

Page 131: ...s 8 H 0020 to H 0023 9 H 0024 to H 0027 10 H 0028 to H 002B 11 H 002C to H 002F Reserved for system use 12 H 0030 to H 0033 13 H 0034 to H 0037 14 H 0038 to H 003B 15 H 003C to H 003F External interru...

Page 132: ...et Sequence The chip enters the reset state when the RES pin goes low To ensure that the chip is reset hold the RES pin low for at least 20 ms at power up To reset the chip during operation hold the R...

Page 133: ...tack pointer SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset Since t...

Page 134: ...fected by interrupt masking Table 4 3 shows the state of CCR and EXR after execution of trace exception handling Interrupts are accepted even within the trace exception handling routine The T bit save...

Page 135: ...e has a separate vector address NMI is the highest priority interrupt Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control modes and can assign inte...

Page 136: ...CCR and EXR after execution of trap instruction exception handling Table 4 4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 2 1 0 L...

Page 137: ...Use the following instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 5 shows an example of what happens...

Page 138: ...Rev 5 00 12 03 page 108 of 1088...

Page 139: ...y registers IPRs are provided for setting interrupt priorities Eight priority levels can be set for each module for all interrupts except NMI NMI is assigned the highest priority level of 8 and can be...

Page 140: ...to TEI INTM1 INTM0 NMIEG NMI input unit IRQ input unit ISR ISCR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU Legend ISCR IRQ sense control...

Page 141: ...1 H FF39 IRQ sense control register H ISCRH R W H 00 H FF2C IRQ sense control register L ISCRL R W H 00 H FF2D IRQ enable register IER R W H 00 H FF2E IRQ status register ISR R W 2 H 00 H FF2F Interru...

Page 142: ...reset and in hardware standby mode It is not initialized in software standby mode Bits 5 and 4 Interrupt Control Mode 1 and 0 INTM1 INTM0 These bits select one of two interrupt control modes for the i...

Page 143: ...registers set a priority levels 7 to 0 for each interrupt source other than NMI The IPR registers are initialized to H 77 by a reset and in hardware standby mode Bits 7 and 3 Reserved Read only bits a...

Page 144: ...vel set by the interrupt mask bits I2 to I0 in the extend register EXR in the CPU and if the priority level of the interrupt is higher than the set mask level an interrupt request is issued to the CPU...

Page 145: ...able register that selects rising edge falling edge or both edge detection or level sensing for the input at pins IRQ7 to IRQ0 ISCR is initialized to H 0000 by a reset and in hardware standby mode Bit...

Page 146: ...ading IRQnF flag when IRQnF 1 then writing 0 to IRQnF flag When interrupt exception handling is executed when low level detection is set IRQnSCB IRQnSCA 0 and IRQn input is high When IRQn interrupt ex...

Page 147: ...ge or a falling edge on the NMI pin The vector number for NMI interrupt exception handling is 7 IRQ7 to IRQ0 Interrupts Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0 In...

Page 148: ...tatus and enable bits that select enabling or disabling of these interrupts If both of these are set to 1 for a particular interrupt source an interrupt request is issued to the interrupt controller T...

Page 149: ...for system 2 H 0008 use 3 H 000C 4 H 0010 Trace 5 H 0014 Reserved for system use 6 H 0018 NMI External pin 7 H 001C Trap instruction 8 H 0020 4 sources 9 H 0024 10 H 0028 11 H 002C Reserved for syste...

Page 150: ...IPRD4 Reserved 26 H 0068 IPRD2 to IPRD0 Reserved 27 H 006C IPRE6 to IPRE4 ADI A D conversion end A D 28 H 0070 IPRE2 to IPRE0 Reserved 29 H 0074 30 H 0078 31 H 007C TGI0A TGR0A input capture compare...

Page 151: ...derflow 1 43 H 00AC TGI2A TGR2A input capture compare match TPU channel 2 44 H 00B0 IPRG6 to IPRG4 TGI2B TGR2B input capture compare match 45 H 00B4 TCI2V overflow 2 46 H 00B8 TCI2U underflow 2 47 H 0...

Page 152: ...nderflow 4 59 H 00EC TGI5A TGR5A input capture compare match TPU channel 5 60 H 00F0 IPRH2 to IPRH0 TGI5B TGR5B input capture compare match 61 H 00F4 TCI5V overflow 5 62 H 00F8 TCI5U underflow 5 63 H...

Page 153: ...013C ERI0 receive error 0 SCI channel 0 80 H 0140 IPRJ2 to IPRJ0 RXI0 receive data full 0 81 H 0144 TXI0 transmit data empty 0 82 H 0148 TEI0 transmit end 0 83 H 014C ERI1 receive error 1 SCI channel...

Page 154: ...enable bits are set to 1 are controlled by the interrupt controller Table 5 5 shows the interrupt control modes The interrupt controller performs interrupt control according to the interrupt control m...

Page 155: ...rupt control mode 0 I Figure 5 4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control In interrupt control mode 0 interrupt acceptance is controlled by the I bit in CCR Table 5 6...

Page 156: ...ed and a vector number is generated If the same value is set for IPR acceptance of multiple interrupts is enabled and so only the interrupt source with the highest priority according to the preset def...

Page 157: ...t is accepted and other interrupt requests are held pending 3 Interrupt requests are sent to the interrupt controller the highest ranked interrupt according to the priority system is accepted and othe...

Page 158: ...terrupt generated NMI IRQ0 IRQ1 TEI1 I 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5 5 Flowchart of Proced...

Page 159: ...shown in table 5 4 is selected 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR An interrupt request with a priority no higher than the mask...

Page 160: ...7 interrupt Mask level 6 or below Save PC CCR and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt Mask level 0 Yes Yes No...

Page 161: ...errupt Exception Handling Sequence Figure 5 7 shows the interrupt exception handling sequence The example shown is for the case where interrupt control mode 0 is set in advanced mode and the program a...

Page 162: ...nternal read signal Internal write signal Internal data bus 3 1 2 4 3 5 7 Instruction prefetch address Not executed This is the contents of the saved PC the return address Instruction code Not execute...

Page 163: ...until executing instruction ends 2 1 to 19 2 SI 1 to 19 2 SI 3 PC CCR EXR stack save 2 SK 3 SK 4 Vector fetch 2 SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 6 Internal processing 4 2 2 Total using on chip...

Page 164: ...be executed on completion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for the higher priority inte...

Page 165: ...e for a 3 state period after the CPU has updated the mask level with an LDC ANDC ORC or XORC instruction 5 5 4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the...

Page 166: ...to activate the DTC see section 7 Data Transfer Controller 5 6 2 Block Diagram Figure 5 9 shows a block diagram of the DTC and interrupt controller Selection circuit DTCER DTVECR Control logic Determ...

Page 167: ...ee section 7 3 3 DTC Vector Table for the respective priorities Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source the DTC data transfer is perform...

Page 168: ...Rev 5 00 12 03 page 138 of 1088...

Page 169: ...rnal space as 8 areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM interfaces can be set Basic bus interface Chip select CS0 to CS7 can be output for areas 0 to 7 8...

Page 170: ...R ASTCR BCRH BCRL Internal address bus CS0 to CS7 External bus control signals BREQ BACK BREQO Internal control signals Wait controller WCRH WCRL Bus mode signal Bus arbiter CPU bus request signal DTC...

Page 171: ...put Strobe signal indicating that area 1 is selected Chip select 2 CS2 Output Strobe signal indicating that area 2 is selected Chip select 3 CS3 Output Strobe signal indicating that area 3 is selected...

Page 172: ...n R W Reset Address 1 Bus width control register ABWCR R W H FF H 00 2 H FED0 Access state control register ASTCR R W H FF H FED1 Wait control register H WCRH R W H FF H FED2 Wait control register L W...

Page 173: ...data bus width for the external memory space The bus width for on chip memory and internal I O registers is fixed regardless of the settings in ABWCR After a reset and in hardware standby mode ABWCR i...

Page 174: ...I O registers is fixed regardless of the settings in ASTCR ASTCR is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 0 Area 7 to 0 A...

Page 175: ...he AST7 bit in ASTCR is set to 1 Bit 7 W71 Bit 6 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is acce...

Page 176: ...rnal space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed Initial value Bits 1 and 0 Area 4 Wait Control 1 and 0 W41 W40 These bits select the number of pro...

Page 177: ...rea 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed Initial value Bits 5 and 4 Area 2 Wa...

Page 178: ...m wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1 Bit 1 W01 Bit 0 W00 Description 0 0 Program wait not inserted when external space area 0 is accessed 1 1...

Page 179: ...nserted between bus cycles when successive external read and external write cycles are performed Bit 6 ICIS0 Description 0 Idle cycle not inserted in case of successive external read and external writ...

Page 180: ...col selection of the area division unit and enabling or disabling of WAIT pin input BCRL is initialized to H 3C by a reset and in hardware standby mode It is not initialized in software standby mode B...

Page 181: ...03FFFF 2 are external addresses in external expanded mode or reserved area 1 in single chip mode Initial value Notes 1 Do not access a reserved area 2 H 010000 to H 03FFFF in the H8S 2318 H 010000 to...

Page 182: ...ea units Figure 6 2 shows an outline of the area partitioning Chip select signals CS0 to CS7 can be output for each area Area 0 2 Mbytes H 000000 H FFFFFF H 1FFFFF H 200000 Area 1 2 Mbytes H 3FFFFF H...

Page 183: ...is designated for 16 bit access 16 bit bus mode is set When the burst ROM interface is designated 16 bit bus mode is always set Number of Access States Two or three access states can be selected with...

Page 184: ...0 1 0 0 3 0 1 1 1 0 2 1 3 6 3 3 Memory Interfaces The chip s memory interfaces comprise a basic bus interface that allows direct connection of ROM SRAM and so on and a burst ROM interface that allows...

Page 185: ...ccessed the CS0 signal can be output Either basic bus interface or burst ROM interface can be selected for area 0 Areas 1 to 6 In external expansion mode all of area 1 to 6 is external space When area...

Page 186: ...CSn pin In ROM disabled expansion mode the CS0 pin is placed in the output state after a power on reset Pins CS1 to CS7 are placed in the input state after a power on reset and so the corresponding DD...

Page 187: ...rding to the bus specifications for the area being accessed 8 bit access space or 16 bit access space and the data size 8 Bit Access Space Figure 6 4 illustrates data alignment control for the 8 bit a...

Page 188: ...one word and a longword transfer instruction is executed as two word transfer instructions In byte access whether the upper or lower data bus is used is determined by whether the address is even or od...

Page 189: ...f the data bus and the LWR signal for the lower half Table 6 4 Data Buses Used and Valid Strobes Area Access Size Read Write Address Valid Strobe Upper Data Bus D15 to D8 Lower Data Bus D7 to D0 Byte...

Page 190: ...hen an 8 bit access space is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states cannot be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7...

Page 191: ...it access space is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states can be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7 to D0 Invali...

Page 192: ...upper half D15 to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states cannot be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D...

Page 193: ...8 Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write Note n 0 to 7 High Figure 6 9 Bus Timing for 16 Bit 2 State Access S...

Page 194: ...ge 164 of 1088 Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note n 0 to 7 Figure 6 10 Bus Timing for 16 Bit 2 State Access Spa...

Page 195: ...upper half D15 to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states can be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7 t...

Page 196: ...Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write High Note n 0 to 7 T3 Figure 6 12 Bus Timing for 16 Bit 3 State Access...

Page 197: ...e 167 of 1088 Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note n 0 to 7 T3 Figure 6 13 Bus Timing for 16 Bit 3 State Access S...

Page 198: ...ate access space according to the settings of WCRH and WCRL Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin When external space is accessed in thi...

Page 199: ...dress bus AS RD Data bus Read data Read HWR LWR Write data Write Note indicates the timing of WAIT pin sampling WAIT Data bus T2 Tw Tw Tw T3 By WAIT pin Figure 6 14 Example of Wait State Insertion Tim...

Page 200: ...burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR Also when the AST0 bit is set to 1 wait state insertion is possible One or two states can be selected for the burst cycl...

Page 201: ...ge 171 of 1088 T1 Address bus CS0 AS Data bus T2 T3 T1 T2 T1 Full access T2 RD Burst access Only lower address changed Read data Read data Read data Figure 6 15 a Example of Burst ROM Access Timing Wh...

Page 202: ...ad data Figure 6 15 b Example of Burst ROM Access Timing When AST0 BRSTS1 0 6 5 3 Wait Control As with the basic bus interface either program wait insertion or pin wait insertion using the WAIT pin ca...

Page 203: ...serted at the start of the second read cycle This is enabled in advanced mode Figure 6 16 shows an example of the operation in this case In this example bus cycle A is a read cycle from ROM with a lon...

Page 204: ...e B is a CPU write cycle In a an idle cycle is not inserted and a collision occurs in cycle B between the read data from ROM and the CPU write data In b an idle cycle is inserted and a data collision...

Page 205: ...l and the bus cycle B CS signal Setting idle cycle insertion as in b however will prevent any overlap between the RD and CS signals In the initial state after reset release idle cycle insertion b is s...

Page 206: ...n States in Idle Cycle Table 6 5 shows the pin states in an idle cycle Table 6 5 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 High impedance CSn High AS High...

Page 207: ...trol signals are placed in the high impedance state establishing the external bus released state In the external bus released state an internal bus master can perform accesses using the internal bus W...

Page 208: ...Table 6 6 shows the pin states in the external bus released state Table 6 6 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn High impedance AS High...

Page 209: ...te Output only when BREQOE is set to 1 Low level of BREQ pin is sampled at rise of T2 state BACK pin is driven low at end of CPU read cycle releasing bus to external bus master BREQ pin state is still...

Page 210: ...session of the bus and begins its operation 6 8 2 Operation The bus arbiter detects the bus masters bus request signals and if the bus is requested sends a bus request acknowledge signal to the bus ma...

Page 211: ...during Instruction Execution for timings at which the bus is not transferred If the CPU is in sleep mode it transfers the bus immediately DTC The DTC sends the bus arbiter a request for the bus when a...

Page 212: ...Rev 5 00 12 03 page 182 of 1088...

Page 213: ...repeat and block transfer modes available Incrementing decrementing and fixing of source and destination addresses can be selected Direct specification of 16 Mbyte address space possible 24 bit transf...

Page 214: ...AME bit in SYSCR must be set to 1 Interrupt request Interrupt controller DTC Internal address bus DTC activation request Control logic Register information MRA MRB CRA CRB DAR SAR CPU interrupt reques...

Page 215: ...defined 3 DTC transfer count register A CRA 2 Undefined 3 DTC transfer count register B CRB 2 Undefined 3 DTC enable registers DTCER R W H 00 H FF30 to H FF34 DTC vector register DTVECR R W H 00 H FF3...

Page 216: ...to be incremented decremented or left fixed after a data transfer Bit 7 SM1 Bit 6 SM0 Description 0 SAR is fixed 1 0 SAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 1 SAR is decremen...

Page 217: ...in repeat mode or block transfer mode Bit 1 DTS Description 0 Destination side is repeat area or block area 1 Source side is repeat area or block area Bit 0 DTC Data Transfer Size Sz Specifies the siz...

Page 218: ...DTC Interrupt Select DISEL Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer Bit 6 DISEL Description 0 After a data transfer ends the CPU interrupt is disab...

Page 219: ...2 5 DTC Transfer Count Register A CRA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fi...

Page 220: ...The DTC enable registers comprise six 8 bit readable writable registers DTCERA to DTCERF with bits corresponding to the interrupt sources that can activate the DTC These bits enable or disable DTC ser...

Page 221: ...pt DTVECR is initialized to H 00 by a reset and in hardware standby mode Bit 7 DTC Software Activation Enable SWDTE Enables or disables DTC activation by software Bit 7 SWDTE Description 0 DTC softwar...

Page 222: ...fies the DTC module stop mode Bit 14 MSTP14 Description 0 DTC module stop mode cleared Initial value 1 DTC module stop mode set 7 3 Operation 7 3 1 Overview When activated the DTC reads register infor...

Page 223: ...register information Data transfer Write register information Clear activation flag CHNE 1 End No No No No No Yes Yes Yes Yes Yes Transfer counter 0 or DISEL 1 Clear DTCER Interrupt exception handling...

Page 224: ...CPU 1 1 0 Not 0 Ends at 1st transfer 1 1 0 0 0 Not 0 Ends at 2nd transfer 0 0 0 Ends at 2nd transfer 0 1 Interrupt request to CPU 1 1 1 Not 0 Ends at 1st transfer Interrupt request to CPU The DTC tra...

Page 225: ...transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers 1 to 256 the initial state resumes and operation conti...

Page 226: ...e activation source flag in the case of RXI0 for example is the RDRF flag of SCI0 Table 7 4 Activation Source and DTCER Clearance Activation Source When the DISEL Bit Is 0 and the Specified Number of...

Page 227: ...ween DTC vector addresses and register information Table 7 5 shows the correspondence between activation vector addresses and DTCER bits When the DTC is activated by software the vector address is obt...

Page 228: ...TCEA2 IRQ6 22 H 042C DTCEA1 IRQ7 23 H 042E DTCEA0 ADI A D conversion end A D 28 H 0438 DTCEB6 TGI0A GR0A compare match input capture TPU channel 0 32 H 0440 DTCEB5 TGI0B GR0B compare match input captu...

Page 229: ...470 DTCEC1 TGI4B GR4B compare match input capture 57 H 0472 DTCEC0 TGI5A GR5A compare match input capture TPU channel 5 60 H 0478 DTCED5 TGI5B GR5B compare match input capture 61 H 047A DTCED4 CMIA0 6...

Page 230: ...DAR CRA and CRB registers in that order from the start address of the register information contents of the vector address In the case of chain transfer register information should be located in consec...

Page 231: ...lists the register information in normal mode and figure 7 6 shows the memory map in normal mode Table 7 6 Register Information in Normal Mode Name Abbreviation Function DTC source address register S...

Page 232: ...nd therefore CPU interrupts cannot be requested when DISEL 0 Table 7 7 lists the register information in repeat mode and figure 7 7 shows the memory map in repeat mode Table 7 7 Register Information i...

Page 233: ...d or left fixed From 1 to 65 536 transfers can be specified Once the specified number of transfers have ended a CPU interrupt is requested Table 7 8 lists the register information in block transfer mo...

Page 234: ...Rev 5 00 12 03 page 204 of 1088 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 7 8 Memory Map in Block Transfer Mode...

Page 235: ...MRA and MRB which define data transfers can be set independently Figure 7 9 shows the memory map for chain transfer Source Source Destination Destination DTC vector address Register information start...

Page 236: ...sfer information read Transfer information write Data transfer Read Write Figure 7 10 DTC Operation Timing Example in Normal Mode or Repeat Mode Read Write Read Write Data transfer Transfer informatio...

Page 237: ...Operation Timing Example of Chain Transfer 7 3 10 Number of DTC Execution States Table 7 9 lists execution phases for a single DTC data transfer and table 7 10 shows the number of states required for...

Page 238: ...2 2 3 m 2 3 m Word data write SL 1 1 4 2 4 6 2m 2 3 m Internal operation SM 1 The number of execution states is calculated from the formula below Note that means the sum of all transfers activated by...

Page 239: ...is cleared to 0 and a CPU interrupt is requested If the DTC is to continue transferring data set the DTCE bit to 1 Activation by Software The procedure for using the DTC with software activation is a...

Page 240: ...onding bit in DTCER to 1 4 Set the SCI to the appropriate receive mode Set the RIE bit in SCR to 1 to enable the reception data full RXI interrupt Since the generation of a receive error during the SC...

Page 241: ...first data transfer Use the upper 8 bits of DAR in the first register information area as the transfer destination Set CHNE DISEL 0 If the above input buffer is specified as H 200000 to H 21FFFF set t...

Page 242: ...page 212 of 1088 First data transfer register information Second data transfer register information Chain transfer counter 0 Upper 8 bits of DAR Input buffer Input circuit Figure 7 13 Chain Transfer...

Page 243: ...80 in CRA Set 1 H 0001 in CRB 2 Set the start address of the register information at the DTC vector address H 04C0 3 Check that the SWDTE bit in DTVECR is 0 Check that there is currently no transfer a...

Page 244: ...n the MSTP14 bit in MSTPCR is set to 1 the DTC clock stops and the DTC enters the module stop state However 1 cannot be written to the MSTP14 bit while the DTC is operating On Chip RAM The MRA MRB SAR...

Page 245: ...T used to read the pin states Ports A to E have a built in MOS pull up function and in addition to DR and DDR have a MOS input pull up control register PCR to control the on off state of MOS input pul...

Page 246: ...DDR 1 and A23E to A20E 1 Address output When DDR 1 and A23E to A20E 0 DR value output Port 2 8 bit I O port Schmitt triggered input P27 TIOCB5 TMO1 P26 TIOCA5 TMO0 P25 TIOCB4 TMCI1 P24 TIOCA4 TMRI1 P2...

Page 247: ...t pull up Open drain output capability PA3 A19 to PA0 A16 Address output When DDR 0 after reset input ports When DDR 1 address output I O ports Port B 8 bit I O port Built in MOS input pull up PB7 A15...

Page 248: ...n 16 bit bus mode LWR output also functioning as interrupt input pin IRQ3 I O port also functioning as interrupt input pins IRQ3 to IRQ0 PF2 WAIT IRQ2 BREQO When WAITE 0 BRLE 0 BREQOE 0 after reset I...

Page 249: ...O port When DDR 1 and CS25E 1 Also functions as CS2 output I O port also functions as interrupt input pins IRQ7 IRQ6 and A D converter input pin ADTRG PG1 CS3 IRQ7 CS6 I O port When DDR 1 CS25E 1 and...

Page 250: ...input P14 I O TIOCA1 I O P13 I O TIOCD0 I O TCLKB input A23 output P12 I O TIOCC0 I O TCLKA input A22 output P11 I O TIOCB0 I O A21 output P10 I O TIOCA0 I O A20 output Port 1 Note Modes 6 and 7 are n...

Page 251: ...vidual bits of which specify input or output for the pins of port 1 P1DDR cannot be read if it is an undefined value will be read Setting a P1DDR bit to 1 makes the corresponding port 1 pins output pi...

Page 252: ...e determined by the pin states as P1DDR and P1DR are initialized PORT1 retains its prior state after in software standby mode Port Function Control Register 1 PFCR1 Bit 7 6 5 4 3 2 1 0 CSS17 CSS36 PF1...

Page 253: ...lue Bit 1 Address 21 Enable A21E Enables or disables address output 21 A21 This bit is valid in modes 4 to 6 Bit 1 A21E Description 0 P11DR is output when P11DDR 1 1 A21 is output when P11DDR 1 Initia...

Page 254: ...low 1 Table Below 2 P17DDR 0 1 Pin function TIOCB2 output P17 input P17 output TIOCB2 input 1 TCLKD input 2 TPU Channel 2 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 01 B 0010 B 0011 IOB3 to IOB0 B 0000 B...

Page 255: ...nnel 2 Setting Table Below 1 Table Below 2 P16DDR 0 1 Pin function TIOCA2 output P16 input P16 output TIOCA2 input 1 TPU Channel 2 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01 B 001 B 0011 B 0011 IOA3 t...

Page 256: ...output P15 input P15 output TIOCB1 input 1 TCLKC input 2 TPU Channel 1 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 01 B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1 B 0001 to B 0011 B 0101 to B 0111 B 00 O...

Page 257: ...Setting Table Below 1 Table Below 2 P14DDR 0 1 Pin function TIOCA1 output P14 input P14 output TIOCA1 input 1 TPU Channel 1 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01 B 001 B 0010 B 0011 IOA3 to IOA0...

Page 258: ...0 1 0 1 Pin function TIOCD0 output P13 input P13 output TIOCD0 output TIOCD0 output A23 output P13 input P13 output A23 output TIOCD0 input 2 TIOCD0 input 2 TCLKB input 3 TPU Channel 0 Setting 2 1 2...

Page 259: ...OCC0 output TIOCC0 output A22 output P12 input P12 output A22 output TIOCC0 input 2 TIOCC0 input 2 TCLKA input 3 TPU Channel 0 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001 B 0010 B 0011 IOC3 to IOC0 B...

Page 260: ...ble Below 2 Table Below 1 Table Below 2 P11DDR 0 1 0 1 0 1 A21E 0 1 0 1 Pin function TIOCB0 output P11 input P11 output TIOCB0 output TIOCB0 output A21 output P11 input P11 output A21 output TIOCB0 in...

Page 261: ...able Below 2 P10DDR 0 1 0 1 0 1 A20E 0 1 0 1 Pin function TIOCA0 output P10 input P10 output TIOCA0 output TIOCA0 output A20 output P10 input P10 output A20 output TIOCA0 input 2 TIOCA0 input 2 TPU Ch...

Page 262: ...27 I O TIOCB5 I O TMO1 output P26 I O TIOCA5 I O TMO0 output P25 I O TIOCB4 I O TMCI1 input P24 I O TIOCA4 I O TMRI1 input P23 I O TIOCD3 I O TMCI0 input P22 I O TIOCC3 I O TMRI0 input P21 I O TIOCB3...

Page 263: ...7 6 5 4 3 2 1 0 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P2DR is an 8 bit readable writable register that stores output data f...

Page 264: ...P27 TIOCB5 TMO1 The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5 bits IOB3 to IOB0 in TIOR5 bits CCLR1 and CCLR0 in TC...

Page 265: ...All 0 Any 1 TPU Channel 5 Setting Table Below 1 Table Below 2 P26DDR 0 1 Pin function TIOCA5 output P26 input P26 output TMO0 output TIOCA5 input 1 TPU Channel 5 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000...

Page 266: ...R4 and bits IOB3 to IOB0 in TIOR4 bits CCLR1 and CCLR0 in TCR4 and bit P25DDR TPU Channel 4 Setting Table Below 1 Table Below 2 P25DDR 0 1 Pin function TIOCB4 output P25 input P25 output TIOCB4 input...

Page 267: ...LR1 and CCLR0 in TCR4 and bit P24DDR TPU Channel 4 Setting Table Below 1 Table Below 2 P24DDR 0 1 Pin function TIOCA4 output P24 input P24 output TIOCA4 input 1 TMRI1 input TPU Channel 4 Setting 2 1 2...

Page 268: ...in TMDR3 bits IOD3 to IOD0 in TIOR3L bits CCLR2 to CCLR0 in TCR3 and bit P23DDR TPU Channel 3 Setting Table Below 1 Table Below 2 P23DDR 0 1 Pin function TIOCD3 output P23 input P23 output TIOCD3 inpu...

Page 269: ...22DDR TPU Channel 3 Setting Table Below 1 Table Below 2 P22DDR 0 1 Pin function TIOCC3 output P22 input P22 output TIOCC3 input 1 TMRI0 input TPU Channel 3 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001...

Page 270: ...TCR3 and bit P21DDR TPU Channel 3 Setting Table Below 1 Table Below 2 P21DDR 0 1 Pin function TIOCB3 output P21 input P21 output TIOCB3 input TPU Channel 3 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 001...

Page 271: ...el 3 Setting Table Below 1 Table Below 2 P20DDR 0 1 Pin function TIOCA3 output P20 input P20 output TIOCA3 input 1 TPU Channel 3 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001 B 0010 B 0011 IOA3 to IOA0...

Page 272: ...32 P31 P30 I O I O I O I O I O I O SCK1 SCK0 RxD1 RxD0 TxD1 TxD0 I O I O input input output output Port 3 pins Port 3 IRQ5 input IRQ4 input Figure 8 3 Port 3 Pin Functions 8 4 2 Register Configuration...

Page 273: ...s P3DDR is initialized to H 00 bits 5 to 0 by a reset and in hardware standby mode It retains its prior state after in software standby mode As the SCI is initialized the pin states are determined by...

Page 274: ...and in hardware standby mode PORT3 contents are determined by the pin states as P3DDR and P3DR are initialized PORT3 retains its prior state after in software standby mode Port 3 Open Drain Control R...

Page 275: ...utput pin 1 SCK1 input pin IRQ5 interrupt input pin 2 Notes 1 When P35ODR 1 the pin becomes an NMOS open drain output 2 When this pin is used as an external interrupt input it should not be used as an...

Page 276: ...E 0 1 P32DDR 0 1 Pin function P32 input pin P32 output pin RxD0 input pin Note When P32ODR 1 the pin becomes an NMOS open drain output P31 TxD1 The pin function is switched as shown below according to...

Page 277: ...P42 input AN2 input P41 input AN1 input P40 input AN0 input Port 4 pins Port 4 Figure 8 4 Port 4 Pin Functions 8 5 2 Register Configuration Table 8 8 shows the port 4 register configuration Port 4 is...

Page 278: ...ting mode Port A has a built in MOS input pull up function that can be controlled by software Figure 8 5 shows the port A pin configuration PA3 A19 PA2 A18 PA1 A17 PA0 A16 Note Modes 6 and 7 are not a...

Page 279: ...d Undefined Undefined 0 0 0 0 R W W W W W PADDR is an 8 bit write only register the individual bits of which specify input or output for the pins of port A PADDR cannot be read if it is an undefined v...

Page 280: ...It retains its prior state after in software standby mode Port A Register PORTA Bit 7 6 5 4 3 2 1 0 PA3 PA2 PA1 PA0 Initial value Undefined Undefined Undefined Undefined R W R R R R Note Determined by...

Page 281: ...o 0 by a reset and in hardware standby mode It retains its prior state after in software standby mode Note Modes 6 and 7 are not available in the ROMless versions Port A Open Drain Control Register PA...

Page 282: ...etting PADDR bits to 1 makes the corresponding port A pins address outputs while clearing the bits to 0 makes the pins input ports Port A pin functions in mode 6 are shown in figure 8 7 A19 A18 A17 A1...

Page 283: ...s When PADDR bits are cleared to 0 setting the corresponding PAPCR bits to 1 turns on the MOS input pull up for that pins The MOS input pull up function is in the off state after a reset and in hardwa...

Page 284: ...B4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 PB7 input A15 output PB6 input A14 output PB5 input A13 output PB4 input A12 output PB3 input A11 output PB2 input A10 output PB1 input A9 output PB0 input A8 outp...

Page 285: ...pecify input or output for the pins of port B PBDDR cannot be read if it is an undefined value will be read PBDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior st...

Page 286: ...3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value R W R R R R R R R R Note Determined by state of pins PB7 to PB0 PORTB is an 8 bit read only register that shows the pin states It cannot be writte...

Page 287: ...eared to 0 input port setting in mode 6 or 7 setting the corresponding PBPCR bits to 1 turns on the MOS input pull up for the corresponding pins PBPCR is initialized to H 00 by a reset and in hardware...

Page 288: ...t PB7 input PB6 input PB5 input PB4 input PB3 input PB2 input PB1 input PB0 input When PBDDR 1 When PBDDR 0 Port B Figure 8 11 Port B Pin Functions Mode 6 Mode 7 In mode 7 port B pins function as I O...

Page 289: ...the corresponding PBPCR bits to 1 turns on the MOS input pull up for that pins The MOS input pull up function is in the off state after a reset and in hardware standby mode The prior state is retaine...

Page 290: ...5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 Port C PC7 input A7 output PC6 input A6 output PC5 input A5 output PC4 input A4 output PC3 input A3 output PC2 input A2 output PC1 input A1 output PC0 input A0...

Page 291: ...ify input or output for the pins of port C PCDDR cannot be read if it is an undefined value will be read PCDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state...

Page 292: ...3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Initial value R W R R R R R R R R Note Determined by state of pins PC7 to PC0 PORTC is an 8 bit read only register that shows the pin states It cannot be writte...

Page 293: ...cleared to 0 input port setting in mode 6 or 7 setting the corresponding PCPCR bits to 1 turns on the MOS input pull up for the corresponding pins PCPCR is initialized to H 00 by a reset and in hardw...

Page 294: ...Port C PC7 input PC6 input PC5 input PC4 input PC3 input PC2 input PC1 input PC0 input When PCDDR 1 When PCDDR 0 Figure 8 15 Port C Pin Functions Mode 6 Mode 7 In mode 7 port C pins function as I O p...

Page 295: ...the corresponding PCPCR bits to 1 turns on the MOS input pull up for that pins The MOS input pull up function is in the off state after a reset and in hardware standby mode The prior state is retaine...

Page 296: ...t can be controlled by software Figure 8 17 shows the port D pin configuration PD7 D15 PD6 D14 PD5 D13 PD4 D12 PD3 D11 PD2 D10 PD1 D9 PD0 D8 Port D D15 I O D14 I O D13 I O D12 I O D11 I O D10 I O D9 I...

Page 297: ...D3DDR PD2DDR PD1DDR PD0DDR Initial value 0 0 0 0 0 0 0 0 R W W W W W W W W W PDDDR is an 8 bit write only register the individual bits of which specify input or output for the pins of port D PDDDR can...

Page 298: ...3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Initial value R W R R R R R R R R Note Determined by state of pins PD7 to PD0 PORTD is an 8 bit read only register that shows the pin states It cannot be writte...

Page 299: ...PDDDR bits are cleared to 0 input port setting in mode 7 setting the corresponding PDPCR bits to 1 turns on the MOS input pull up for the corresponding pins PDPCR is initialized to H 00 by a reset an...

Page 300: ...unctions Mode 7 Note Modes 6 and 7 are not available in the ROMless versions 8 9 4 MOS Input Pull Up Function Port D has a built in MOS input pull up function that can be controlled by software This M...

Page 301: ...6 MOS Input Pull Up States Port D Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations 4 to 6 OFF OFF OFF OFF 7 ON OFF ON OFF Legend OFF MOS input pull up is always off ON OFF O...

Page 302: ...t can be controlled by software Figure 8 20 shows the port E pin configuration PE7 D7 PE6 D6 PE5 D5 PE4 D4 PE3 D3 PE2 D2 PE1 D1 PE0 D0 PE7 I O D7 I O PE6 I O D6 I O PE5 I O D5 I O PE4 I O D4 I O PE3 I...

Page 303: ...fy input or output for the pins of port E PEDDR cannot be read if it is an undefined value will be read PEDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state...

Page 304: ...3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Initial value R W R R R R R R R R Note Determined by state of pins PE7 to PE0 PORTE is an 8 bit read only register that shows the pin states It cannot be writte...

Page 305: ...H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode 8 10 3 Pin Functions Modes 4 to 6 In modes 4 to 6 when 8 bit access is designated and 8 bit bus mode i...

Page 306: ...the ROMless versions 8 10 4 MOS Input Pull Up Function Port E has a built in MOS input pull up function that can be controlled by software This MOS input pull up function can be used in modes 4 5 and...

Page 307: ...t Pull Up States Port E Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations 7 OFF OFF ON OFF ON OFF 4 to 6 8 bit bus 16 bit bus OFF OFF Legend OFF MOS input pull up is always o...

Page 308: ...F6 AS PF5 RD PF4 HWR PF3 LWR IRQ3 PF2 WAIT IRQ2 BREQO PF1 BACK IRQ1 CS5 PF0 BREQ IRQ0 CS4 Port F Note Modes 6 and 7 are not available in the ROMless versions PF7 input output PF6 I O AS output RD outp...

Page 309: ...F Data Direction Register PFDDR Bit 7 6 5 4 3 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 Initial value 1 0 0 0 0 0 0 0 R W W W W W W W W W Mode 7 Initial value 0 0 0 0...

Page 310: ...output data for the port F pins PF7 to PF0 must always be performed on PFDR If a port F read is performed while PFDDR bits are set to 1 the PFDR values are read If a port F read is performed while PFD...

Page 311: ...itial value 1 PF0 is the PF0 BREQ IRQ0 CS4 pin CS4 output is enabled when BRLE 0 CS25E 1 and PF0DDR 1 Bit 3 Address 23 Enable A23E Enables or disables address output 23 A23 For details see section 8 2...

Page 312: ...nitial value Bit 3 AS Output Disable ASOD Enables or disables AS output This bit is valid in modes 4 to 6 Bit 3 ASOD Description 0 PF6 is used as AS output pin Initial value 1 PF6 is designated as I O...

Page 313: ...al bus release Bit 7 BRLE Description 0 External bus release disabled BREQ BACK and BREQO pins can be used as I O ports Initial value 1 External bus release enabled Bit 6 BREQO Pin Enable BREQOE Outpu...

Page 314: ...PF7 input pin output pin PF6 AS The pin function is switched as shown below according to the operating mode and bit PF6DDR and bit ASOD in PFCR2 Operating Mode Modes 4 to 6 1 Mode 7 1 ASOD 0 1 PF6DDR...

Page 315: ...pin PF3 input pin PF3 output pin PF3 input pin PF3 output pin IRQ3 interrupt input pin 2 PF2 WAIT IRQ2 BREQO The pin function is switched as shown below according to the operating mode and WAITE bit...

Page 316: ...pin IRQ1 interrupt input pin 2 PF0 BREQ IRQ0 CS4 The pin function is switched as shown below according to the operating mode and the BRLE bit in BCRL and PF0CS4S bit in PFCR1 and CS25E bit in PFCR2 an...

Page 317: ...nputs Figure 8 24 shows the port G pin configuration PG4 CS0 PG3 CS1 CS7 PG2 CS2 PG1 CS3 IRQ7 CS6 PG0 ADTRG IRQ6 PG4 PG3 PG2 PG1 PG0 Note Modes 6 and 7 are not available in the ROMless versions I O I...

Page 318: ...G0DDR Modes 4 and 5 Initial value Undefined Undefined Undefined 1 0 0 0 0 R W W W W W W Modes 6 and 7 Initial value Undefined Undefined Undefined 0 0 0 0 0 R W W W W W W PGDDR is an 8 bit write only r...

Page 319: ...1 0 PG4 PG3 PG2 PG1 PG0 Initial value Undefined Undefined Undefined R W R R R R R Note Determined by state of pins PG4 to PG0 PORTG is an 8 bit read only register that shows the pin states It cannot...

Page 320: ...7 pin CS7 output is enabled when CS167E 1 and PG3DDR 1 Bit 6 CS36 Select CSS36 Selects whether CS3 or CS6 is output from the PG1 pin Change the CSS36 bit setting only when the corresponding DDR bit is...

Page 321: ...ld be written to these bits Bit 5 CS167 Enable CS167E Enables or disables CS1 CS6 and CS7 output Change the CS167E setting only when the DDR bits are cleared to 0 Bit 5 CS167E Description 0 CS1 CS6 an...

Page 322: ...4 to 6 1 Mode 7 1 PG4DDR 0 1 0 1 Pin function PG4 input pin CS0 output pin PG4 input pin PG4 output pin PG3 CS1 CS7 The pin function is switched as shown below according to the operating mode and CSS...

Page 323: ...pin PG1 output pin CS6 output pin CS3 output pin CS6 output pin PG1 input pin PG1 output pin IRQ7 interrupt input pin 2 PG0 ADTRG IRQ6 The pin function is switched as shown below according to the com...

Page 324: ...Rev 5 00 12 03 page 294 of 1088...

Page 325: ...ritten to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input output possible by counter synchronous operation PWM mode Any PWM output duty can...

Page 326: ...by data transfer controller DTC activation A D converter conversion start trigger can be generated Channel 0 to 5 compare match A input capture A signals can be used as A D converter conversion start...

Page 327: ...2A TGR2B TGR3A TGR3B TGR4A TGR4B TGR5A TGR5B General registers buffer registers TGR0C TGR0D TGR3C TGR3D I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIO...

Page 328: ...input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Co...

Page 329: ...TIOCB4 TIOCA5 TIOCB5 Clock input 1 4 16 64 256 1024 4096 TCLKA TCLKB TCLKC TCLKD Input output pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3 Channel 4...

Page 330: ...capture input output compare output PWM output pin Input capture out compare match B0 TIOCB0 I O TGR0B input capture input output compare output PWM output pin Input capture out compare match C0 TIOCC...

Page 331: ...output PWM output pin Input capture out compare match D3 TIOCD3 I O TGR3D input capture input output compare output PWM output pin 4 Input capture out compare match A4 TIOCA4 I O TGR4A input capture...

Page 332: ...TGR0C R W H FFFF H FFDC Timer general register 0D TGR0D R W H FFFF H FFDE 1 Timer control register 1 TCR1 R W H 00 H FFE0 Timer mode register 1 TMDR1 R W H C0 H FFE1 Timer I O control register 1 TIOR1...

Page 333: ...FE91 Timer I O control register 4 TIOR4 R W H 00 H FE92 Timer interrupt enable register 4 TIER4 R W H 40 H FE94 Timer status register 4 TSR4 R W 2 H C0 H FE95 Timer counter 4 TCNT4 R W H 0000 H FE96...

Page 334: ...1 TCR1 Channel 2 TCR2 Channel 4 TCR4 Channel 5 TCR5 Bit 7 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W The TCR registers are 8...

Page 335: ...2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 1 Channel Bit 7 Reserved 3 Bit 6 CCLR1 Bit 5 CCLR0 Description 1 2 4 5 0 0 0 TCNT cleari...

Page 336: ...t falling edge 1 Count at both edges Note Internal clock edge selection is valid when the input clock is 4 or slower This setting is ignored if the input clock is 1 or when overflow underflow of anoth...

Page 337: ...ts on 4 1 0 Internal clock counts on 16 1 Internal clock counts on 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKB pin input 1 0 Internal clock counts on 256 1 Count...

Page 338: ...nal clock counts on 16 1 Internal clock counts on 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKC pin input 1 0 Internal clock counts on 1024 1 Counts on TCNT5 overf...

Page 339: ...each channel The TMDR registers are initialized to H C0 by a reset and in hardware standby mode TMDR register settings should be made only when TCNT operation is stopped Bits 7 and 6 Reserved These bi...

Page 340: ...perates normally Initial value 1 TGRA and TGRC used together for buffer operation Bits 3 to 0 Modes 3 to 0 MD3 to MD0 These bits are used to set the timer operating mode Bit 3 MD3 1 Bit 2 MD2 2 Bit 1...

Page 341: ...Note When TGRC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register The TIOR registers are 8 bit registers that control the TGR registers T...

Page 342: ...t at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 In...

Page 343: ...output at compare match 0 Input capture at rising edge 0 1 Input capture at falling edge 1 0 1 Capture input source is TIOCD0 pin Input capture at both edges 1 TGR0D is input capture register 2 Captur...

Page 344: ...both edges 1 TGR1B is input capture register Capture input source is TGR0C compare match input capture Input capture at generation of TGR0C compare match input capture Don t care Channel Bit 7 IOB3 B...

Page 345: ...ompare match 1 0 Initial output is 1 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 Capture input source is TI...

Page 346: ...output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 Capture input source is TIOCD3 pin Input capture at both edges 1 TGR3D is input capture register 2 Captur...

Page 347: ...both edges 1 TGR4B is input capture register Capture input source is TGR3C compare match input capture Input capture at generation of TGR3C compare match input capture Don t care Channel Bit 7 IOB3 B...

Page 348: ...re register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 Initial output is 1 outp...

Page 349: ...ompare match 1 0 Initial output is 1 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 Capture input source is TI...

Page 350: ...edges 1 TGR1A is input capture register Capture input source is TGR0A compare match input capture Input capture at generation of channel 0 TGR0A compare match input capture Don t care Channel Bit 3 I...

Page 351: ...re match Toggle output at compare match 1 0 0 Output disabled 1 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 Input captur...

Page 352: ...ompare match 1 0 Initial output is 1 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 Capture input source is TI...

Page 353: ...both edges 1 TGR4A is input capture register Capture input source is TGR3A compare match input capture Input capture at generation of TGR3A compare match input capture Don t care Channel Bit 3 IOA3 B...

Page 354: ...ER registers are 8 bit registers that control enabling or disabling of interrupt requests for each channel The TPU has six TIER registers one for each channel The TIER registers are initialized to H 4...

Page 355: ...isabled Initial value 1 Interrupt requests TCIV by TCFV enabled Bit 3 TGR Interrupt Enable D TGIED Enables or disables interrupt requests TGID by the TGFD bit when the TGFD bit in TSR is set to 1 in c...

Page 356: ...FA bit when the TGFA bit in TSR is set to 1 Bit 0 TGIEA Description 0 Interrupt requests TGIA by TGFA disabled Initial value 1 Interrupt requests TGIA by TGFA enabled 9 2 5 Timer Status Registers TSR...

Page 357: ...is bit cannot be modified and is always read as 1 Bit 5 Underflow Flag TCFU Status flag that indicates that TCNT underflow has occurred when channels 1 2 4 and 5 are set to phase counting mode In chan...

Page 358: ...When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2 Input Capture Output Compare Flag C TGFC Status flag that indicates the occurr...

Page 359: ...When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Bit 0 Input Capture Output Compare Flag A TGFA Status flag that indicates the occurr...

Page 360: ...tialized to H 0000 by a reset and in hardware standby mode The TCNT counters cannot be accessed in 8 bit units they must always be accessed as a 16 bit unit 9 2 7 Timer General Registers TGR Bit 15 14...

Page 361: ...nitial value 1 TCNTn performs count operation n 5 to 0 Note If 0 is written to the CST bit during operation with the TIOC pin designated for output the counter stops but the TIOC pin output compare ou...

Page 362: ...the SYNC bit the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR 9 2 10 Module Stop Control Register MSTPCR MSTPCRH MSTPCRL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initi...

Page 363: ...bit units 16 bit access must always be used An example of 16 bit register access operation is shown in figure 9 2 Bus interface H Internal data bus L Bus master Module data bus TCNTH TCNTL Figure 9 2...

Page 364: ...s master Figure 9 3 8 Bit Register Access Operation Bus Master TCR Upper 8 Bits Bus interface H Internal data bus L Module data bus TMDR Bus master Figure 9 4 8 Bit Register Access Operation Bus Maste...

Page 365: ...put compare register When a compare match occurs the value in the buffer register for the relevant channel is transferred to TGR When TGR is an input capture register When input capture occurs the val...

Page 366: ...er Set period Start count Periodic counter 1 2 4 3 5 Free running counter Start count Free running counter 5 1 2 3 4 5 Select output compare register Select the counter clock with bits TPSC2 to TPSC0...

Page 367: ...CNT value H FFFF H 0000 CST bit TCFV Time Figure 9 7 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs period...

Page 368: ...tput by compare match Figure 9 9 shows an example of the setting procedure for waveform output by compare match Select waveform output mode Output selection Set output timing Start count Waveform outp...

Page 369: ...e H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 9 10 Example of 0 Output 1 Output Operation Figure 9 11 shows an example of toggle output In...

Page 370: ...annels 0 and 3 1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if 1 is selected Example of input capture operation setting procedur...

Page 371: ...cted as the TIOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT val...

Page 372: ...s presetting 1 2 Synchronous clearing Select counter clearing source Counter clearing 3 Start count 5 Set synchronous counter clearing Synchronous clearing 4 Start count 5 Clearing source generation c...

Page 373: ...he channel 1 and 2 counter clearing sources Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clearing by TGR0B compare match...

Page 374: ...tions used in buffer operation Table 9 5 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGR0A TGR0C TGR0B TGR0D 3 TGR3A TGR3C TGR3B TGR3D When TGR is an out...

Page 375: ...e signal Figure 9 17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 9 18 shows an example of the buffer operation setting procedure Select TGR function Buffer oper...

Page 376: ...tch B 1 output at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneousl...

Page 377: ...GRA input capture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set when the TCNT value is stored in...

Page 378: ...hannel 1 or 4 the counter clock setting is invalid and the counter operates independently in phase counting mode Table 9 6 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and...

Page 379: ...data are transferred to TGR1A and the lower 16 bits to TGR2A TCNT2 clock TCNT2 H FFFF H 0000 H 0001 TIOCA1 TIOCA2 TGR1A H 03A2 TGR2A H 0000 TCNT1 clock TCNT1 H 03A1 H 03A2 Figure 9 22 Example of Casca...

Page 380: ...fied by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D The initial output value is the value set in TGRA or TGRC If the set values of paired TGRs are identical the out...

Page 381: ...A0 TGR0B TIOCB0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 1 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 2 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 3 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3 TGR3C TIOCC3 TIOCC3 TGR3D TIOCD3 4 TGR4A TIOCA...

Page 382: ...ource 3 Use TIOR to designate the TGR as an output compare register and select the initial value and output value 4 Set the period in the TGR selected in 2 and set the duty in the other TGR 5 Select t...

Page 383: ...pare match is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGR0A to TGR0D TGR1A to output a 5 phase PWM waveform In t...

Page 384: ...RA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when period register and duty register compare matches occur simultaneously TCNT value TGRA H 000...

Page 385: ...t when underflow occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag provides an indication of whether TCNT is counting up or...

Page 386: ...e 9 9 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 29 Example o...

Page 387: ...KB channels 1 and 5 TCLKD channels 2 and 4 Figure 9 30 Example of Phase Counting Mode 2 Operation Table 9 10 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channels 1 and 5 TCLKC Channels 2 a...

Page 388: ...1 and 5 TCLKD channels 2 and 4 Down count Figure 9 31 Example of Phase Counting Mode 3 Operation Table 9 11 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channels 1 and 5 TCLKC Channels 2 a...

Page 389: ...ls 1 and 5 TCLKD channels 2 and 4 Up count Down count TCNT value Figure 9 32 Example of Phase Counting Mode 4 Operation Table 9 12 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channels 1 an...

Page 390: ...match TGR0A and TGR0C are used for the compare match function and are set with the speed control period and position control period TGR0B is used for input capture with TGR0B and TGR0D operating in bu...

Page 391: ...1A speed period capture TGR0A speed control period TGR1B position period capture TGR0C position control period TGR0B pulse width capture TGR0D buffer operation Channel 0 TCLKA TCLKB Edge detection cir...

Page 392: ...ignals to be enabled or disabled individually When an interrupt request is generated the corresponding status flag in TSR is set to 1 If the corresponding enable disable bit in TIER is set to 1 at thi...

Page 393: ...mpare match Possible TCI2V TCNT2 overflow Not possible TCI2U TCNT2 underflow Not possible 3 TGI3A TGR3A input capture compare match Possible TGI3B TGR3B input capture compare match Possible TGI3C TGR3...

Page 394: ...ow on a channel The interrupt request is cleared by clearing the TCFU flag to 0 The TPU has four underflow interrupts one each for channels 1 2 4 and 5 9 5 2 DTC Activation The DTC can be activated by...

Page 395: ...operation and figure 9 35 shows TCNT count timing in external clock operation TCNT TCNT input clock Internal clock N 1 N N 1 N 2 Falling edge Rising edge Figure 9 34 Count Timing in Internal Clock Op...

Page 396: ...t the output compare output pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 9 36 shows output compare output timing TGR...

Page 397: ...pare match occurrence is specified and figure 9 39 shows the timing when counter clearing by input capture occurrence is specified TCNT Counter clear signal Compare match signal TGR N N H 0000 Figure...

Page 398: ...and 9 41 show the timing in buffer operation TGRA TGRB Compare match signal TCNT TGRC TGRD n N N n n 1 Figure 9 40 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal TGRC TGRD...

Page 399: ...g in Case of Compare Match Figure 9 42 shows the timing for setting of the TGF flag in TSR by compare match occurrence and TGI interrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare...

Page 400: ...Case of Input Capture Figure 9 43 shows the timing for setting of the TGF flag in TSR by input capture occurrence and TGI interrupt request signal timing TGR TCNT Input capture signal N N TGF flag TG...

Page 401: ...ing Figure 9 45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock H FFFF H 0000 TCFV...

Page 402: ...status flag clearing by the CPU and figure 9 47 shows the timing for status flag clearing by the DTC Status flag Write signal Address TSR address Interrupt request signal TSR write cycle T1 T2 Figure...

Page 403: ...e at least 2 5 states Figure 9 48 shows the input clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TCLKA TCLKC TCLKB TCLKD Pulse width Pulse width Pulse widt...

Page 404: ...generated in the T2 state of a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 9 49 shows the timing in this case Counter clear signal Write signal Address...

Page 405: ...s in the T2 state of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 9 50 shows the timing in this case TCNT input clock Write signal Address TCNT address TCNT TC...

Page 406: ...takes precedence and the compare match signal is inhibited A compare match does not occur even if the same value as before is written Figure 9 51 shows the timing in this case Compare match signal Wr...

Page 407: ...cycle the data transferred to TGR by the buffer operation will be the data prior to the write Figure 9 52 shows the timing in this case Compare match signal Write signal Address Buffer register addres...

Page 408: ...erated in the T1 state of a TGR read cycle the data that is read will be the data after input capture transfer Figure 9 53 shows the timing in this case Input capture signal Read signal Address TGR ad...

Page 409: ...ated in the T2 state of a TGR write cycle the input capture operation takes precedence and the write to TGR is not performed Figure 9 54 shows the timing in this case Input capture signal Write signal...

Page 410: ...ffer write cycle the buffer operation takes precedence and the write to the buffer register is not performed Figure 9 55 shows the timing in this case Input capture signal Write signal Address TCNT Bu...

Page 411: ...ltaneously the TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 9 56 shows the operation timing when a TGR compare match is specified as the clearing source and H FFFF is set...

Page 412: ...V flag Figure 9 57 Contention between TCNT Write and Overflow Multiplexing of I O Pins In the chip the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB input pin with the TIOCD0 I O pi...

Page 413: ...pare match A or B or by an external reset signal Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two indepe...

Page 414: ...match A0 Clear 1 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals TMO0 TMRI0 Internal bus TCORA0 Comparator A0 Comparator B0 TCORB0 TCSR0 TCR0 TCORA1 Comparator A1 TCNT1 Comparator B1 TCORB1 TCSR1...

Page 415: ...t Timer Registers Channel Name Abbreviation R W Initial value Address 1 0 Timer control register 0 TCR0 R W H 00 H FFB0 Timer control status register 0 TCSR0 R W 2 H 00 H FFB2 Time constant register A...

Page 416: ...e used for clearing is selected by clock clear bits CCLR1 and CCLR0 in TCR When a timer counter overflows from H FF to H 00 OVF in TCSR is set to 1 TCNT0 and TCNT1 are each initialized to H 00 by a re...

Page 417: ...corresponding CMFB flag in TCSR is set Note however that comparison is disabled during the T2 state of a TCOR write cycle The timer output can be freely controlled by these compare match signals and...

Page 418: ...s whether OVF interrupt requests OVI are enabled or disabled when the OVF flag in TCSR is set to 1 Bit 5 OVIE Description 0 OVF interrupt requests OVI are disabled Initial value 1 OVF interrupt reques...

Page 419: ...at falling edge 1 External clock counted at both rising and falling edges Note If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal no...

Page 420: ...g A CMFA Status flag indicating whether the values of TCNT and TCORA match Bit 6 CMFA Description 0 Clearing conditions Initial value Cleared by reading CMFA when CMFA 1 then writing 0 to CMFA When DT...

Page 421: ...he output level and both of them can be controlled independently Note however that priorities are set such that toggle output 1 output 0 output If compare matches occur simultaneously the output chang...

Page 422: ...TP12 bit in MSTPCR is set to 1 the 8 bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For d...

Page 423: ...TCNT N 1 N N 1 Figure 10 2 Count Timing for Internal Clock Input External Clock Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR at the rising edge the falling edge an...

Page 424: ...in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match The compare match signal is generated at the last state in which the match is true just before the timer co...

Page 425: ...ggle Figure 10 5 shows the timing when the output is set to toggle at compare match A Compare match A signal Timer output pin Figure 10 5 Timing of Timer Output Timing of Compare Match Clear The timer...

Page 426: ...must be at least 1 5 states Figure 10 7 shows the timing of this operation Clear signal External reset input pin TCNT N H 00 N 1 Figure 10 7 Timing of Clearance by External Reset 10 3 4 Timing of Ove...

Page 427: ...TCNT0 and TCNT1 together is cleared when a 16 bit compare match event occurs The 16 bit counter TCNT0 and TCNT1 together is cleared even if counter clear by the TMRI0 pin has also been set The settin...

Page 428: ...ty 0 CMIA0 Interrupt by CMFA Possible High CMIB0 Interrupt by CMFB Possible OVI0 Interrupt by OVF Not possible 1 CMIA1 Interrupt by CMFA Possible CMIB1 Interrupt by CMFB Possible OVI1 Interrupt by OVF...

Page 429: ...o 1 so that the timer counter is cleared when its value matches the constant in TCORA 2 In TCSR bits OS3 to OS0 are set to B 0110 causing the output to change to 1 at a TCORA compare match and to 0 at...

Page 430: ...lear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the clear takes priority so that the counter is cleared and the write is not performed Figure 10 10 shows thi...

Page 431: ...nerated during the T2 state of a TCNT write cycle the write takes priority and the counter is not incremented Figure 10 11 shows this operation Address TCNT address Internal write signal TCNT input cl...

Page 432: ...OR write has priority and the compare match signal is inhibited even if a compare match event occurs Figure 10 12 shows this operation Address TCOR address Internal write signal TCNT TCOR N M T1 T2 TC...

Page 433: ...peration TCNT may increment erroneously when the internal clock is switched over Table 10 5 shows the relationship between the timing at which the internal clock is switched by writing to the CKS1 and...

Page 434: ...eration 1 Switching from low to low 1 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N 1 2 Switching from low to high 2 Clock before switchover Clock after switchover T...

Page 435: ...to stop and from stop to low 2 Includes switching from stop to high 3 Includes switching from high to stop 4 Generated on the assumption that the switchover is a falling edge TCNT is incremented 10 6...

Page 436: ...Rev 5 00 12 03 page 406 of 1088...

Page 437: ...terval timer operation an interval timer interrupt is generated each time the counter overflows Note The WDTOVF function is not available in the F ZTAT versions 11 1 1 Features WDT features are listed...

Page 438: ...T TSCR 2 64 128 512 2048 8192 32768 131072 Clock Clock select Internal clock sources Bus interface Module bus Legend TCSR TCNT RSTCSR Notes Timer control status register Timer counter Reset control st...

Page 439: ...ee registers as summarized in table 11 2 These registers control clock selection WDT mode switching and the reset signal Table 11 2 WDT Registers Address 1 Name Abbreviation R W Initial Value Write 2...

Page 440: ...e TME bit is cleared to 0 It is not initialized in software standby mode Notes 1 TCNT is write protected by a password to prevent accidental overwriting For details see section 11 2 4 Notes on Registe...

Page 441: ...as an interval timer the WDT generates an interval timer interrupt request WOVI when TCNT overflows If used as a watchdog timer the WDT generates the WDTOVF signal 1 when TCNT overflows Bit 6 WT IT I...

Page 442: ...TCNT starts counting up from H 00 until overflow occurs 11 2 3 Reset Control Status Register RSTCSR Bit 7 6 5 4 3 2 1 0 WOVF RSTE Initial value 0 0 0 1 1 1 1 1 R W R W R W R W Note Only 0 can be writ...

Page 443: ...t but TCNT and TCSR within the WDT are reset Bit 5 Reserved This bit should be written with 0 Bits 4 to 0 Reserved These bits cannot be modified and are always read as 1 11 2 4 Notes on Register Acces...

Page 444: ...e WOVF bit the write data must have H A5 in the upper byte and H 00 in the lower byte This clears the WOVF bit to 0 but has no effect on the RSTE bit To write to the RSTE bit the upper byte must conta...

Page 445: ...OVF signal is output This is shown in figure 11 4 This WDTOVF signal can be used to reset the system The WDTOVF signal is output for 132 states when RSTE 1 and for 130 states when RSTE 0 If TCNT overf...

Page 446: ...nal reset signal 1 WT IT TME Notes 1 The internal reset signal is generated only if the RSTE bit is set to 1 2 130 states when the RSTE bit is cleared to 0 3 The WDTOVF output function is not availabl...

Page 447: ...enerate interrupt requests at regular intervals TCNT count H 00 Time H FF WT IT 0 TME 1 WOVI Overflow Overflow Overflow Overflow Legend WOVI Interval timer interrupt request generation WOVI WOVI WOVI...

Page 448: ...OVF output function is not available in the F ZTAT versions H FF H 00 Overflow signal internal signal WOVF WDTOVF signal Internal reset signal 132 states 518 states Figure 11 7 Timing of WOVF Setting...

Page 449: ...e WDT is operating errors may occur in the incrementation Software must stop the watchdog timer by clearing the TME bit to 0 before changing the value of bits CKS2 to CKS0 11 5 3 Switching between Wat...

Page 450: ...TOVF Note The WDTOVF output function is not available in F ZTAT versions Figure 11 9 Circuit for System Reset by WDTOVF WDTOVF WDTOVF WDTOVF Signal Example 11 5 5 Internal Reset in Watchdog Timer Mode...

Page 451: ...asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiprocessor communication function is provided th...

Page 452: ...s mode 7 bit data Built in baud rate generator allows any bit rate to be selected Choice of serial clock source internal clock from baud rate generator or external clock from SCK pin Four interrupt so...

Page 453: ...generator Internal data bus RxD TxD SCK Parity generation Parity check Clock External clock 4 16 64 TXI TEI RXI ERI SMR Legend SCMR Smart card mode register RSR Receive shift register RDR Receive dat...

Page 454: ...mbol I O Function 0 Serial clock pin 0 SCK0 I O SCI0 clock input output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output 1 Serial clock p...

Page 455: ...W H 00 H FF7A Transmit data register 0 TDR0 R W H FF H FF7B Serial status register 0 SSR0 R W 1 H 84 H FF7C Receive data register 0 RDR0 R H 00 H FF7D Smart card mode register 0 SCMR0 R W H F2 H FF7E...

Page 456: ...itten to by the CPU 12 2 2 Receive Data Register RDR Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R RDR is a register that stores received serial data When the SCI has received...

Page 457: ...rformed if the TDRE bit in SSR is set to 1 TSR cannot be directly read or written to by the CPU 12 2 4 Transmit Data Register TDR Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W...

Page 458: ...standby mode and module stop mode it retains its previous state Bit 7 Communication Mode C A A A A Selects asynchronous mode or synchronous mode as the SCI operating mode Bit 7 C A A A A Description 0...

Page 459: ...in parity addition and checking The O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking in asynchronous mode The O E bit setting is invalid in synchrono...

Page 460: ...ansmit character before it is sent In reception only the first stop bit is checked regardless of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit if it is 0 it is treated a...

Page 461: ...ms enabling or disabling of SCI transfer operations serial clock output in asynchronous mode and interrupt requests and selection of the serial clock source SCR can be read or written to by the CPU at...

Page 462: ...disables the start of serial transmission by the SCI Bit 5 TE Description 0 Transmission disabled 1 Initial value 1 Transmission enabled 2 Notes 1 The TDRE flag in SSR is fixed at 1 2 In this state se...

Page 463: ...1 is received Note When receive data including MPB 0 is received receive data transfer from RSR to RDR receive error detection and setting of the RDRF FER and ORER flags in SSR is not performed When r...

Page 464: ...r details of clock source selection see table 12 9 in section 12 3 Operation Bit 1 CKE1 Bit 0 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin functions as I O port 1 Synchronous mode Int...

Page 465: ...serial data can be written to TDR Bit 7 TDRE Description 0 Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the DTC is activated by a TXI interrupt and writes data to TDR 1 Set...

Page 466: ...ansmission cannot be continued either Bit 4 Framing Error FER Indicates that a framing error occurred during reception in asynchronous mode causing abnormal termination Bit 4 FER Description 0 Clearin...

Page 467: ...ntinued either Bit 2 Transmit End TEND Indicates that there is no valid data in TDR when the last bit of the transmit character is sent and transmission has been ended The TEND flag is read only and c...

Page 468: ...ister BRR Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W BRR is an 8 bit register that sets the serial transfer bit rate in accordance with the baud rate generat...

Page 469: ...00 0 19 2 34 9600 0 6 0 6 2 48 0 7 0 00 0 9 2 34 19200 0 2 0 2 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 0 1 0 2 0 00 38400 0 1 0 1 0 1 0 00 3 6864 MHz 4 MHz 4 9152 MHz 5 MHz Bit Rate bits s n N Error n N...

Page 470: ...9 2 34 0 9 0 00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 9 8304 MHz 10 MHz 12 MHz 12 288 MHz Bit Rate bits s n N Error n N Error n N Error n N Error 110 2...

Page 471: ...23 0 00 0 25 0 16 0 27 0 00 31250 0 13 0 00 0 14 1 70 0 15 0 00 0 16 1 20 38400 0 10 0 11 0 00 0 12 0 16 0 13 0 00 18 MHz 19 6608 MHz 20 MHz 25 MHz Bit Rate bits s n N Error n N Error n N Error n N E...

Page 472: ...124 2 155 5 k 0 99 0 199 1 99 1 124 1 199 1 249 2 77 10 k 0 49 0 99 0 199 0 249 1 99 1 124 1 155 25 k 0 19 0 39 0 79 0 99 0 159 0 199 0 249 50 k 0 9 0 19 0 39 0 49 0 79 0 99 0 124 100 k 0 4 0 9 0 19 0...

Page 473: ...B Bit rate bits s N BRR setting for baud rate generator 0 N 255 Operating frequency MHz n Baud rate generator input clock n 0 to 3 See the table below for the relation between n and the clock SMR Set...

Page 474: ...ncy Asynchronous Mode MHz Maximum Bit Rate bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 19200...

Page 475: ...76 0 6144 38400 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 5 1 2500 78125 6 1 5000 93750 6 144 1 5360 96000 7 3728 1 8432 115200 8 2 0000 125000 9 8304 2 4576 153600 10 2 50...

Page 476: ...SINV SMIF Initial value 1 1 1 1 0 0 1 0 R W R W R W R W SCMR selects LSB first or MSB first transfer by means of bit SDIR Except in the case of asynchronous mode 7 bit data LSB first or MSB first tran...

Page 477: ...s not affect the logic level of the parity bit s parity bit inversion requires inversion of the O E bit in SMR Bit 2 SINV Description 0 TDR contents are transmitted without modification Initial value...

Page 478: ...e and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For details see section 19 5 Module Stop Mode MSTPCR is initialized to H 3FFF by a reset and i...

Page 479: ...rameters determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI clock source When in...

Page 480: ...0 8 bit data Yes No 1 bit 1 2 bits 1 0 7 bit data 1 bit 1 Asynchronous mode multi processor format 2 bits 1 Synchronous mode 8 bit data No None Table 12 9 SMR and SCR Settings and SCI Clock Source Se...

Page 481: ...line and when it goes to the space state low level recognizes a start bit and starts serial communication One serial communication character consists of a start bit low level followed by data in LSB f...

Page 482: ...S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1...

Page 483: ...of each transmit data bit as shown in figure 12 3 0 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Figure 12 3 Relation between Output Clock and Transfer Data Phase Asynchronous Mode Data Transfer Operations...

Page 484: ...sed 1 Set the clock selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When the clock is selected in asynchronous mode it is output immediately after SCR settings are...

Page 485: ...t to 1 a frame of 1s is output and transmission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TD...

Page 486: ...or multiprocessor bit One parity bit even or odd parity or one multiprocessor bit is output A format in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit s...

Page 487: ...ta Start bit Parity bit Stop bit Start bit Data Parity bit Stop bit TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt reque...

Page 488: ...o identify the error After performing the appropriate error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the...

Page 489: ...andling Parity error handling No Yes Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error handling No Yes Overrun error handling ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to 0 Figur...

Page 490: ...stop bits only the first is checked c Status check The SCI checks whether the RDRF flag is 0 indicating that the receive data can be transferred from RSR to RDR If all the above checks are passed the...

Page 491: ...received data differs from the parity even or odd set in SMR Receive data is transferred from RSR to RDR Figure 12 8 shows an example of the operation for reception in asynchronous mode RDRF FER 0 1...

Page 492: ...smitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0...

Page 493: ...le Data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 12 9 Example of Inter Processor Communication Using Multiprocessor Format Transmiss...

Page 494: ...te Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR Set the MPBT bit in SSR to 0 or 1 Finally clear the TDRE flag to 0 Serial transmission continuation procedure To co...

Page 495: ...8 bit or 7 bit data is output in LSB first order c Multiprocessor bit One multiprocessor bit MPBT value is output d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuo...

Page 496: ...rupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt request generated Idle state mark state TXI interrupt request generated Figure 12...

Page 497: ...d check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag...

Page 498: ...Error handling Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error handling Overrun error handling ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 12 12 Sample Multiproces...

Page 499: ...interrupt request is not generated and RDR retains its state ID1 a Data does not match station s ID MPIE RDR value 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1 1 Data ID2 Start bit MPB Stop bit Start bit Data Data...

Page 500: ...re One unit of transfer data character or frame Bit 0 Serial data Serial clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note High except in continuous transfer Figure 12 14 Data Format in Syn...

Page 501: ...ection see table 12 9 When the SCI is operated on an internal clock the serial clock is output from the SCK pin Eight serial clock pulses are output in the transfer of one character and when no transf...

Page 502: ...alization Set data transfer format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE or RE bit in SCR to 1 and set RIE TIE TEIE and MPIE bits as necessary Note In sim...

Page 503: ...ialization The TxD pin is automatically designated as the transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data...

Page 504: ...al clock has been specified data is output synchronized with the input clock The serial transmit data is sent from the TxD pin starting with the LSB bit 0 and ending with the MSB bit 7 3 The SCI check...

Page 505: ...pt request generated Figure 12 17 Example of SCI Transmit Operation Serial data reception synchronous mode Figure 12 18 shows a sample flowchart for serial reception The following procedure should be...

Page 506: ...Transfer cannot be resumed if the ORER flag is set to 1 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF f...

Page 507: ...it in SCR is set to 1 when the RDRF flag changes to 1 a receive data full interrupt RXI request is generated Also if the RIE bit in SCR is set to 1 when the ORER flag changes to 1 a receive error inte...

Page 508: ...r handling If a receive error occurs read the ORER flag in SSR and after performing the appropriate error handling clear the ORER flag to 0 Transmission reception cannot be resumed if the ORER flag is...

Page 509: ...R is set to 1 an RXI interrupt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request is generated An RXI interrupt can activate the DTC to perform data transfe...

Page 510: ...data is written to TDR when the TDRE flag is cleared to 0 the data stored in TDR will be lost since it has not yet been transferred to TSR It is therefore essential to check that the TDRE flag is set...

Page 511: ...g to the TxD pin should first be set to 1 To send a break during serial transmission first clear DR to 0 then clear the TE bit to 0 When the TE bit is cleared to 0 the transmitter is initialized regar...

Page 512: ...mode is given by formula 1 below M 0 5 1 2N L 0 5 F D 0 5 N 1 F 100 Formula 1 Where M Receive margin N Ratio of bit rate to clock N 16 D Clock duty D 0 to 1 0 L Frame length L 9 to 12 F Absolute valu...

Page 513: ...in module stop mode or software standby mode depend on the port settings and becomes high level output after the relevant mode is cleared If a transition is made during transmission the data being tr...

Page 514: ...wchart for mode transition during reception Read TEND flag in SSR TE 0 Transition to software standby mode etc Exit from software standby mode etc Change operating mode No All data transmitted TEND 1...

Page 515: ...andby Exit from software standby Figure 12 24 Asynchronous Transmission Using Internal Clock Port input output Last TxD bit held High output Port input output Marking output Port input output SCI TxD...

Page 516: ...RDR Read RDRF flag in SSR Exit from software standby mode etc Change operating mode No RDRF 1 Yes Yes Reception No 1 2 RE 1 Initialization Start of reception 1 Receive data being received becomes inva...

Page 517: ...by the chip is as follows Asynchronous mode Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data re...

Page 518: ...Baud rate generator Internal data bus RxD TxD SCK Parity generation Parity check Clock 4 16 64 TXI RXI ERI SMR Legend SCMR Smart card mode register RSR Receive shift register RDR Receive data registe...

Page 519: ...Pin Name Symbol I O Function 0 Serial clock pin 0 SCK0 I O SCI0 clock input output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output 1 Se...

Page 520: ...trol register 0 SCR0 R W H 00 H FF7A Transmit data register 0 TDR0 R W H FF H FF7B Serial status register 0 SSR0 R W 1 H 84 H FF7C Receive data register 0 RDR0 R H 00 H FF7D Smart card mode register 0...

Page 521: ...Data Transfer Direction SDIR Selects the serial parallel conversion format Bit 3 SDIR Description 0 TDR contents are transmitted LSB first Initial value Receive data is stored in RDR LSB first 1 TDR...

Page 522: ...t 2 TEND are also different Bits 7 to 5 Operate in the same way as for the normal SCI For details see section 12 2 7 Serial Status Register SSR Bit 4 Error Signal Status ERS In smart card interface mo...

Page 523: ...on 1 5 etu after transmission of a 1 byte serial character when GM 0 and BLK 1 When TDRE 1 and ERS 0 normal transmission 1 0 etu after transmission of a 1 byte serial character when GM 1 and BLK 0 Whe...

Page 524: ...r Mode BLK Selects block transfer mode Bit 6 BLK Description 0 Normal smart card interface mode operation Initial value Error signal transmission detection and automatic data retransmission performed...

Page 525: ...ction 12 2 6 Serial Control Register SCR Bits 1 and 0 Clock Enable 1 and 0 CKE1 CKE0 These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin In smart car...

Page 526: ...etu or longer This does not apply to block transfer mode Only asynchronous communication is supported there is no synchronous communication function 13 3 2 Pin Connections Figure 13 2 shows a schemati...

Page 527: ...equipment IC card Data line Clock line Reset line Figure 13 2 Schematic Diagram of Smart Card Interface Pin Connections Note If an IC card is not connected and the TE and RE bits are both set to 1 cl...

Page 528: ...t back to the transmitting end and retransmission of the data is requested If an error signal is sampled during transmission the same data is retransmitted Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When there is...

Page 529: ...n The signal line is pulled high again by a pull up resistor 5 If the transmitting station does not receive an error signal it proceeds to transmit the next data frame If it does receive an error sign...

Page 530: ...O E bit is cleared to 0 if the IC card is of the direct convention type and set to 1 if of the inverse convention type Bits CKS1 and CKS0 select the clock source of the built in baud rate generator an...

Page 531: ...t convention type the logic 1 level corresponds to state Z and the logic 0 level to state A and transfer is performed in LSB first order The start character data above is H 3B The parity bit is 1 sinc...

Page 532: ...etermined by the bit rate and the setting of bits BCP1 and BCP0 B S 22n 1 N 1 106 Where N Value set in BRR 0 N 255 B Bit rate bits s Operating frequency MHz n See table 13 4 S Number of internal clock...

Page 533: ...0 00 10 7136 13 00 14 2848 16 00 18 00 20 00 25 00 Bits s N Error N Error N Error N Error N Error N Error N Error N Error N Error 9600 0 0 00 1 30 1 25 1 8 99 1 0 00 1 12 01 2 15 99 2 6 60 3 12 49 Tab...

Page 534: ...1 and CKS0 bits in SMR and set the PE bit to 1 4 Set the SMIF SDIR and SINV bits in SCMR When the SMIF bit is set to 1 the TxD and RxD pins are both switched from ports to SCI pins and are placed in t...

Page 535: ...ly go back to step 2 6 To end transmission clear the TE bit to 0 With the above processing interrupt handling or data transfer by the DTC is possible If transmission ends and the TEND flag is set to 1...

Page 536: ...Yes Clear TE bit to 0 Start of transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error handling Error handling TEND 1 All data transmitted TEND 1 ERS...

Page 537: ...eted In case of normal transmission TEND flag is set In case of transmit error ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set I O signal line output Data 1 Data 1 Figure 1...

Page 538: ...cleared to 0 If either is set perform the appropriate receive error handling then clear both the ORER and the PER flag to 0 3 Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set t...

Page 539: ...ee section 12 3 2 Operation in Asynchronous Mode Mode Switching Operation When switching from receive mode to transmit mode first confirm that the receive operation has been completed then start from...

Page 540: ...a transmit operation the TDRE flag is also set to 1 at the same time as the TEND flag in SSR and a TXI interrupt is generated If the TXI request is designated beforehand as a DTC activation source the...

Page 541: ...the value for the fixed output state in software standby mode 2 Write 0 to the TE bit and RE bit in the serial control register SCR to halt the transmit receive operation At the same time set the CKE...

Page 542: ...g points For details see section 12 3 2 Operation in Asynchronous Mode Data Format The data format is 8 bits with parity There is no stop bit but there is a guard time of 2 or more bits 1 or more bits...

Page 543: ...bits BCP1 and BCP0 In reception the SCI samples the falling edge of the start bit using the base clock and performs internal synchronization Receive data is latched internally at the rising edge of th...

Page 544: ...ived parity bit is checked the PER bit in SSR is automatically set to 1 If the RIE bit in SCR is enabled at this time an ERI interrupt request is generated The PER bit in SSR should be kept cleared to...

Page 545: ...et for a frame for which an error signal indicating an abnormality is received 8 If an error signal is not sent back from the receiving end the ERS bit in SSR is not set 9 If an error signal is not se...

Page 546: ...Rev 5 00 12 03 page 516 of 1088...

Page 547: ...at 20 MHz operation Choice of single mode or scan mode Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels Four data registers Conversion results are held...

Page 548: ...Bus interface A D C S R A D C R A D D R D A D D R C A D D R B A D D R A AVCC Vref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG Conversion start trigger from 8 bit timer or TPU Successive approximations...

Page 549: ...Symbol I O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and A D conversion reference voltage Reference voltage pin Vref Input...

Page 550: ...data register BH ADDRBH R H 00 H FF92 A D data register BL ADDRBL R H 00 H FF93 A D data register CH ADDRCH R H 00 H FF94 A D data register CL ADDRCL R H 00 H FF95 A D data register DH ADDRDH R H 00...

Page 551: ...ansferred to the upper byte bits 15 to 8 of ADDR and the lower 2 bits are transferred to the lower byte bits 7 and 6 and stored Bits 5 to 0 are always read as 0 The correspondence between the analog i...

Page 552: ...le stop mode Bit 7 A D End Flag ADF Status flag that indicates the end of A D conversion Bit 7 ADF Description 0 Clearing conditions Initial value When 0 is written to the ADF flag after reading ADF 1...

Page 553: ...e Bit 4 Scan Mode SCAN Selects single mode or scan mode as the A D conversion operating mode See section 14 4 Operation for details of single mode and scan mode operation Only set the SCAN bit while c...

Page 554: ...r disables external triggering of A D conversion operations ADCR is initialized to H 3F by a reset and in standby mode or module stop mode Bits 7 and 6 Timer Trigger Select 1 and 0 TRGS1 TRGS0 These b...

Page 555: ...R W R W R W R W R W R W R W R W R W R W R W MSTPCR is a 16 bit readable writable register that performs module stop mode control When the MSTP9 bit in MSTPCR is set to 1 A D converter operation stops...

Page 556: ...d the lower byte value is transferred to TEMP Next when the lower byte is read the TEMP contents are transferred to the CPU When reading ADDR always read the upper byte before the lower byte It is pos...

Page 557: ...n ADCSR to halt A D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the operating mode or input channel is...

Page 558: ...nnel 2 AN2 State of channel 3 AN3 Note Vertical arrows indicate instructions executed by software Set Set Clear Clear A D conversion result 1 A D conversion A D conversion result 2 Read conversion res...

Page 559: ...n The ADST bit can be set at the same time as the operating mode or input channel is changed Typical operations when three channels AN0 to AN2 are selected in scan mode are described next Figure 14 4...

Page 560: ...d by software 2 Data currently being converted is ignored Clear 1 Idle Idle A D conversion time Idle Continuous A D conversion A D conversion 1 Idle Idle Idle Idle Idle Transfer 2 A D conversion 3 A D...

Page 561: ...udes tD and the input sampling time The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 14 4 In...

Page 562: ...mber of states Table 14 5 A D Conversion Time Scan Mode CKS1 CKS Conversion Time States 0 0 512 Fixed 1 64 Fixed 1 0 256 Fixed 1 128 Fixed 14 4 4 External Trigger Input Timing A D conversion can be ex...

Page 563: ...s can be enabled or disabled by means of the ADIE bit in ADCSR The DTC can be activated by an ADI interrupt Having the converted data read by the DTC in response to an ADI interrupt enables continuous...

Page 564: ...ould be avoided as far as possible Failure to do so may result in incorrect operation of the analog circuitry due to inductance adversely affecting A D conversion values Also digital circuitry must be...

Page 565: ...Precision Definitions The chip s A D conversion precision definitions are given below Resolution The number of A D converter digital output codes Offset error The deviation of the analog input voltag...

Page 566: ...tage Does not include the offset error full scale error or quantization error Absolute precision The deviation between the digital value and the analog input value Includes the offset error full scale...

Page 567: ...sor output impedance exceeds 5 k charging may be insufficient and it may not be possible to guarantee the A D conversion precision If a large capacitance is provided externally the input load will ess...

Page 568: ...ot communicate with digital signals on the mounting board so acting as antennas A D converter equivalent circuit Chip 20 pF Cin 15 pF 10 k Low pass filter C to 0 1 F Sensor output impedance Max 5 k Se...

Page 569: ...15 1 1 Features D A converter features are listed below 8 bit resolution Two output channels Maximum conversion time of 10 s with 20 pF load Output voltage of 0 V to Vref D A output hold function in...

Page 570: ...a block diagram of the D A converter Module data bus Internal data bus Vref AVCC DA1 DA0 AVSS 8 bit D A converter Control circuit DADR0 Bus interface DADR1 DACR Legend DACR D A control register DADR0...

Page 571: ...el 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference voltage pin Vref Input Analog reference voltage 15 1 4 Register Configuration Table 15 2 summarizes the registers of...

Page 572: ...gisters 01 DACR01 Bit 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE Initial value 0 0 0 1 1 1 1 1 R W R W R W R W DACR01 is 8 bit readable writable register that controls the operation of the D A converter DACR01 i...

Page 573: ...ns disabled 1 0 Channel 0 D A conversion enabled Channel 1 D A conversion disabled 1 Channel 0 and 1 D A conversions enabled 1 0 0 Channel 0 D A conversion disabled Channel 1 D A conversion enabled 1...

Page 574: ...set to 1 D A converter operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For details see section 19 5...

Page 575: ...nel 0 Figure 15 2 shows the timing of this operation 1 Write the conversion data to DADR0 2 Set the DAOE0 bit in DACR01 to 1 D A conversion is started and the DA0 pin becomes an output pin The convers...

Page 576: ...result 1 High impedance state tDCONV DADR0 write cycle DA0 DAOE0 DADR0 Address DACR01 write cycle Conversion data 2 Conversion result 2 tDCONV Legend tDCONV D A conversion time DADR0 write cycle DACR0...

Page 577: ...of the RAM enable bit RAME in the system control register SYSCR Note The amount of on chip RAM is 16 kbytes in the H8S 2319C 8 kbytes in the H8S 2319 H8S 2318 H8S 2317 H8S 2316 H8S 2315 and H8S 2312S...

Page 578: ...ystem Control Register SYSCR Bit 7 6 5 4 3 2 1 0 INTM1 INTM0 NMIEG LWROD RAME Initial value 0 0 0 0 0 0 0 1 R W R W R W R W R W R W R W R W The on chip RAM is enabled or disabled by the RAME bit in SY...

Page 579: ...or word units Each type of access can be performed in one state Even addresses use the upper 8 bits and odd addresses use the lower 8 bits Word data must start at an even address Note The amount of on...

Page 580: ...Rev 5 00 12 03 page 550 of 1088...

Page 581: ...ching is thus speeded up and processing speed increased The on chip ROM is enabled and disabled by means of the mode pins MD2 to MD0 and the EAE bit in BCRL The flash memory version of the chip can be...

Page 582: ...3 2 1 0 MDS2 MDS1 MDS0 Initial value 1 0 0 0 0 R W R R R Note Determined by pins MD2 to MD0 MDCR is an 8 bit read only register used to monitor the current operating mode of the chip Bit 7 Reserved T...

Page 583: ...to H 01FFFF are in on chip ROM and addresses H 020000 to H 03FFFF are a reserved area 1 Reserved area 1 1 Addresses H 010000 to H 03FFFF 2 are external addresses in external expanded mode or a reserve...

Page 584: ...d single chip mode 1 0 Enabled 256 kbytes 1 5 1 Enabled 64 kbytes 8 1 0 0 0 9 1 10 1 0 0 Enabled 256 kbytes 2 5 Boot mode advanced expanded mode with on chip ROM enabled 3 1 Enabled 64 kbytes 11 Boot...

Page 585: ...ash memory can be erased and programmed operation is the same as in advanced expanded mode with on chip ROM enabled 4 Apart from the fact that flash memory can be erased and programmed operation is th...

Page 586: ...2319 and H8S 2319C have 512 kbytes of on chip ROM The H8S 2318 has 256 kbytes of on chip ROM The H8S 2317 has 128 kbytes of on chip ROM The H8S 2316 and H8S 2313 have 64 kbytes of on chip ROM The H8S...

Page 587: ...kbyte and 64 kbyte blocks Programming erase times The flash memory programming time is 10 0 ms typ for simultaneous 128 byte programming equivalent to 78 s typ per byte and the erase time is 50 ms ty...

Page 588: ...verview Block Diagram Module bus Bus interface controller Flash memory 128 384 256 kbytes Operating mode EBR1 Internal address bus Internal data bus 16 bits FWE pin Mode pins EBR2 SYSCR2 FLMCR2 FLMCR1...

Page 589: ...d or erased Flash memory can be programmed and erased in boot mode user program mode and programmer mode Boot mode On board programming mode User program mode User mode on chip ROM enabled Reset state...

Page 590: ...the host 2 Programming control program transfer When boot mode is entered the boot program in the chip originally incorporated in the chip is started and the programming control program in the host is...

Page 591: ...should be prepared in the host or in the flash memory 2 Programming erase control program transfer When the FWE pin is driven high user software confirms this fact executes the transfer program in the...

Page 592: ...mode or user program mode When the emulation block set in RAMER is accessed while the emulation function is being executed data written in the overlap RAM is read Application program Execution state...

Page 593: ...ap RAM to be rewritten Application program Flash memory RAM SCI Overlap RAM programming data Programming data Programming control program Execution state Figure 17 7 Writing Overlap RAM Data in User P...

Page 594: ...kbyte block and eight 4 kbyte blocks On chip 384 kbyte flash memory is divided into five 64 kbyte blocks one 32 kbyte block and eight 4 kbyte blocks Address H 3FFFF Address H 5FFFF 4 kbytes 8 32 kbyt...

Page 595: ...h program erase protection by hardware Mode 2 MD2 Input Sets MCU operating mode Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port F2 PF2 Input Sets MCU operating m...

Page 596: ...register RAMER R W H 00 H FEDB Notes 1 Lower 16 bits of the address 2 Flash memory Registers selection is performed by the FLSHE bit in system control register 2 SYSCR2 3 In modes in which the on chip...

Page 597: ...and H 00 when a low level is input When on chip flash memory is disabled a read will return H 00 and writes are invalid Writes to the SWE bit in FLMCR1 are enabled only when FWE 1 writes to bits ESU...

Page 598: ...ondition When FWE 1 and SWE 1 Bit 4 Program Setup Bit PSU Prepares for a transition to program mode Do not set the SWE ESU EV PV E or P bit at the same time Bit 4 PSU Description 0 Program setup clear...

Page 599: ...SWE 1 Bit 1 Erase E Selects erase mode transition or clearing Do not set the SWE ESU PSU EV PV or P bit at the same time Bit 1 E Description 0 Erase mode cleared Initial value 1 Transition to erase m...

Page 600: ...LER Indicates that an error has occurred during an operation on flash memory programming or erasing When FLER is set to 1 flash memory goes to the error protection state Bit 7 FLER Description 0 Flash...

Page 601: ...5 4 3 2 1 0 EBR2 EB13 1 EB12 1 EB11 2 EB10 2 EB9 EB8 Initial value 0 0 0 0 0 0 0 0 R W R W 1 R W 1 R W R W R W R W Notes 1 Available only in the H8S 2315 F ZTAT and H8S 2314 F ZTAT 2 Reserved in the...

Page 602: ...to H 03FFFF EB12 64 kbytes 1 H 040000 to H 04FFFF EB13 64 kbytes 1 H 050000 to H 05FFFF Notes 1 These blocks are valid only in the H8S 2315 F ZTAT and H8S 2314 F ZTAT 2 Not available in the H8S 2317...

Page 603: ...AMER Bit 7 6 5 4 3 2 1 0 RAMS RAM2 RAM1 RAM0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real time flash...

Page 604: ...Memory Area Selection RAM2 to RAM0 These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM see table 17 8 Table 17 8 Flash Memory Area Divisions RAM Area Blo...

Page 605: ...7 6 1 Boot Mode When boot mode is used the flash memory programming control program must be prepared in the host beforehand The channel 1 SCI to be used is set to asynchronous mode When a reset start...

Page 606: ...Rev 5 00 12 03 page 576 of 1088 RxD1 TxD1 SCI1 Chip Flash memory Write data reception Verify data transmission Host On chip RAM Figure 17 9 System Configuration in Boot Mode...

Page 607: ...00 and transmits one H 55 data byte After receiving H 55 chip transmits one H AA data byte to host Host transmits number of programming control program bytes N upper byte followed by lower byte Chip t...

Page 608: ...Depending on the host s transmission bit rate and the chip s system clock frequency there will be a discrepancy between the bit rates of the host and the chip To ensure correct SCI operation the host...

Page 609: ...on state for the programming control program transferred to RAM Note that the boot program remains stored in this area after a branch is made to the programming control program Figure 17 12 RAM Areas...

Page 610: ...pin The reset should end with RxD1 high After the reset ends it takes approximately 100 states before the chip is ready to measure the low level period of the RxD1 pin In boot mode if any data has be...

Page 611: ...pins from becoming output signal pins during a reset or to prevent collision with signals outside the microcomputer Notes 1 Mode pins and FWE pin input must satisfy the mode programming setup time tMD...

Page 612: ...t Write the FWE assessment program and transfer program and the program erase control program if necessary beforehand Notes Do not apply a constant high level to the FWE pin Apply a high level to the...

Page 613: ...e Follow the procedure shown in the program program verify flowchart in figure 17 15 to write data or programs to flash memory Performing program operations according to this flowchart will enable dat...

Page 614: ...y setting the PV bit in FLMCR1 Before reading in program verify mode a dummy write of H FF data should be made to the addresses to be read The dummy write should be executed after the elapse of s or m...

Page 615: ...umber of Writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 Write Time z s z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 z2 z2 z2 Notes 1 Data transfer is performed by byte transfer The lower 8 bits of the...

Page 616: ...7 4 Erase Verify Mode In erase verify mode data is read after memory has been erased to check whether it has been correctly erased After the elapse of the erase time erase mode is exited the E bit in...

Page 617: ...n FLMCR1 Clear SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n N NG NG NG NG OK OK OK OK n...

Page 618: ...protected state is entered Yes Yes Reset standby protection In a reset including a WDT overflow reset and in standby mode FLMCR1 FLMCR2 EBR1 and EBR2 are initialized and the program erase protected s...

Page 619: ...ce with the program erase algorithm and the program erase operation is aborted Aborting the program erase operation prevents damage to the flash memory due to overprogramming or overerasing If the MCU...

Page 620: ...PR ER FLER 1 RD VF PR ER FLER 1 Error protection mode Error protection mode software standby Software standby mode FLMCR1 FLMCR2 except FLER bit EBR1 EBR2 initialization state FLMCR1 FLMCR2 EBR1 EBR2...

Page 621: ...e made from the flash memory area or the RAM area overlapping flash memory Emulation can be performed in user mode and user program mode Figure 17 18 shows an example of emulation of real time flash m...

Page 622: ...EB8 and EB9 in the H8S 2317 F ZTAT Figure 17 19 Example of RAM Overlap Operation Example in Which Flash Memory Block Area EB1 is Overlapped 1 Set bits RAMS RAM2 RAM1 and RAM0 in RAMER to 1 0 0 1 to o...

Page 623: ...n handling sequence during programming or erasing the vector would not be read correctly 2 possibly resulting in MCU runaway 3 If an interrupt occurred during boot program execution it would not be po...

Page 624: ...e detailed internal signals are output after execution of an auto program or auto erase operation Note In the H8S 2315 F ZTAT and H8S 2314 F ZTAT a PROM programmer that supports the Renesas Technology...

Page 625: ...chip ROM memory map and figures 17 21 and 17 23 show the socket adapter pin assignments H 00000000 MCU mode address Programmer mode address H 0003FFFF H 0005FFFF 1 H 0001FFFF 2 H 00000 H 3FFFF H 5FFFF...

Page 626: ...7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 CE OE WE FWE VCC VSS NC 64 68 69 62 66 67 RES XTAL EXTAL NC OPEN 40 63 64 65 74 77 7...

Page 627: ...Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the I O6 signal In status read mode error information is output if an error occurs Table...

Page 628: ...11 4 Memory Read Mode After the end of an auto program auto erase or status read operation the command wait state is entered To read memory contents a transition must be made to memory read mode by m...

Page 629: ...emory Read Mode Timing Waveforms after Command Write Table 17 17 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max...

Page 630: ...Memory Read Mode Table 17 18 AC Characteristics in Memory Read Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Access time tacc 20 s CE output delay time tce 150 ns OE ou...

Page 631: ...g will be started but a programming error will occur Memory address transfer is executed in the second cycle figure 17 26 Do not perform transfer later than the second cycle Do not perform a command w...

Page 632: ...1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms WE rise time tr 30 ns WE fall time tf 30 ns Write setup time tpn...

Page 633: ...ommand write As long as the next command write has not been performed reading is possible by enabling CE and OE AC Characteristics Table 17 20 AC Characteristics in Auto Erase Mode Conditions VCC 3 3...

Page 634: ...mode when an abnormal end occurs in auto program mode or auto erase mode The return code is retained until a command write for other than status read mode is performed Table 17 21 AC Characteristics...

Page 635: ...ffective address error Initial value 0 0 0 0 0 0 0 0 Indications Normal end 0 Abnormal end 1 Command error 1 Otherwise 0 Program ming error 1 Otherwise 0 Erase error 1 Otherwise 0 Count exceeded 1 Oth...

Page 636: ...e tosc1 tbmv tdwn Note Except in auto program mode and auto erase mode drive the FWE input pin low Figure 17 29 Oscillation Stabilization Time Programmer Mode Setup Time and Power Supply Fall Sequence...

Page 637: ...VCC has stabilized Also drive the FWE pin low before turning off VCC When applying or disconnecting VCC power fix the FWE pin low and place the flash memory in the hardware protection state The power...

Page 638: ...verify or erase verify mode Access flash memory only for verify operations verification during programming erasing Also do not clear the SWE bit during programming erasing or verifying Similarly when...

Page 639: ...erify operations prohibited VCC FWE tOSC1 Min 0 s Min 0 s tMDS 3 tMDS 3 MD2 to MD0 1 RES SWE bit SWE set SWE cleared Programming erasing possible Wait time x Wait time 100 s Notes 1 Except when switch...

Page 640: ...WE bit 2 Period during which flash memory can be programmed Execution of program in flash memory prohibited and data reads other than verify operations prohibited Notes 1 Except when switching modes t...

Page 641: ...ime 100 s Programming erasing possible Wait time x Wait time 100 s User mode User program mode Notes 1 When entering boot mode or making a transition from boot mode to another mode mode switching must...

Page 642: ...yte programming equivalent to 78 s typ per byte and the erase time is 50 ms typ Reprogramming capability The flash memory can be reprogrammed up to 100 times On board programming modes There are two m...

Page 643: ...EBR1 Internal address bus Internal data bus 16 bits Mode pin EBR2 SYSCR2 FLMCR2 FLMCR1 RAMER Legend FLMCR1 Flash memory control register 1 FLMCR2 Flash memory control register 2 EBR1 Erase block regis...

Page 644: ...rogrammed or erased Flash memory can be programmed and erased in boot mode user program mode and PROM mode Boot mode On board programming mode User program mode User mode on chip ROM enabled Reset sta...

Page 645: ...the host 2 Programming control program transfer When boot mode is entered the boot program in the chip originally incorporated in the chip is started and the programming control program in the host is...

Page 646: ...erase control program should be prepared in the host or in the flash memory 2 Programming erase control program transfer Executes the transfer program in the flash memory and transfers the programming...

Page 647: ...mode or user program mode When the emulation block set in RAMER is accessed while the emulation function is being executed data written in the overlap RAM is read Application program Execution state...

Page 648: ...RAM to be rewritten Application program Flash memory RAM SCI Overlap RAM programming data Programming data Programming control program Execution state Figure 17 38 Writing Overlap RAM Data in User Pr...

Page 649: ...memory is divided into seven 64 kbyte blocks one 32 kbyte block and eight 4 kbyte blocks Address H 000000 Address H 07FFFF 4 kbytes 8 32 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kby...

Page 650: ...et Mode 2 MD2 Input Sets MCU operating mode Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port PF2 PF2 Input Sets MCU operating mode in programmer mode Port PF1 PF1...

Page 651: ...F42 RAM emulation register RAMER R W H 00 H FEDB Notes 1 Lower 16 bits of the address 2 Flash memory Registers selection is performed by the FLSHE bit in system control register 2 SYSCR2 3 In modes in...

Page 652: ...ng the E1 bit FLMCR1 is initialized to H 80 by a reset and in hardware standby mode and software standby mode When on chip flash memory is disabled a read will return H 00 and writes are invalid Write...

Page 653: ...0 Program setup cleared Initial value 1 Program setup Setting condition When SWE1 1 Bit 3 Erase Verify 1 EV1 Selects erase verify mode transition or clearing for addresses H 000000 to H 03FFFF Do not...

Page 654: ...PV2 E2 P2 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W FLMCR2 is an 8 bit register used for flash memory operating mode control Program verify mode or erase verify mode for address...

Page 655: ...n error protection is enabled Setting condition See section 17 17 3 Error Protection Bit 6 Software Write Enable Bit 2 SWE2 Enables or disables flash memory programming and erasing for addresses H 040...

Page 656: ...ion 0 Erase verify mode cleared Initial value 1 Transition to erase verify mode Setting condition When SWE2 1 Bit 2 Program Verify 2 PV2 Selects program verify mode transition or clearing for addresse...

Page 657: ...0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W EBR1 is an 8 bit register that specifies the flash memory erase area block by block EBR1 is initialized to H 00 by a reset in hardware standby mode and...

Page 658: ...y clear all EBR1 and EBR2 bits to 0 When on chip flash memory is disabled a read will return H 00 and writes are invalid The flash memory block configuration is shown in table 17 28 Table 17 28 Flash...

Page 659: ...e flash memory control registers to be read and written to Clearing FLSHE to 0 designates these registers as unselected the register contents are retained Bit 3 FLSHE Description 0 Flash control regis...

Page 660: ...not selected Initial value Program erase protection of all flash memory blocks is disabled 1 Emulation selected Program erase protection of all flash memory blocks is enabled Bits 2 to 0 Flash Memory...

Page 661: ...rase verify operation 17 15 1 Boot Mode When boot mode is used the flash memory programming control program must be prepared in the host beforehand The channel 1 SCI to be used is set to asynchronous...

Page 662: ...Rev 5 00 12 03 page 632 of 1088 RxD1 TxD1 SCI1 Chip Flash memory Write data reception Verify data transmission Host On chip RAM Figure 17 40 System Configuration in Boot Mode...

Page 663: ...00 and transmits one H 55 data byte After receiving H 55 chip transmits one H AA data byte to host Host transmits number of programming control program bytes N upper byte followed by lower byte Chip t...

Page 664: ...the above operations Depending on the host s transmission bit rate and the chip s system clock frequency there will be a discrepancy between the bit rates of the host and the chip To ensure correct SC...

Page 665: ...hat the boot program remains stored in this area after a branch is made to the programming control program Figure 17 43 RAM Areas in Boot Mode Notes on Use of Boot Mode When the chip comes out of rese...

Page 666: ...ports with multiplexed address functions and bus control output pins AS RD HWR will change according to the change in the microcomputer s operating mode 2 Therefore care must be taken to make pin sett...

Page 667: ...ram when transferred to on chip RAM Branch to flash memory application program Branch to program erase control program in RAM area Execute program erase control program flash memory rewriting Transfer...

Page 668: ...ed by a program in flash memory 2 Perform programming in the erased state Do not perform additional programming on previously programmed addresses 3 Do not program addresses H 000000 to H 03FFFF and H...

Page 669: ...ramming time the programming mode is exited the Pn bit in FLMCRn is cleared to 0 then the PSUn bit is cleared to 0 at least s later Next the watchdog timer is cleared after the elapse of s or more and...

Page 670: ...reprogram data area Number of Writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 Write Time z s z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 z2 z2 z2 Notes 1 Data transfer is performed by byte transfer Th...

Page 671: ...16 4 Erase Verify Mode n 1 for addresses H 000000 to H 03FFFF and n 2 for addresses H 040000 to H 07FFFF In erase verify mode data is read after memory has been erased to check whether it has been cor...

Page 672: ...r EV1 2 bit in FLMCR1 2 Clear SWE1 2 bit in FLMCR1 2 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE1 2 bit in FLMCR1 2 n N...

Page 673: ...in standby mode FLMCR1 FLMCR2 EBR1 and EBR2 are initialized and the program erase protected state is entered In a reset via the RES pin the reset state is not entered unless the RES pin is held low u...

Page 674: ...o 0 in FLMCR2 sets the program erase protected state for area H 040000 to H 07FFFF Execute in on chip RAM external memory or addresses H 000000 to H 03FFFF Yes Yes Block specification protection Erase...

Page 675: ...e retained but program mode or erase mode is aborted at the point at which the error occurred Program mode or erase mode cannot be re entered by re setting the P1 P2 E1 or E2 bit However PV1 PV2 EV1 a...

Page 676: ...ion mode software standby Software standby mode FLMCR1 FLMCR2 except FLER bit EBR1 EBR2 initialization state FLMCR1 FLMCR2 EBR1 EBR2 initialization state Software standby mode release RD Memory read p...

Page 677: ...R setting has been made accesses can be made from the flash memory area or the RAM area overlapping flash memory Emulation can be performed in user mode and user program mode Figure 17 48 shows an exa...

Page 678: ...0 1 to overlap part of RAM onto the area EB1 for which real time programming is required 2 Real time programming is performed using the overlapping RAM 3 After the program data has been confirmed the...

Page 679: ...y 3 If an interrupt occurred during boot program execution it would not be possible to execute the normal boot mode sequence For these reasons in on board programming mode alone there are conditions f...

Page 680: ...of an auto program or auto erase operation Table 17 34 shows programmer mode pin settings Table 17 34 Programmer Mode Pin Settings Pin Names Settings External Circuit Connection Mode pins MD2 MD1 MD0...

Page 681: ...14 A15 A16 A17 A18 A19 A20 I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 CE OE WE FWE VCC VSS NC 64 68 69 62 66 67 RES XTAL EXTAL NC OPEN 40 63 64 65 74 77 78 98 59 42 65 66 67 76 79 80 100 61 9 20 33 51 59...

Page 682: ...tatus polling is used to confirm the end of auto erasing Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the I O6 signa...

Page 683: ...20 4 Memory Read Mode After the end of an auto program auto erase or status read operation the command wait state is entered To read memory contents a transition must be made to memory read mode by m...

Page 684: ...emory Read Mode Timing Waveforms after Command Write Table 17 38 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max...

Page 685: ...Memory Read Mode Table 17 39 AC Characteristics in Memory Read Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Access time tacc 20 s CE output delay time tce 150 ns OE ou...

Page 686: ...g will be started but a programming error will occur Memory address transfer is executed in the second cycle figure 17 56 Do not perform transfer later than the second cycle Do not perform a command w...

Page 687: ...70 ns Status polling start time twsts 1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms WE rise time tr 30 ns WE f...

Page 688: ...on is retained until the next command write As long as the next command write has not been performed reading is possible by enabling CE and OE AC Characteristics Table 17 41 AC Characteristics in Auto...

Page 689: ...hen an abnormal end occurs in auto program mode or auto erase mode The return code is retained until a command write for other than status read mode is performed Table 17 42 AC Characteristics in Stat...

Page 690: ...ffective address error Initial value 0 0 0 0 0 0 0 0 Indications Normal end 0 Abnormal end 1 Command error 1 Otherwise 0 Program ming error 1 Otherwise 0 Erase error 1 Otherwise 0 Count exceeded 1 Oth...

Page 691: ...tion Stabilization Time Programmer Mode Setup Time and Power Supply Fall Sequence 17 20 10 Notes on Memory Programming When programming addresses which have previously been programmed carry out auto e...

Page 692: ...ata reliability When setting the P1 or E1 bit in FLMCR1 or the P2 or E2 bit in FLMCR2 the watchdog timer should be set beforehand as a precaution against program runaway etc Do not set or clear the SW...

Page 693: ...on a 128 byte programming unit block Programming should be carried out with the entire programming unit block erased Before programming check that the chip is correctly mounted in the PROM programmer...

Page 694: ...nd this LSI User program mode The user MAT can be programmed by using the optional interface User boot mode The user boot program of the optional interface can be made and the user MAT can be programm...

Page 695: ...e flash memory programming time is TBD ms typ for 128 byte simultaneous programming which is equivalent to TBD s per byte The erasing time is TBD ms typ per 64 kbyte block Number of programming Flash...

Page 696: ...us 16 bits Legend FCCS Flash code control and status register FPCS Flash program code select register FECS Flash erase code select register FKEY Flash key code register FMATS Flash MAT select register...

Page 697: ...rogrammed or erased Flash memory can be read programmed or erased on the board only in user program mode user boot mode and boot mode Flash memory can be read programmed or erased by means of the PROM...

Page 698: ...T User MAT User boot MAT 2 Transition to User Mode Mode setting change and reset FLSHE bit setting change Mode setting change and reset Notes 1 All erasure is performed After that the specified block...

Page 699: ...mode and PROM mode User MAT User boot MAT Address H 000000 Address H 07FFFF Address H 000000 Address H 001FFF 512 kbytes 8 kbytes Figure 17 62 Flash Memory Configuration The user MAT and user boot MAT...

Page 700: ...med in the eight blocks of 4 kbytes Figure 17 63 Block Division of User MAT 17 22 7 Programming Erasing Interface Programming erasing is executed by downloading the on chip program to the on chip RAM...

Page 701: ...is selected by setting the corresponding bits in the programming erasing interface register The download destination can be specified by FTDAR 2 Download of on chip program The on chip program is aut...

Page 702: ...am is initiated The on chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on chip RAM The execution result is returned to the p...

Page 703: ...transmit data output Receive data RxD1 Input Serial receive data input Note For the pin configuration in PROM mode see section 17 28 PROM Mode 17 22 9 Register Configuration 1 Registers The registers...

Page 704: ...ts The SCO bit is a programming only bit The value which can be read is always 0 2 The initial value at initiation in user mode or user program mode is H 00 The initial value at initiation in user boo...

Page 705: ...sh Memory 17 23 1 Programming Erasing Interface Register The programming erasing interface registers are as described below They are all 8 bit registers that can be accessed in byte Except for the FLE...

Page 706: ...1 Indicates an error occurs during programming erasing flash memory Programming erasing protection for flash memory error protection is valid Setting condition See section 17 25 3 Error Protection Bi...

Page 707: ...is written to H A5 During execution in the on chip RAM Not in RAM emulation mode RAMS in RAMER 0 2 Flash Program Code Select Register FPCS FPCS selects the on chip programming program to be downloade...

Page 708: ...of on chip program and programming erasing of flash memory Before setting the SCO bit to 1 in order to download on chip program or executing the downloaded programming erasing program these processing...

Page 709: ...selection state when the value other than H AA is written and in user boot MAT selection state when H AA is written The MAT is switched by writing the value in FMATS When the MAT is switched follow se...

Page 710: ...d Before setting the SCO bit to 1 be sure to set the FTDAR value between H 00 to H 03 as well as clearing this bit to 0 Bit 7 TDER Description Return Value after Download 0 Setting of TDA6 to TDA0 is...

Page 711: ...0L are stored The return value of the processing result is written in R0L Since the stack area is used for storing the registers except for R0L the stack area must be saved at the processing start A m...

Page 712: ...as much as 4 kbytes starting from the start address specified by FTDAR For the address map of the on chip RAM see figure 17 69 The download control is set by using the programming erasing interface re...

Page 713: ...r is occurred Multi selection or program which is not mapped is selected Bit 1 Flash Key Register Error Detect FK Returns the check result whether the value of FKEY is set to H A5 Bit 1 FK Description...

Page 714: ...mming erasing program which has downloaded these settings a Flash programming erasing frequency parameter FPEFEQ general register ER0 of CPU This parameter sets the operating frequency of the CPU The...

Page 715: ...thus 25 00 The formula that 25 00 100 2500 is converted to the binary digit and b 0000 1001 1100 0100 H 09C4 is set to ER0 b Flash pass fail parameter FPFR general register R0L of CPU This is the ret...

Page 716: ...r H 80 as the boundary of the programming start address on the user MAT 2 The program data for the user MAT must be prepared in the consecutive area The program data must be in the consecutive space w...

Page 717: ...MOA27 MOA26 MOA25 MOA24 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 MOA23 MOA22 MOA21 MOA20 MOA19 MOA18 MOA17 MOA16 Initial value R W R W R W R W R W R W R W R W R W...

Page 718: ...D26 MOD25 MOD24 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 MOD23 MOD22 MOD21 MOD20 MOD19 MOD18 MOD17 MOD16 Initial value R W R W R W R W R W R W R W R W R W Bit 15 1...

Page 719: ...e see section 17 25 3 Error Protection Bit 6 MD Description 0 FLER setting is normal FLER 0 1 FLER 1 and programming cannot be performed Bit 5 Programming Execution Error Detect EE 1 is returned to th...

Page 720: ...ing of write data address is normal 1 Setting of write data address is abnormal Bit 1 Write Address Error Detect WA When the following area is specified as the start address of the programming destina...

Page 721: ...everal block numbers cannot be specified Bit 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 Initial value R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 Initial value R W R W...

Page 722: ...nter the error protection state see section 17 25 3 Error Protection Bit 6 MD Description 0 FLER settings is normal FLER 0 1 FLER 1 and erasure cannot be performed Bit 5 Erasure Execution Error Detect...

Page 723: ...its 2 and 1 Reserved Return 0 Bit 0 Success Fail SF Indicates whether the erasing processing is ended normally or not Bit 0 SF Description 0 Erasure is ended normally no error 1 Erasure is ended abnor...

Page 724: ...0 may be written to this bit 17 23 4 RAM Emulation Register RAMER Bit 7 6 5 4 3 2 1 0 RAMS RAM2 RAM1 RAM0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W RAMER specifies the area of flash memory to...

Page 725: ...Memory Area Selection RAM2 to RAM0 These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM see table 17 51 Table 17 51 Flash Memory Area Divisions RAM Area Bl...

Page 726: ...anced single chip mode 1 Note Normally user mode should be used Before downloading a program erase program set the FLSHE bit to 1 to switch to the user program mode 17 24 1 Boot Mode Boot mode execute...

Page 727: ...byte of H 55 to this LSI When reception is not executed normally boot mode is initiated again reset and the operation described above must be executed The bit rate between the host and this LSI is no...

Page 728: ...t be set to H FFFFFFFF and transmitted Then the state for waiting program data is returned to the state of programming erasing command wait When the erasure preparation notice is received the state fo...

Page 729: ...ram data transmission Erasure command reception Program end Erase block specification Erasure end Inquiry command reception H 55 reception Inquiry command response 1 2 3 4 Figure 17 67 Overview of Boo...

Page 730: ...led in advance Download cannot be executed in emulation mode 2 When the program data is made by means of emulation use the FTDAR register to change the download destination Note that the download area...

Page 731: ...tion process entry Initialization programming program or Initialization erasing program Area that can be used by user Area that can be used by user Area that can be used by user H FFEC00 RAMEND H FFFB...

Page 732: ...rogram must be executed in an area other than the flash memory to be programmed Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on chip RAM The area t...

Page 733: ...ameter Before the SCO bit is set to 1 incorrect judgement must be prevented by setting the DPFR parameter that is one byte of the start address of the on chip RAM area specified by FTDAR to a value ot...

Page 734: ...e source that caused download to fail can be investigated by the description below If the value of the DPFR parameter is the same as before downloading e g H FF the address setting of the download des...

Page 735: ...nitialization program FPFR general register R0L is judged i All interrupts and the use of a bus master other than the CPU are prohibited The specified voltage is applied for the specified time when pr...

Page 736: ...sferred to the on chip RAM and then programming must be executed l Programming There is an entry point of the programming program in the area from download start address set by FTDAR 16 bytes of on ch...

Page 737: ...ng procedure program FPFR 0 No Initialization error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set FEBS parameter Erasing JSR FTDAR setting 16 Yes FPFR 0 No...

Page 738: ...set no block is erased even though the erasing program is executed and an error is returned to the return value parameter FPFR c Erasure Similar to as in programming there is an entry point of the er...

Page 739: ...to H 01 Specify H FFCC00 as download destination Download erasing program Initialize erasing program Initialize programming program Download programming program 1 End procedure program Enter RAM emul...

Page 740: ...mode is a user arbitrary boot mode unlike boot mode that uses the on chip SCI Only the user MAT can be programmed erased in user boot mode Programming erasing of the user boot MAT is only enabled in...

Page 741: ...amming procedure program Figure 17 73 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT...

Page 742: ...lization error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set FEBS parameter Programming JSR FTDAR setting 16 Yes FPFR 0 No Clear FKEY and erasing error proc...

Page 743: ...on chip RAM user MAT and external space is shown in section 17 29 3 Procedure Program and Storable Area for Programming Data 17 25 Protection There are two kinds of flash memory program erase protecti...

Page 744: ...e unless the RES pin is held low until oscillation has stabilized In the case of a reset during operation hold the RES pin low for the RES pulse width that is specified in the section on AC characteri...

Page 745: ...the form of the microcomputer entering runaway during programming erasing of the flash memory or operations that are not according to the established procedures for programming erasing Aborting progra...

Page 746: ...transition diagram in figure 17 75 shows transitions to and from the error protection state Reset or standby Hardware protection Program mode Erase mode Error protection mode Error protection mode So...

Page 747: ...accessible in both the user MAT area and as the RAM area that has been overlaid on the user MAT area Such emulation is possible in both user mode and user program mode Figure 17 76 shows an example of...

Page 748: ...ime programming of the data for this area set the RAMER register s RAMS bit to 1 and each of the RAM2 to RAM0 bits to 0 2 Realtime programming is carried out using the overlaid area of RAM In programm...

Page 749: ...ues clear the RAMS bit to 0 to cancel the overlap of RAM 2 Transfer the user programming erasing procedure program to RAM 3 Run the programming erasing procedure program in RAM and download the on chi...

Page 750: ...ring switching there is no guarantee of which memory MAT is being accessed Always mask the maskable interrupts before switching between MATs In addition configure the system so that NMI interrupts do...

Page 751: ...s Accordingly when the CPU clock frequency is 25 MHz the download for each program takes approximately TBD s at maximum 2 Write to flash memory related registers by DTC While an instruction in on chip...

Page 752: ...crocomputer no countermeasures are available for a runaway by WDT during programming erasing by the downloaded on chip program Prepare countermeasures e g use of the user branch routine and periodic t...

Page 753: ...nal signals are output after execution of automatic programming or automatic erasure In the PROM mode provide a 12 MHz input clock signal Table 17 56 PROM Mode Pins Pin Names Settings External Circuit...

Page 754: ...ress in MCU mode Address in MCU mode Address in PROM mode Address in PROM mode H 00000 H 7FFFF H 000000 H 001FFF H 00000 H 01FFF On chip ROM space user boot MAT 8 kbytes On chip ROM space user MAT 512...

Page 755: ...12 2 20 3 4 1 40 11 30 5 6 7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 CE OE WE FWE VCC VSS NC 40 63 64 65 74 77 78 98 59 42 65...

Page 756: ...e automatic erasing of the entire user MAT or user boot MAT Status polling is used to confirm the end of automatic erasing Status read mode Status polling is used with automatic programming and automa...

Page 757: ...waiting state So to read the contents of memory after these operations issue the command to change the mode to the memory read mode before reading from the memory 2 In memory read mode the writing of...

Page 758: ...28 5 Auto Erase Mode 1 Auto erase mode only supports erasing of the entire memory 2 Do not perform command writing during auto erasing is in progress 3 To confirm the end of automatic erasing check th...

Page 759: ...mode 2 The I O6 status polling output is a flag that indicates normal abnormal end of auto program or auto erase mode Table 17 60 Truth Table of Status Polling Output Pin Name In Progress Abnormal End...

Page 760: ...than the normal 100 s 4 The flash memory is initially in the erased state when the device is shipped by Renesas Technology For other chips for which the history of erasure is unknown auto erasing as...

Page 761: ...rate the program enters the inquiry selection state 2 Inquiry Selection State In this state the boot program responds to inquiry commands from the host The device name clock mode and bit rate are sel...

Page 762: ...erations for Selection Operations for Programming Operations for Checking Operations for Erasing Figure 17 82 Boot Program States Bit Rate Adjustment State The bit rate is calculated by measuring the...

Page 763: ...are consists of the inquiries and the ACK for successful completion 2 n byte commands or n byte responses These commands and responses are comprised of n bytes of data These are selections and respon...

Page 764: ...ng erasing and checking Response 1 byte Response to an inquiry Size 1 byte The amount of data for transmission excluding the command amount of data and checksum Checksum 1 byte The checksum is calcula...

Page 765: ...oot MAT Information Inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT H 25 User MAT Information Inquiry Inquiry regarding the a number of user MATs an...

Page 766: ...by the product names the number of devices characters and device codes A number of devices 1 byte The number of device types supported by the boot program A number of characters 1 byte The number of c...

Page 767: ...presents the number of modes and modes A number of clock modes 1 byte The number of supported clock modes H 00 indicates no clock mode or the device allows to read the clock mode Mode 1 byte Values of...

Page 768: ...he number of multiplication ratios and the multiplication ratios A number of types 1 byte The number of supported multiplied clock types e g when there are two multiplied clock types which are the mai...

Page 769: ...ng clock frequency types e g when there are two operating clock frequency types which are the main and peripheral clocks the number of types will be H 02 Minimum value of operating clock frequency 2 b...

Page 770: ...there are areas SUM 1 byte Checksum 8 User MAT Information Inquiry The boot program will return the number of user MATs and their addresses Command H 25 Command H 25 1 byte Inquiry regarding user MAT...

Page 771: ...Number of erased blocks in flash memory Block Start Address 4 bytes Start address of a block Block Last Address 4 bytes Last address of a block There are as many groups of data representing the start...

Page 772: ...hich the device can be set Normally the value is two main operating frequency and peripheral module operating frequency Multiplication ratio 1 1 byte The value of multiplication or division ratios for...

Page 773: ...data are listed below 1 Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of t...

Page 774: ...enerated Error 1 100 N 1 B 64 2 2 n 1 106 When the new bit rate is selectable the rate will be set in the register after sending ACK in response The host will send an ACK with the new bit rate for con...

Page 775: ...1 byte Transition to programming erasing state Response H 06 Response H 06 1 byte Response to transition to programming erasing state The boot program will send ACK when the user MAT and user boot MAT...

Page 776: ...should be selected with the new bit rate selection H 3F command according to the returned information on multiplication ratios and operating frequencies 7 After selection of the device and clock mode...

Page 777: ...ming selection command and an 128 byte programming command Firstly the host should send the programming selection command and select the programming method and programming MATs There are two programmi...

Page 778: ...boot program will transfer a programming program The data is programmed to the user boot MATs by the transferred programming program Command H 42 Command H 42 1 byte User boot program programming sel...

Page 779: ...de H 54 Selection processing error transfer error occurs and processing is not completed 4 128 Byte Programming The boot program will use the programming program transferred by the programming selecti...

Page 780: ...st should fill the rest with H FF Sending the 128 byte programming command with the address of H FFFFFFFF will stop the programming operation The boot program will interpret this as the end of the pro...

Page 781: ...ill wait for selection of programming or erasing The sequences of the issuing of erasure selection commands and the erasure of data are shown in figure 17 87 Transfer of Erasure Program Host Boot Prog...

Page 782: ...f the block to be erased SUM 1 byte Checksum Response H 06 Response H 06 1 byte Response to Erasure After erasure has been completed the boot program will return ACK Error Response H D8 ERROR Error Re...

Page 783: ...read size fixed at 9 Area 1 byte H 00 User boot MAT H 01 User MAT An address error occurs when the area setting is incorrect Read address 4 bytes Start address to be read from Read size 4 bytes Size...

Page 784: ...gram will return the byte by byte total of the contents of the bytes of the user program Command H 4B Command H 4B 1 byte Sum check for user program Response H 5B Size Checksum of user program SUM Res...

Page 785: ...ror response to the blank check of user MATs Error code H 52 1 byte Erasure has not been completed Boot Program State Inquiry The boot program will return indications of its present state and error co...

Page 786: ...g is completed H 5F Erasure Block Specification Wait Erasure is completed Table 17 64 Error Code Code Description H 00 No Error H 11 Sum Check Error H 12 Program Size Error H 21 Device Code Mismatch E...

Page 787: ...mmand write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf...

Page 788: ...E hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A18 0 I O7 0 OE WE Ot...

Page 789: ...tce 150 ns OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE A18 0 I O7 0 OE WE VIH VIL VIL tacc toh toh tacc Address Stable Address Stable Figure...

Page 790: ...e twsts 1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory programming time twrite 1 3000 ms WE rise time tr 30 ns WE fall time tf 30 ns Address...

Page 791: ...s Data setup time tds 50 ns Programming pulse width twep 70 ns Status polling start time tests 1 ms Status polling access time tspa 150 ns Memory erase time terase 100 40000 ms WE rise time tr 30 ns W...

Page 792: ...put delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time tce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A18 0 I O7 0 OE WE tdh tdf tds tf tr twep tnxtc tnxtc tf tr twep...

Page 793: ...RAM 4 The flash memory is accessible until the start of programming or erasing that is until the result of downloading has been judged When in a mode in which the external address space is not accessi...

Page 794: ...ore the data should be transferred to the on chip RAM to place the address that FMPDR indicates in an area other than the flash memory In consideration of these conditions there are three factors oper...

Page 795: ...1 to FCCS Download Operation for Key Register Clear Judgement of Download Result Programming Procedure Operation for Download Error Operation for Settings of Initial Parameter Execution of Initializa...

Page 796: ...Execution of Writing SC0 1 to FCCS Download Operation for Key Register Clear Erasing Procedure Judgement of Download Result Operation for Download Error Operation for Settings of Default Parameter Exe...

Page 797: ...gement of Download Result Programming procedure Operation for Download Error Operation for Settings of Default Parameter Execution of Initialization Judgement of Initialization Result Operation for In...

Page 798: ...or Key Register Clear Erasing Procedure Judgement of Download Result Operation for Download Error Operation for Settings of Default Parameter Execution of Initialization Judgement of Initialization Re...

Page 799: ...ster runs on a medium speed clock and the other supporting modules run on the high speed clock and a function that allows the medium speed mode to be disabled and the clock division ratio to be change...

Page 800: ...n that allows the medium speed mode to be disabled and the clock division ratio to be changed for the entire chip SCKCR is initialized to H 00 by a reset and in hardware standby mode It is not initial...

Page 801: ...l also change when the division ratio is changed The frequency of the clock output from the pin in this case will be as follows EXTAL n Where EXTAL Crystal resonator or external clock frequency n Divi...

Page 802: ...crystal resonator or by input of an external clock 18 3 1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as shown in the example in figure 18 2 Select the d...

Page 803: ...Notes on Board Design When a crystal resonator is connected the following points should be noted Other signal lines should be routed away from the oscillator circuit to prevent induction from interfe...

Page 804: ...re than 10 pF In example b make sure that the external clock is held high in standby mode EXTAL XTAL External clock input Open a XTAL pin left open EXTAL XTAL External clock input b Complementary cloc...

Page 805: ...width tEXL 20 10 ns Figure 18 6 External clock input high pulse width tEXH 20 10 ns External clock rise time tEXr 5 5 ns External clock fall time tEXf 5 5 ns tCL 0 4 0 6 0 4 0 6 tcyc 5 MHz Figure 20 2...

Page 806: ...ator to generate the system clock 18 5 Medium Speed Clock Divider The medium speed clock divider divides the system clock to generate 2 4 8 16 and 32 18 6 Bus Master Clock Selection Circuit The bus ma...

Page 807: ...re as follows 1 High speed mode 2 Medium speed mode 3 Sleep mode 4 Module stop mode 5 Software standby mode 6 Hardware standby mode Of these 2 to 6 are power down modes Sleep mode is a CPU mode medium...

Page 808: ...Halted Retained Halted Retained reset 2 Retained Hardware standby mode Pin Halted Halted Undefined Halted Reset High impedance Notes 1 The bus master operates on the medium speed clock and other on c...

Page 809: ...by an external interrupt and a transition is made to normal operation The SSBY bit should be cleared by writing 0 to it Bit 7 SSBY Description 0 Transition to sleep mode after execution of SLEEP instr...

Page 810: ...pedance state in software standby mode Bit 3 OPE Description 0 In software standby mode address bus and bus control signals are high impedance 1 In software standby mode address bus and bus control si...

Page 811: ...nce 1 Fixed high Fixed high Fixed high High impedance Bit 6 Reserved This bit can be read or written to but only 0 should be written Bit 5 Division Ratio Select DIV When the DIV bit is set to 1 the me...

Page 812: ...o SCK0 are set to other than high speed mode a divided clock is supplied to the entire chip Bits 4 and 3 Reserved These bits cannot be modified and are always read as 0 Bits 2 to 0 System Clock Select...

Page 813: ...W MSTPCR is a 16 bit readable writable register that performs module stop mode control MSTPCR is initialized to H 3FFF by a reset and in hardware standby mode It is not initialized in software standby...

Page 814: ...made to high speed mode and medium speed mode is cleared at the end of the current bus cycle If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 a transition is made to slee...

Page 815: ...p mode can be set for individual on chip supporting modules When the corresponding MSTP bit in MSTPCR is set to 1 module operation stops at the end of the bus cycle and a transition is made to module...

Page 816: ...but do not affect operation 19 5 2 Usage Notes DTC Module Stop Depending on the operating status of the DTC the MSTP14 bit may not be set to 1 Setting of the DTC module stop mode should be carried out...

Page 817: ...7 interrupt request signal is input clock oscillation starts and after the elapse of the time set in bits STS2 to STS0 in SYSCR stable clocks are supplied to the entire chip software standby mode is c...

Page 818: ...6 6 8 2 10 9 13 1 16 4 21 8 32 8 65 5 1 262144 states 10 4 13 1 16 4 21 8 26 2 32 8 43 6 65 6 131 2 1 0 Reserved 1 16 states 0 6 0 8 1 0 1 3 1 6 2 0 2 7 4 0 8 0 s Recommended time setting Using an Ex...

Page 819: ...cation Example 19 6 5 Usage Notes I O Port Status In software standby mode I O port states are retained If the OPE bit is set to 1 the address bus and bus control signal output is also retained Theref...

Page 820: ...e Hardware standby mode is cleared by means of the STBY pin and the RES pin When the STBY pin is driven high while the RES pin is low the reset state is set and clock oscillation is started Ensure tha...

Page 821: ...ck stops at the end of the bus cycle and output goes high clock output is enabled when the PSTOP bit is cleared to 0 When DDR for the corresponding port is cleared to 0 clock output is disabled and in...

Page 822: ...Rev 5 00 12 03 page 792 of 1088...

Page 823: ...tings Item Symbol Value Unit Power supply voltage VCC 0 3 to 4 3 V Input voltage except port 4 Vin 0 3 to VCC 0 3 V Input voltage port 4 Vin 0 3 to AVCC 0 3 V Reference power supply voltage Vref 0 3 t...

Page 824: ...7 V Input high voltage RES STBY NMI MD2 to MD0 VIH VCC 0 9 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Ports 3 A to G 2 2 VCC 0 3 V Port 4 2 2 AVCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 VCC 0 1 V...

Page 825: ...mA Analog power supply voltage Idle 0 01 5 0 A During A D and D A conversion AICC 1 4 3 0 V 3 0 mA Reference power supply voltage Idle 0 01 5 0 A RAM standby voltage VRAM 2 0 V Notes 1 If the A D and...

Page 826: ...IOL 2 0 mA Permissible output low current total Total of all output pins IOL 80 mA Permissible output high current per pin All output pins IOH 2 0 mA Permissible output high current total Total of all...

Page 827: ...Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Test Item Symbol Min Max Min Max Unit Conditions Clock cycle time tcyc 50 500 40 500 ns Figure...

Page 828: ...Rev 5 00 12 03 page 798 of 1088 tCr tCL tCf tCH tcyc Figure 20 2 System Clock Timing tOSC1 tOSC1 EXTAL VCC STBY RES tDEXT tDEXT NMI Figure 20 3 Oscillation Stabilization Timing...

Page 829: ...o AVCC VSS AVSS 0 V 2 MHz to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Test Item Symbol Min Max Min Max Unit Conditions RES setup...

Page 830: ...Rev 5 00 12 03 page 800 of 1088 tRESW tRESS tRESS RES Figure 20 4 Reset Input Timing tIRQS IRQ edge input tIRQH tNMIS tNMIH tIRQS IRQ level input NMI IRQ tNMIW tIRQW Figure 20 5 Interrupt Input Timing...

Page 831: ...Min Max Min Max Unit Test Conditions Address delay time tAD 20 20 ns Figures 20 6 to 20 10 Address setup time tAS 0 5 tcyc 15 0 5 tcyc 15 ns Address hold time tAH 0 5 tcyc 10 0 5 tcyc 8 ns CS delay t...

Page 832: ...0 tcyc 15 ns WR pulse width 2 tWSW2 1 5 tcyc 20 1 5 tcyc 15 ns Write data delay time tWDD 30 20 ns Write data setup time tWDS 0 5 tcyc 20 0 5 tcyc 15 ns Write data hold time tWDH 0 5 tcyc 10 0 5 tcyc...

Page 833: ...8 A23 to A0 CS7 to CS0 AS tRSD2 tAS tAH tCSD1 tACC2 tRSD1 tASD tASD tAD tACC3 tWRD2 tWRD2 tWSW1 tWDD tWDH T1 T2 RD read D15 to D0 read HWR LWR write D15 to D0 write tRDS tAH tAS tAS tRDH Figure 20 6 B...

Page 834: ...A23 to A0 CS7 to CS0 AS tRSD2 tAS tAH tCSD1 tACC4 tRSD1 tASD tASD tAD tACC5 tWRD2 tWRD1 tWSW2 tWDD tWDH T1 T3 RD read D15 to D0 read HWR LWR write D15 to D0 write tWDS T2 tRDS tAS tAH tRDH Figure 20 7...

Page 835: ...Rev 5 00 12 03 page 805 of 1088 A23 to A0 CS7 to CS0 AS tWTH T1 T2 RD read D15 to D0 read HWR to LWR write D15 to D0 write WAIT Tw T3 tWTS tWTH tWTS Figure 20 8 Basic Bus Timing 3 State Access 1 Wait...

Page 836: ...Rev 5 00 12 03 page 806 of 1088 A23 to A0 CS0 AS tRSD2 tAS tAH tASD tASD tAD tACC3 tRDS tRDH T1 T2 RD read D15 to D0 read T2 or T3 T1 Figure 20 9 Burst ROM Access Timing 2 State Access...

Page 837: ...Rev 5 00 12 03 page 807 of 1088 tAD tACC1 tRDS tRDH T1 T2 or T3 T1 A23 to A0 CS0 AS RD read D15 to D0 read tRSD2 Figure 20 10 Burst ROM Access Timing 1 State Access...

Page 838: ...2 03 page 808 of 1088 BREQ BACK tBACD tBZD A23 to A0 CS7 to CS0 AS RD HWR LWR tBACD tBZD tBRQS tBRQS Figure 20 11 External Bus Release Timing BREQO tBRQOD tBRQOD Figure 20 12 External Bus Request Outp...

Page 839: ...ns I O ports Output data delay time tPWD 50 40 ns Figure 20 13 Input data setup time tPRS 30 25 ns Input data hold time tPRH 30 25 ns TPU Timer output delay time tTOCD 50 40 ns Figure 20 14 Timer inpu...

Page 840: ...0 6 tScyc Input clock rise time tSCKr 1 5 1 5 tcyc Input clock fall time tSCKf 1 5 1 5 tcyc Transmit data delay time tTXD 50 40 ns Figure 20 21 Receive data setup time synchronous tRXS 50 40 ns Recei...

Page 841: ...tput Input capture input Note TIOCA0 to TIOCA5 TIOCB0 to TIOCB5 TIOCC0 TIOCC3 TIOCD0 TIOCD3 Figure 20 14 TPU Input Output Timing tTCKS tTCKS TCLKA to TCLKD tTCKWH tTCKWL Figure 20 15 TPU Clock Input T...

Page 842: ...0 TMCI1 tTMCWH tTMCWL Figure 20 17 8 Bit Timer Clock Input Timing tTMRS TMRI0 TMRI1 Figure 20 18 8 Bit Timer Reset Input Timing tWOVD WDTOVF tWOVD Figure 20 19 WDT Output Timing tScyc tSCKr tSCKW SCK0...

Page 843: ...3 page 813 of 1088 SCK0 SCK1 TxD0 TxD1 transmit data RxD0 RxD1 receive data tTXD tRXH tRXS Figure 20 21 SCI Input Output Timing Synchronous Mode tTRGS ADTRG Figure 20 22 A D Converter External Trigger...

Page 844: ...C 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V 2 MHz to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Item Min T...

Page 845: ...0 C to 85 C wide range specifications Condition B VCC 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V Vref 3 0 V to AVCC VSS AVSS 0 V 2 MHz to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide ran...

Page 846: ...l Value Unit Power supply voltage VCC 0 3 to 4 3 V Input voltage except port 4 Vin 0 3 to VCC 0 3 V Input voltage port 4 Vin 0 3 to AVCC 0 3 V Reference power supply voltage Vref 0 3 to AVCC 0 3 V Ana...

Page 847: ...ge RES STBY NMI MD2 to MD0 VIH VCC 0 9 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Ports 3 A to G 2 2 VCC 0 3 V Port 4 2 2 AVCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 VCC 0 1 V NMI EXTAL ports 3 4...

Page 848: ...e Idle 0 01 5 0 A During A D and D A conversion AICC 1 4 3 0 V 3 0 mA Reference power supply voltage Idle 0 01 5 0 A RAM standby voltage VRAM 2 0 V Notes 1 If the A D and D A converters are not used d...

Page 849: ...e output low current total Total of all output pins IOL 80 mA Permissible output high current per pin All output pins IOH 2 0 mA Permissible output high current total Total of all output pins IOH 40 m...

Page 850: ...standby oscillation stabilization time crystal tOSC2 10 ms External clock output stabilization delay time tDEXT 500 s Figure 20 3 2 Control Signal Timing Table 20 14 Control Signal Timing Condition C...

Page 851: ...DS 15 ns Read data hold time tRDH 0 ns Read data access time 1 tACC1 1 0 tcyc 35 ns Read data access time 2 tACC2 1 5 tcyc 35 ns Read data access time 3 tACC3 2 0 tcyc 35 ns Read data access time 4 tA...

Page 852: ...ge specification tTCKWH 1 5 tcyc Both edge specification tTCKWL 2 5 tcyc 8 bit timer Timer output delay time tTMOD 70 ns Figure 20 16 Timer reset input setup time tTMRS 40 ns Figure 20 18 Timer clock...

Page 853: ...missible signal source impedance 5 k Nonlinearity error 7 5 LSB Offset error 7 5 LSB Full scale error 7 5 LSB Quantization error 0 5 LSB Absolute accuracy 8 0 LSB 20 2 5 D A Conversion Characteristics...

Page 854: ...nput voltage FWE EMLE Vin 0 3 to VCC 0 3 V Input voltage except port 4 Vin 0 3 to VCC 0 3 V Input voltage port 4 Vin 0 3 to AVCC 0 3 V Reference power supply voltage Vref 0 3 to AVCC 0 3 V Analog powe...

Page 855: ...gh voltage RES STBY NMI MD2 to MD0 FWE EMLE VIH VCC 0 9 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Ports 3 A to G 2 2 VCC 0 3 V Port 4 2 2 AVCC 0 3 V Input low voltage RES STBY MD2 to MD0 FWE EMLE VIL 0 3 VCC...

Page 856: ...pply voltage Idle 0 01 5 0 A During A D and D A conversion AICC 1 4 3 0 V 3 0 mA Reference power supply voltage Idle 0 01 5 0 A RAM standby voltage VRAM 2 0 V Notes 1 If the A D and D A converters are...

Page 857: ...ge specifications Item Symbol Min Typ Max Unit Permissible output low current per pin All output pins IOL 2 0 mA Permissible output low current total Total of all output pins IOL 80 mA Permissible out...

Page 858: ...to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 40 500 ns Figure 20 2 Clock pulse high width tCH 15 ns Clock pulse low width tCL 15 ns Clock rise time...

Page 859: ...fications Ta 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns Figure 20 4 RES pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns Figure 20...

Page 860: ...a setup time tRDS 15 ns Read data hold time tRDH 0 ns Read data access time 1 tACC1 1 0 tcyc 20 ns Read data access time 2 tACC2 1 5 tcyc 20 ns Read data access time 3 tACC3 2 0 tcyc 20 ns Read data a...

Page 861: ...ure 20 15 Timer clock pulse width Single edge specification tTCKWH 1 5 tcyc Both edge specification tTCKWL 2 5 tcyc 8 bit timer Timer output delay time tTMOD 40 ns Figure 20 16 Timer reset input setup...

Page 862: ...signal source impedance 5 k Nonlinearity error 5 5 LSB Offset error 5 5 LSB Full scale error 5 5 LSB Quantization error 0 5 LSB Absolute accuracy 6 0 LSB 20 3 5 D A Conversion Characteristics Table 20...

Page 863: ...time wait Wait time after P bit clearing 1 5 s Wait time after PSU bit clearing 1 5 s Wait time after PV bit setting 1 4 s Wait time after H FF dummy write 1 2 s Wait time after PV bit clearing 1 2 s...

Page 864: ...Maximum programming time wait time after P bit setting z N tP max i 1 5 The maximum number of writes N should be set as shown below according to the actual set value of z so as not to exceed the maxi...

Page 865: ...0 3 V Reference power supply voltage Vref 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 4 3 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 2...

Page 866: ...VCC 0 07 V Input high voltage RES STBY NMI MD2 to MD0 VIH VCC 0 9 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Ports 3 A to G 2 2 VCC 0 3 V Port 4 2 2 AVCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 VCC...

Page 867: ...r supply voltage Idle TBD TBD A During A D and D A conversion AICC TBD 3 0 V TBD mA Reference power supply voltage Idle TBD TBD A RAM standby voltage VRAM 2 0 V Notes 1 If the A D and D A converters a...

Page 868: ...de range specifications Item Symbol Min Typ Max Unit Permissible output low current per pin All output pins IOL 2 0 mA Permissible output low current total Total of all output pins IOL 80 mA Permissib...

Page 869: ...a 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 40 500 ns Figure 20 2 Clock pulse high width tCH 15 ns Clock pulse low width tCL 15 ns Clock ris...

Page 870: ...specifications Ta 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns Figure 20 4 RES pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns Fig...

Page 871: ...ad data setup time tRDS 15 ns Read data hold time tRDH 0 ns Read data access time 1 tACC1 1 0 tcyc 20 ns Read data access time 2 tACC2 1 5 tcyc 20 ns Read data access time 3 tACC3 2 0 tcyc 20 ns Read...

Page 872: ...ns Figure 20 15 Timer clock pulse width Single edge specification tTCKWH 1 5 tcyc Both edge specification tTCKWL 2 5 tcyc 8 bit timer Timer output delay time tTMOD 40 ns Figure 20 16 Timer reset input...

Page 873: ...sible signal source impedance 5 k Nonlinearity error 5 5 LSB Offset error 5 5 LSB Full scale error 5 5 LSB Quantization error 0 5 LSB Absolute accuracy 6 0 LSB 20 4 5 D A Conversion Characteristics Ta...

Page 874: ...P 10 4 Years Notes 1 The exact programming and erase times depend on the characteristics of the data 2 Programming and erase times do not include data transfer time 3 This is the minimum number of rew...

Page 875: ...on Method 20 5 Usage Note Although both the F ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual there may be differences in the actual values of the electrical...

Page 876: ...Rev 5 00 12 03 page 846 of 1088...

Page 877: ...V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer...

Page 878: ...age 848 of 1088 Condition Code Notation Symbol Changes according to the result of the instruction Undetermined no guaranteed value 0 Always cleared to 0 1 Always set to 1 Not affected by execution of...

Page 879: ...2 Rd B 6 MOV B Rs ERd B 2 MOV B Rs d 16 ERd B 4 MOV B Rs d 32 ERd B 8 MOV B Rs ERd B 2 MOV B Rs aa 8 B 2 MOV B Rs aa 16 B 4 MOV B Rs aa 32 B 6 MOV W xx 16 Rd W 4 MOV W Rs Rd W 2 MOV W ERs Rd W 2 xx 8...

Page 880: ...32 ERd L 6 MOV L ERs ERd L 2 MOV L ERs ERd L 4 MOV L d 16 ERs ERd L 6 MOV L d 32 ERs ERd L 10 MOV L ERs ERd L 4 MOV L aa 16 ERd L 6 MOV L aa 32 ERd L 8 d 16 ERs Rd16 0 3 d 32 ERs Rd16 0 5 ERs Rd16 ER...

Page 881: ...W 2 PUSH L ERn L 4 LDM SP ERm ERn L 4 STM ERm ERn SP L 4 MOVFPE aa 16 Rd MOVTPE Rs aa 16 ERs32 ERd 0 4 ERs32 d 16 ERd 0 5 ERs32 d 32 ERd 0 7 ERd32 4 ERd32 ERs32 ERd 0 5 ERs32 aa 16 0 5 ERs32 aa 32 0...

Page 882: ...DS 2 ERd L 2 ADDS 4 ERd L 2 INC B Rd B 2 INC W 1 Rd W 2 INC W 2 Rd W 2 INC L 1 ERd L 2 INC L 2 ERd L 2 DAA Rd B 2 SUB B Rs Rd B 2 SUB W xx 16 Rd W 4 Rd8 xx 8 Rd8 1 Rd8 Rs8 Rd8 1 Rd16 xx 16 Rd16 3 2 Rd...

Page 883: ...ERd L 2 DAS Rd B 2 MULXU B Rs Rd B 2 MULXU W Rs ERd W 2 MULXS B Rs Rd B 4 MULXS W Rs ERd W 4 Rd16 Rs16 Rd16 3 1 ERd32 xx 32 ERd32 4 3 ERd32 ERs32 ERd32 4 1 Rd8 xx 8 C Rd8 5 1 Rd8 Rs8 C Rd8 5 1 ERd32...

Page 884: ...d W 2 NEG L ERd L 2 EXTU W Rd W 2 EXTU L ERd L 2 Rd16 Rs8 Rd16 RdH remainder 6 7 12 RdL quotient unsigned division ERd32 Rs16 ERd32 Ed remainder 6 7 20 Rd quotient unsigned division Rd16 Rs8 Rd16 RdH...

Page 885: ...LRMAC LDMAC STMAC EXTS W Rd W 2 EXTS L ERd L 2 TAS ERd 3 B 4 MAC ERn ERm CLRMAC LDMAC ERs MACH LDMAC ERs MACL STMAC MACH ERd STMAC MACL ERd bit 7 of Rd16 0 1 bits 15 to 8 of Rd16 bit 15 of ERd32 0 1 b...

Page 886: ...Rd B 2 XOR B Rs Rd B 2 XOR W xx 16 Rd W 4 XOR W Rs Rd W 2 XOR L xx 32 ERd L 6 XOR L ERs ERd L 4 NOT B Rd B 2 NOT W Rd W 2 NOT L ERd L 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 Rd16 0 2 Rd16 Rs16 R...

Page 887: ...AL W Rd W 2 SHAL W 2 Rd W 2 SHAL L ERd L 2 SHAL L 2 ERd L 2 SHAR B Rd B 2 SHAR B 2 Rd B 2 SHAR W Rd W 2 SHAR W 2 Rd W 2 SHAR L ERd L 2 SHAR L 2 ERd L 2 SHLL B Rd B 2 SHLL B 2 Rd B 2 SHLL W Rd W 2 SHLL...

Page 888: ...SHLR L ERd L 2 SHLR L 2 ERd L 2 ROTXL B Rd B 2 ROTXL B 2 Rd B 2 ROTXL W Rd W 2 ROTXL W 2 Rd W 2 ROTXL L ERd L 2 ROTXL L 2 ERd L 2 ROTXR B Rd B 2 ROTXR B 2 Rd B 2 ROTXR W Rd W 2 ROTXR W 2 Rd W 2 ROTXR...

Page 889: ...and Size xx Rn ERn d ERn ERn ERn aa d PC aa Mnemonic ROTL ROTR ROTL B Rd B 2 ROTL B 2 Rd B 2 ROTL W Rd W 2 ROTL W 2 Rd W 2 ROTL L ERd L 2 ROTL L 2 ERd L 2 ROTR B Rd B 2 ROTR B 2 Rd B 2 ROTR W Rd W 2 R...

Page 890: ...32 B 8 BCLR xx 3 Rd B 2 BCLR xx 3 ERd B 4 BCLR xx 3 aa 8 B 4 BCLR xx 3 aa 16 B 6 BCLR xx 3 aa 32 B 8 BCLR Rn Rd B 2 BCLR Rn ERd B 4 BCLR Rn aa 8 B 4 BCLR Rn aa 16 B 6 xx 3 of Rd8 1 1 xx 3 of ERd 1 4...

Page 891: ...16 B 6 BNOT Rn aa 32 B 8 BTST xx 3 Rd B 2 BTST xx 3 ERd B 4 BTST xx 3 aa 8 B 4 BTST xx 3 aa 16 B 6 Rn8 of aa 32 0 6 xx 3 of Rd8 xx 3 of Rd8 1 xx 3 of ERd 4 xx 3 of ERd xx 3 of aa 8 4 xx 3 of aa 8 xx...

Page 892: ...a 32 B 8 BILD xx 3 Rd B 2 BILD xx 3 ERd B 4 BILD xx 3 aa 8 B 4 BILD xx 3 aa 16 B 6 BILD xx 3 aa 32 B 8 BST xx 3 Rd B 2 BST xx 3 ERd B 4 BST xx 3 aa 8 B 4 xx 3 of aa 32 Z 5 Rn8 of Rd8 Z 1 Rn8 of ERd Z...

Page 893: ...BAND xx 3 aa 32 B 8 BIAND xx 3 Rd B 2 BIAND xx 3 ERd B 4 BIAND xx 3 aa 8 B 4 BIAND xx 3 aa 16 B 6 BIAND xx 3 aa 32 B 8 BOR xx 3 Rd B 2 BOR xx 3 ERd B 4 C xx 3 of aa 16 5 C xx 3 of aa 32 6 C xx 3 of Rd...

Page 894: ...B 4 BXOR xx 3 aa 16 B 6 BXOR xx 3 aa 32 B 8 BIXOR xx 3 Rd B 2 BIXOR xx 3 ERd B 4 BIXOR xx 3 aa 8 B 4 BIXOR xx 3 aa 16 B 6 BIXOR xx 3 aa 32 B 8 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C...

Page 895: ...1 2 3 Z 0 2 3 Z 1 2 3 V 0 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BRA d 8 BT d 8 2 if condition is true then BRA d 16 BT d 16 4 PC PC d BRN d 8 BF d 8 2 el...

Page 896: ...PC aa Mnemonic Bcc V 1 2 3 N 0 2 3 N 1 2 3 N V 0 2 3 N V 1 2 3 Z N V 0 2 3 Z N V 1 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BVS d 8 2 BVS d 16 4 BPL d 8 2 B...

Page 897: ...a d PC aa Mnemonic JMP BSR JSR RTS JMP ERn 2 JMP aa 24 4 JMP aa 8 2 BSR d 8 2 BSR d 16 4 JSR ERn 2 JSR aa 24 4 JSR aa 8 2 RTS 2 PC ERn 2 PC aa 24 3 PC aa 8 5 PC SP PC PC d 8 4 PC SP PC PC d 16 5 PC SP...

Page 898: ...s EXR W 6 LDC d 32 ERs CCR W 10 LDC d 32 ERs EXR W 10 LDC ERs CCR W 4 LDC ERs EXR W 4 LDC aa 16 CCR W 6 LDC aa 16 EXR W 6 LDC aa 32 CCR W 8 LDC aa 32 EXR W 8 PC SP CCR SP 1 8 9 EXR SP vector PC EXR SP...

Page 899: ...CCR aa 16 W 6 STC EXR aa 16 W 6 STC CCR aa 32 W 8 STC EXR aa 32 W 8 ANDC xx 8 CCR B 2 ANDC xx 8 EXR B 4 ORC xx 8 CCR B 2 ORC xx 8 EXR B 4 XORC xx 8 CCR B 2 XORC xx 8 EXR B 4 NOP 2 CCR Rd8 1 EXR Rd8 1...

Page 900: ...2 Cannot be used in the chip 3 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 4 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 5 Retains its previous...

Page 901: ...Rev 5 00 12 03 page 871 of 1088 A 2 Instruction Codes Table A 2 shows the instruction codes...

Page 902: ...BF d 8 BRN d 16 BF d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion ADD ADDS ADDX AND ANDC BAND Bcc B B W W...

Page 903: ...8 BGT d 16 BLE d 8 BLE d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion Bcc 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5...

Page 904: ...4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BCLR BIAND BILD BIOR B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 1 0 1 0 1 0 IMM erd erd IMM erd IMM erd IMM er...

Page 905: ...h byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BIST BIXOR BLD BNOT B B B B B B B B B B B B B B B B B B B B B B B B B 1 0 1 0 0 0 0 0 0 IMM erd IMM erd IMM erd IMM erd erd I...

Page 906: ...6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BOR BSET BSR BST BTST B B B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 0 0 0 0 0 0 0 IMM erd IMM erd erd IMM erd IMM erd erd abs...

Page 907: ...2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BTST BXOR CLRMAC CMP DAA DAS DEC DIVXS DIVXU EEPMOV B B B B B B B B B B W W L L B B B W W L L B W B W 0 0...

Page 908: ...at 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion EXTS EXTU INC JMP JSR LDC W L W L B W W L L B B B B W W W W W W W W W W 0 0 ern ern 0 0 0 0 e...

Page 909: ...s Rd MOV W d 32 ERs Rd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion LDC LDM LDMAC MAC MOV W W L L L L L B B...

Page 910: ...4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion MOV MOVFPE MOVTPE MULXS MULXU W W W W W W W W W L L L L L L L L L L L L L L B B B W B W 0 1 1 0 1 1 ers erd erd erd erd ers...

Page 911: ...monic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion NEG NOP NOT OR ORC POP PUSH ROTL B W L B W L B B W W L L B B W L W...

Page 912: ...Rd SHAL L ERd SHAL L 2 ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion ROTR ROTXL ROTXR RTE RTS SHAL B B W...

Page 913: ...ize Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion SHAR SHLL SHLR SLEEP STC B B W W L L B B W W L L B B W W L L B B W W W W...

Page 914: ...ize Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion STC STM STMAC SUB SUBS SUBX TAS TRAPA XOR W W W W L L L L L B W W L L L L...

Page 915: ...d General Register Register Field General Register 000 001 111 ER0 ER1 ER7 0000 0001 0111 1000 1001 1111 R0 R1 R7 E0 E1 E7 0000 0001 0111 1000 1001 1111 R0H R1H R7H R0L R1L R7L 16 Bit Register 8 Bit R...

Page 916: ...D E F 1 BRN DIVXU BNOT 2 BHI MULXU BCLR 3 BLS DIVXU BTST STC STMAC LDC LDMAC 4 ORC OR BCC RTS OR BOR BIOR 6 ANDC AND BNE RTE AND 5 XORC XOR BCS BSR XOR BXOR BIXOR BAND BIAND 7 LDC BEQ TRAPA BST BIST B...

Page 917: ...CMP 3 STM NOT BLS SUB SUB 4 SHLL SHLR ROTXL ROTXR BCC MOVFPE OR OR 5 INC EXTU DEC BCS XOR XOR 6 MAC BNE AND AND 7 INC SHLL SHLR ROTXL ROTXR EXTU DEC BEQ LDC STC 8 SLEEP BVC MOV ADDS SHAL SHAR ROTL RO...

Page 918: ...most significant bit of DH is 0 Instruction when most significant bit of DH is 1 Notes AH AL BH BL CH CL 01C05 01D05 01F06 7Cr06 1 7Cr07 1 7Dr06 1 7Dr07 1 7Eaa6 2 7Eaa7 2 7Faa6 2 7Faa7 2 0 MULXS BSET...

Page 919: ...Instruction when most significant bit of HH is 0 Instruction when most significant bit of HH is 1 Note aa is the absolute address specification 5th byte 6th byte EH EL FH FL 7th byte 8th byte GH GL H...

Page 920: ...quired for execution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N SN Examples Advanced mode program code and stack located in extern...

Page 921: ...us Cycle On Chip Memory 8 Bit Bus 16 Bit Bus 2 State Access 3 State Access 2 State Access 3 State Access Instruction fetch SI 1 4 2 4 6 2m 2 3 m Branch address read SJ Stack operation SK Byte data acc...

Page 922: ...D W Rs Rd 1 ADD L xx 32 ERd 3 ADD L ERs ERd 1 ADDS ADDS 1 2 4 ERd 1 ADDX ADDX xx 8 Rd 1 ADDX Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 AND W xx 16 Rd 2 AND W Rs Rd 1 AND L xx 32 ERd 3 AND L ERs ERd 2...

Page 923: ...2 BRA d 16 BT d 16 2 1 BRN d 16 BF d 16 2 1 BHI d 16 2 1 BLS d 16 2 1 BCC d 16 BHS d 16 2 1 BCS d 16 BLO d 16 2 1 BNE d 16 2 1 BEQ d 16 2 1 BVC d 16 2 1 BVS d 16 2 1 BPL d 16 2 1 BMI d 16 2 1 BGE d 1...

Page 924: ...BILD xx 3 Rd 1 BILD xx 3 ERd 2 1 BILD xx 3 aa 8 2 1 BILD xx 3 aa 16 3 1 BILD xx 3 aa 32 4 1 BIOR BIOR xx 8 Rd 1 BIOR xx 8 ERd 2 1 BIOR xx 8 aa 8 2 1 BIOR xx 8 aa 16 3 1 BIOR xx 8 aa 32 4 1 BIST BIST x...

Page 925: ...OT Rn Rd 1 BNOT Rn ERd 2 2 BNOT Rn aa 8 2 2 BNOT Rn aa 16 3 2 BNOT Rn aa 32 4 2 BOR BOR xx 3 Rd 1 BOR xx 3 ERd 2 1 BOR xx 3 aa 8 2 1 BOR xx 3 aa 16 3 1 BOR xx 3 aa 32 4 1 BSET BSET xx 3 Rd 1 BSET xx 3...

Page 926: ...n Rd 1 BTST Rn ERd 2 1 BTST Rn aa 8 2 1 BTST Rn aa 16 3 1 BTST Rn aa 32 4 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 ERd 2 1 BXOR xx 3 aa 8 2 1 BXOR xx 3 aa 16 3 1 BXOR xx 3 aa 32 4 1 CLRMAC CLRMAC Cannot be use...

Page 927: ...TU EXTU W Rd 1 EXTU L ERd 1 INC INC B Rd 1 INC W 1 2 Rd 1 INC L 1 2 ERd 1 JMP JMP ERn 2 JMP aa 24 2 1 JMP aa 8 2 2 1 JSR JSR ERn 2 2 JSR aa 24 2 2 1 JSR aa 8 2 2 2 LDC LDC xx 8 CCR 1 LDC xx 8 EXR 2 LD...

Page 928: ...MAC MAC ERn ERm Cannot be used in the chip MOV MOV B xx 8 Rd 1 MOV B Rs Rd 1 MOV B ERs Rd 1 1 MOV B d 16 ERs Rd 2 1 MOV B d 32 ERs Rd 4 1 MOV B ERs Rd 1 1 1 MOV B aa 8 Rd 1 1 MOV B aa 16 Rd 2 1 MOV B...

Page 929: ...ERd 1 MOV L ERs ERd 2 2 MOV L d 16 ERs ERd 3 2 MOV L d 32 ERs ERd 5 2 MOV L ERs ERd 2 2 1 MOV L aa 16 ERd 3 2 MOV L aa 32 ERd 4 2 MOV L ERs ERd 2 2 MOV L ERs d 16 ERd 3 2 MOV L ERs d 32 ERd 5 2 MOV L...

Page 930: ...2 OR W Rs Rd 1 OR L xx 32 ERd 3 OR L ERs ERd 2 ORC ORC xx 8 CCR 1 ORC xx 8 EXR 2 POP POP W Rn 1 1 1 POP L ERn 2 2 1 PUSH PUSH W Rn 1 1 1 PUSH L ERn 2 2 1 ROTL ROTL B Rd 1 ROTL B 2 Rd 1 ROTL W Rd 1 RO...

Page 931: ...2 Rd 1 ROTXR L ERd 1 ROTXR L 2 ERd 1 RTE RTE 2 2 3 1 1 RTS RTS 2 2 1 SHAL SHAL B Rd 1 SHAL B 2 Rd 1 SHAL W Rd 1 SHAL W 2 Rd 1 SHAL L ERd 1 SHAL L 2 ERd 1 SHAR SHAR B Rd 1 SHAR B 2 Rd 1 SHAR W Rd 1 SH...

Page 932: ...C W CCR d 32 ERd 5 1 STC W EXR d 32 ERd 5 1 STC W CCR ERd 2 1 1 STC W EXR ERd 2 1 1 STC W CCR aa 16 3 1 STC W EXR aa 16 3 1 STC W CCR aa 32 4 1 STC W EXR aa 32 4 1 STM STM L ERn ERn 1 SP 2 4 1 STM L E...

Page 933: ...nic I J K L M N XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XOR W xx 16 Rd 2 XOR W Rs Rd 1 XOR L xx 32 ERd 3 XOR L ERs ERd 2 XORC XORC xx 8 CCR 1 XORC xx 8 EXR 2 Notes 1 The number of state cycles is 2 when EXR...

Page 934: ...ruction Order of execution Read effective address word size read No read or write Read 2nd word of current instruction word size read Legend R B Byte size read R W Word size read W B Byte size write W...

Page 935: ...ree state access with no wait states Address bus RD HWR LWR R W 2nd Fetching 2nd byte of instruction at jump address Fetching 1st byte of instruction at jump address Fetching 4th byte of instruction F...

Page 936: ...XT ANDC xx 8 CCR R W NEXT ANDC xx 8 EXR R W 2nd R W NEXT BAND xx 3 Rd R W NEXT BAND xx 3 ERd R W 2nd R B EA R W M NEXT BAND xx 3 aa 8 R W 2nd R B EA R W M NEXT BAND xx 3 aa 16 R W 2nd R W 3rd R B EA R...

Page 937: ...BEQ d 16 R W 2nd Internal operation R W EA 1 state BVC d 16 R W 2nd Internal operation R W EA 1 state BVS d 16 R W 2nd Internal operation R W EA 1 state BPL d 16 R W 2nd Internal operation R W EA 1 s...

Page 938: ...d R W 4th R B EA R W M NEXT BIOR xx 3 Rd R W NEXT BIOR xx 3 ERd R W 2nd R B EA R W M NEXT BIOR xx 3 aa 8 R W 2nd R B EA R W M NEXT BIOR xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BIOR xx 3 aa 32 R W...

Page 939: ...Rd R W NEXT BSET xx 3 ERd R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 8 R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W B EA BSET xx 3 aa 32 R W 2nd R W 3r...

Page 940: ...3rd R W 4th R B EA R W M NEXT CLRMAC Cannot be used in the chip CMP B xx 8 Rd R W NEXT CMP B Rs Rd R W NEXT CMP W xx 16 Rd R W 2nd R W NEXT CMP W Rs Rd R W NEXT CMP L xx 32 ERd R W 2nd R W 3rd R W NEX...

Page 941: ...Rs CCR R W 2nd R W NEXT R W EA LDC ERs EXR R W 2nd R W NEXT R W EA LDC d 16 ERs CCR R W 2nd R W 3rd R W NEXT R W EA LDC d 16 ERs EXR R W 2nd R W 3rd R W NEXT R W EA LDC d 32 ERs CCR R W 2nd R W 3rd R...

Page 942: ...MOV B aa 16 Rd R W 2nd R W NEXT R B EA MOV B aa 32 Rd R W 2nd R W 3rd R W NEXT R B EA MOV B Rs ERd R W NEXT W B EA MOV B Rs d 16 ERd R W 2nd R W NEXT W B EA MOV B Rs d 32 ERd R W 2nd R W 3rd R W 4th R...

Page 943: ...2 ERd R W 2nd R W M 3rd R W 4th R W NEXT R W M EA R W EA 2 MOV L ERs ERd R W 2nd R W M NEXT W W M EA W W EA 2 MOV L ERs d 16 ERd R W 2nd R W M 3rd R W NEXT W W M EA W W EA 2 MOV L ERs d 32 ERd R W 2nd...

Page 944: ...W EA 1 state PUSH L ERn R W 2nd R W M NEXT Internal operation W W M EA W W EA 2 1 state ROTL B Rd R W NEXT ROTL B 2 Rd R W NEXT ROTL W Rd R W NEXT ROTL W 2 Rd R W NEXT ROTL L ERd R W NEXT ROTL L 2 ERd...

Page 945: ...SHAR B 2 Rd R W NEXT SHAR W Rd R W NEXT SHAR W 2 Rd R W NEXT SHAR L ERd R W NEXT SHAR L 2 ERd R W NEXT SHLL B Rd R W NEXT SHLL B 2 Rd R W NEXT SHLL W Rd R W NEXT SHLL W 2 Rd R W NEXT SHLL L ERd R W N...

Page 946: ...ck H 3 W W stack L 3 1 state STM L ERn ERn 2 SP R W 2nd R W M NEXT Internal operation W W M stack H 3 W W stack L 3 1 state STM L ERn ERn 3 SP R W 2nd R W M NEXT Internal operation W W M stack H 3 W W...

Page 947: ...ts of ER6 Both registers are incremented by 1 after execution of the instruction n is the initial value of R4L or R4 If n 0 these bus cycles are not executed 3 Repeated two times to save or restore tw...

Page 948: ...r word operands 7 for byte operands Si Di Ri Dn 0 1 Z C The i th bit of the source operand The i th bit of the destination operand The i th bit of the result The specified bit in the destination opera...

Page 949: ...m Rm ADDS ADDX H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm AND 0 N Rm Z Rm Rm 1 R0 ANDC Stores the corresponding bits of the result No flags change when the...

Page 950: ...decimal arithmetic carry DAS N Rm Z Rm Rm 1 R0 C decimal arithmetic borrow DEC N Rm Z Rm Rm 1 R0 V Dm Rm DIVXS N Sm Dm Sm Dm Z Sm Sm 1 S0 DIVXU N Sm Z Sm Sm 1 S0 EEPMOV EXTS 0 N Rm Z Rm Rm 1 R0 EXTU 0...

Page 951: ...NEG H Dm 4 Rm 4 N Rm Z Rm Rm 1 R0 V Dm Rm C Dm Rm NOP NOT 0 N Rm Z Rm Rm 1 R0 OR 0 N Rm Z Rm Rm 1 R0 ORC Stores the corresponding bits of the result No flags change when the operand is EXR POP 0 N Rm...

Page 952: ...corresponding bits of the result RTS SHAL N Rm Z Rm Rm 1 R0 V Dm Dm 1 Dm Dm 1 1 bit shift V Dm Dm 1 Dm 2 Dm Dm 1 Dm 2 2 bit shift C Dm 1 bit shift or C Dm 1 2 bit shift SHAR 0 N Rm Z Rm Rm 1 R0 C D0...

Page 953: ...4 N Rm Z Rm Rm 1 R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm SUBS SUBX H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm TAS 0 N Dm Z Dm Dm 1 D0 TRAPA XOR 0 N Rm Z...

Page 954: ...6 32 1 bits H FBFF MRB CHNE DISEL CHNS DAR CRA CRB H FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3 16 bits H FE81 TMDR3 BFB BFA MD3 MD2 MD1 MD0 H FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3...

Page 955: ...TIER5 TTGE TCIEU TCIEV TGIEB TGIEA H FEA5 TSR5 TCFD TCFU TCFV TGFB TGFA H FEA6 TCNT5 H FEA7 H FEA8 TGR5A H FEA9 H FEAA TGR5B H FEAB H FEB0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR...

Page 956: ...W00 H FED4 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 H FED5 BCRL BRLE BREQOE EAE WAITE H FEDB RAMER 2 RAMS RAM2 RAM1 RAM0 Flash memory 8 bits H FF2C ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA...

Page 957: ...DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR H FF61 P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR H FF62 P3DR P35DR P34DR P33DR P32DR P31DR P30DR H FF69 PADR PA3DR PA2DR PA1DR PA0DR H FF6A PBDR...

Page 958: ...CHR BLK 5 PE O E STOP BCP1 6 MP BCP0 7 CKS1 CKS0 8 bits H FF81 BRR1 H FF82 SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI1 smart card interface 1 H FF83 TDR1 H FF84 SSR1 TDRE RDRF ORER FER ERS 8 PER TEND...

Page 959: ...CLR0 CKS2 CKS1 CKS0 16 bits H FFB1 TCR1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H FFB2 TCSR0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 8 bit timer channel 0 1 H FFB3 TCSR1 CMFB CMFA OVF OS3 OS2 OS1 OS0 H...

Page 960: ...FLMCR2 FLER H FFCA 11 EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H FFCB 11 EBR2 EB13 EB12 EB11 EB10 EB9 EB8 Flash memory 2315 F ZTAT 2314 F ZTAT H FFC8 12 FLMCR1 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 8 bits H FF...

Page 961: ...3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H FFD4 TIER0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA H FFD5 TSR0 TCFV TGFD TGFC TGFB TGFA H FFD6 TCNT0 H FFD7 H FFD8 TGR0A H FFD9 H FFDA TGR0B H FFDB H FFDC TGR0C H FFD...

Page 962: ...bits otherwise 2 Valid only in the F ZTAT versions but the H8S 2314 F ZTAT In the H8S 2314 F ZTAT this cannot be used and must not be accessed 3 Valid only in the F ZTAT versions 4 Functions as C A fo...

Page 963: ...nterrupt priority register E IPRE R W H 77 H FEC8 Interrupt priority register F IPRF R W H 77 H FEC9 Interrupt priority register G IPRG R W H 77 H FECA Interrupt priority register H IPRH R W H 77 H FE...

Page 964: ...7 H 00 H FFB2 Timer constant register A0 TCORA0 R W H FF H FFB4 Timer constant register B0 TCORB0 R W H FF H FFB6 Timer counter 0 TCNT0 R W H 00 H FFB8 Timer control register 1 TCR1 R W H 00 H FFB1 8...

Page 965: ...W 2 H 84 H FF84 Receive data register 1 RDR1 R H 00 H FF85 Smart card mode register 1 SCMR1 R W H F2 H FF86 All SCI channels Module stop control register MSTPCR R W H 3FFF H FF3C SMCI0 Serial mode reg...

Page 966: ...ADR0 R W H 00 H FFA4 D A data register 1 DADR1 R W H 00 H FFA5 D A control register 01 DACR01 R W H 1F H FFA6 All DAC channels Module stop control register MSTPCR R W H 3FFF H FF3C On chip RAM System...

Page 967: ...R2B R W H FFFF H FFFA TPU3 Timer control register 3 TCR3 R W H 00 H FE80 Timer mode register 3 TMDR3 R W H C0 H FE81 Timer I O control register 3H TIOR3H R W H 00 H FE82 Timer I O control register 3L...

Page 968: ...gister 1 FLMCR1 14 R W 11 H 00 H 80 12 H FFC8 10 Flash memory Flash memory control register 2 FLMCR2 14 R W 11 H 00 H FFC9 10 Erase block register 1 EBR1 14 R W 11 H 00 13 H FFCA 10 Erase block regist...

Page 969: ...ain control register P3ODR R W H 00 H FF76 Port 4 Port 4 register PORT4 R Undefined H FF53 Port A Port A data direction register PADDR W H 0 16 H FEB9 Port A data register PADR R W H 0 16 H FF69 Port...

Page 970: ...t be located in external memory space Do not clear the RAME bit in SYSCR to 0 when using the DTC 5 Determined by the MCU operating mode 6 Bits used for pulse output cannot be written to 7 Only 0 can b...

Page 971: ...return an undefined value if read and cannot be written to 16 Value of bits 3 to 0 17 The initial value depends on the mode 18 Value of bits 4 to 0 19 Valid only in the F ZTAT versions but the H8S 231...

Page 972: ...rmal mode Repeat mode Block transfer mode 0 1 0 1 DTC Data Transfer Size 0 1 Byte size transfer DTC Transfer Mode Select 0 1 Word size transfer Destination side is repeat area or block area Source sid...

Page 973: ...ad Write DTC Chain Transfer Enable DTC Chain Transfer Select CHNE 0 1 1 CHNS 0 1 Description No chain transfer At end of DTC data transfer DTC waits for activation Chain transfer every time Chain tran...

Page 974: ...10 9 8 7 6 5 4 3 2 1 0 CRAH CRAL Specifies the number of DTC data transfers Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Und...

Page 975: ...n 16 Internal clock counts on 64 External clock counts on TCLKA pin input Internal clock counts on 1024 Internal clock counts on 256 Internal clock counts on 4096 Timer Prescaler 0 1 0 1 0 1 0 1 0 1 0...

Page 976: ...y 0 1 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1 2 Don t care MD3...

Page 977: ...e register Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA3 pin Capture input source is channel 4 count clock Input capture at TCNT4 count up count...

Page 978: ...ch Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is TIOCC3 pin TGR3C is input capture register Capture input so...

Page 979: ...t request TCIV by TCFV disabled Interrupt request TCIV by TCFV enabled Overflow Interrupt Enable TGR Interrupt Enable D TGR Interrupt Enable C TGR Interrupt Enable B 0 1 Interrupt request TGIA by TGFA...

Page 980: ...EL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 Input Capture Output Compare Flag B 1 Setting conditions 0 Clearing conditions When DTC is activated by TGIA interrupt while DI...

Page 981: ...4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W Up counter TGR3A Timer General Register 3A H FE88 TPU3 TGR3B Timer General Register 3B H FE8A TPU3 TGR3C Timer General Register 3C H FE8C TPU3 TGR3D Timer Gener...

Page 982: ...4 Counts on TCNT5 overflow underflow Timer Prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 0 TPSC0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Bit Initial value...

Page 983: ...1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Don t care 7 1 6 1 5 0 4 0 3 MD3 0 R W 0 MD0 0 R W 2 MD2 0 R...

Page 984: ...e match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges TGR4A is input capture register Capture input source is TIOCA4 pin Input captu...

Page 985: ...t request TGIA by TGFA bit enabled Interrupt request TGIB by TGFB bit disabled Interrupt request TGIB by TGFB bit enabled TGR Interrupt Enable B Interrupt request TCIV by TCFV disabled Interrupt reque...

Page 986: ...e Flag B 1 0 Clearing conditions When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after reading TGFA 1 Input Capture Output Compare Flag A 1 Setting...

Page 987: ...ounter can be used as an up down counter only in phase counting mode or when performing overflow underflow counting on another channel In other cases it functions as an up counter Up down counter TGR4...

Page 988: ...7 0 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 0 TPSC0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Bit Initial value Read Write Note 0 1 Clock Edge 0 1 Count at rising edge Count at falling edge C...

Page 989: ...1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note MD3 is a reserved bit In a write it should always be written...

Page 990: ...put is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge...

Page 991: ...abled A D Conversion Start Request Enable 0 1 Interrupt request TCIU by TCFU disabled Interrupt request TCIU by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B 0 1 Interrupt request TGI...

Page 992: ...value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Note Can only be written with 0 for flag clearing Clearing conditions When DTC is activated by...

Page 993: ...another channel In other cases it functions as an up counter Up down counter TGR5A Timer General Register 5A H FEA8 TPU5 TGR5B Timer General Register 5B H FEAA TPU5 15 1 R W 14 1 R W 13 1 R W 12 1 R...

Page 994: ...e P3DDR Port 3 Data Direction Register H FEB2 Port 3 7 Undefined 6 Undefined 5 P35DDR 0 W 4 P34DDR 0 W 3 P33DDR 0 W 0 P30DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W Specify input or output for individual port 3...

Page 995: ...C0DDR 0 W 2 PC2DDR 0 W 1 PC1DDR 0 W Specify input or output for individual port C pins Bit Initial value Read Write PDDDR Port D Data Direction Register H FEBC Port D 7 PD7DDR 0 W 6 PD6DDR 0 W 5 PD5DD...

Page 996: ...lue Read Write Mode 7 Initial value Read Write Note Modes 6 and 7 cannot be used in the ROMless versions PGDDR Port G Data Direction Register H FEBF Port G 7 Undefined Undefined 6 Undefined Undefined...

Page 997: ...er IPRI Interrupt Priority Register I H FECC Interrupt Controller IPRJ Interrupt Priority Register J H FECD Interrupt Controller IPRK Interrupt Priority Register K H FECE Interrupt Controller 7 0 6 IP...

Page 998: ...not be used in the ROMless versions 0 1 Area n is designated for 16 bit access Area n is designated for 8 bit access n 7 to 0 ASTCR Access State Control Register H FED1 Bus Controller 7 AST7 1 R W 6 A...

Page 999: ...ram wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait sta...

Page 1000: ...ram wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait sta...

Page 1001: ...in case of successive external read cycles in different areas Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case...

Page 1002: ...hip ROM H8S 2317 On chip ROM at addresses H 010000 to H 01FFFF and reserved area 1 at addresses H 020000 to H 03FFFF H8S 2311 H8S 2313 and H8S 2316 Reserved area 1 Addresses H 010000 to H 03FFFF 2 Exp...

Page 1003: ...Select RAM1 0 1 0 1 RAM0 0 1 0 1 0 1 0 1 RAM Area Block Name Don t care H FFDC00 to H FFEBFF H 000000 to H 000FFF H 001000 to H 001FFF H 002000 to H 002FFF H 003000 to H 003FFF H 004000 to H 004FFF H...

Page 1004: ...A 0 R W 9 IRQ4SCB 0 R W Bit Initial value Read Write ISCRH 7 IRQ3SCB 0 R W 6 IRQ3SCA 0 R W 5 IRQ2SCB 0 R W 4 IRQ2SCA 0 R W 3 IRQ1SCB 0 R W 0 IRQ0SCA 0 R W 2 IRQ1SCA 0 R W 1 IRQ0SCB 0 R W IRQ7 to IRQ4...

Page 1005: ...egister H FF2E Interrupt Controller 7 IRQ7E 0 R W 6 IRQ6E 0 R W 5 IRQ5E 0 R W 4 IRQ4E 0 R W 3 IRQ3E 0 R W 0 IRQ0E 0 R W 2 IRQ2E 0 R W 1 IRQ1E 0 R W IRQn Enable 0 1 IRQn interrupt disabled IRQn interru...

Page 1006: ...IRQn input is high When IRQn interrupt exception handling is executed while falling rising or both edge detection is set IRQnSCB 1 or IRQnSCA 1 When the DTC is activated by an IRQn interrupt and the D...

Page 1007: ...en the DISEL bit is 0 and the specified number of transfers have not ended Correspondence between Interrupt Sources and DTCER Bits Register 7 6 5 4 3 2 1 0 DTCERA IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IR...

Page 1008: ...transfer has ended When the specified number of transfers have ended During data transfer due to software activation Sets vector number for DTC software activation Bit Initial value Read Write Note Bi...

Page 1009: ...1 0 1 0 1 0 1 0 1 0 1 Standby time 8192 states Standby time 16384 states Standby time 32768 states Standby time 65536 states Standby time 131072 states Standby time 262144 states Reserved Standby time...

Page 1010: ...o this bit RAM Enable 0 On chip RAM disabled 1 On chip RAM enabled NMI Input Edge Select 0 Falling edge 1 Rising edge Interrupt Control Mode Selection 0 1 Interrupt control mode 0 0 1 0 1 Setting proh...

Page 1011: ...k Select Division Ratio Select Reserved Only 0 should be written to this bit 0 1 0 1 0 1 0 1 0 1 0 1 Bus master is in high speed mode Medium speed clock is 2 Medium speed clock is 4 Medium speed clock...

Page 1012: ...gister L H FF3D Power Down State 15 0 R W 14 0 R W 13 1 R W 12 1 R W 11 1 R W 10 1 R W 9 1 R W 8 1 R W 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 2 1 R W 1 1 R W 0 1 R W MSTPCRH MSTPCRL Specifies module...

Page 1013: ...T and H8S 2314 F ZTAT Flash control registers are not selected for addresses H FFFFC8 to H FFFFCB H8S 2319C F ZTAT Flash control registers are not selected for addresses H FFFFC4 to H FFFFCF H8S 2319...

Page 1014: ...when BRLE 0 CS25E 1 and PF0DDR 1 Port F0 chip select 4 select 1 0 1 PF1 is PF1 BACK IRQ1 pin PF1 is PF1 BACK IRQ1 CS5 pin CS5 output is enabled when BRLE 0 CS25E 1 and PF1DDR 1 Port F1 chip select 5...

Page 1015: ...e Read Write PORT2 Port 2 Register H FF51 Port 2 7 P27 R 6 P26 R 5 P25 R 4 P24 R 3 P23 R 0 P20 R 2 P22 R 1 P21 R State of port 2 pins Note Determined by the state of pins P27 to P20 Bit Initial value...

Page 1016: ...ad Write PORTA Port A Register H FF59 Port A 7 Undefined 6 Undefined 5 Undefined 4 Undefined 3 PA3 R 0 PA0 R 2 PA2 R 1 PA1 R State of port A pins Note Determined by the state of pins PA3 to PA0 Bit In...

Page 1017: ...value Read Write PORTD Port D Register H FF5C Port D 7 PD7 R 6 PD6 R 5 PD5 R 4 PD4 R 3 PD3 R 0 PD0 R 2 PD2 R 1 PD1 R State of port D pins Note Determined by the state of pins PD7 to PD0 Bit Initial va...

Page 1018: ...TG Port G Register H FF5F Port G 7 Undefined 6 Undefined 5 Undefined 4 PG4 R 3 PG3 R 0 PG0 R 2 PG2 R 1 PG1 R State of port G pins Note Determined by the state of pins PG4 to PG0 Bit Initial value Read...

Page 1019: ...0 P30DR 0 R W 2 P32DR 0 R W 1 P31DR 0 R W Stores output data for port 3 pins P35 to P30 Bit Initial value Read Write PADR Port A Data Register H FF69 Port A 7 Undefined 6 Undefined 5 Undefined 4 Unde...

Page 1020: ...te PDDR Port D Data Register H FF6C Port D 7 PD7DR 0 R W 6 PD6DR 0 R W 5 PD5DR 0 R W 4 PD4DR 0 R W 3 PD3DR 0 R W 0 PD0DR 0 R W 2 PD2DR 0 R W 1 PD1DR 0 R W Stores output data for port D pins PD7 to PD0...

Page 1021: ...ster H FF6F Port G 7 Undefined 6 Undefined 5 Undefined 4 PG4DR 0 R W 3 PG3DR 0 R W 0 PG0DR 0 R W 2 PG2DR 0 R W 1 PG1DR 0 R W Stores output data for port G pins PG4 to PG0 Bit Initial value Read Write...

Page 1022: ...Controls the MOS input pull up function incorporated into port C on a bit by bit basis Bit Initial value Read Write PDPCR Port D MOS Pull Up Control Register H FF73 Port D 7 PD7PCR 0 R W 6 PD6PCR 0 R...

Page 1023: ...32ODR 0 R W 1 P31ODR 0 R W Controls the PMOS on off status for each port 3 pin P35 to P30 Bit Initial value Read Write PAODR Port A Open Drain Control Register H FF77 Port A 7 Undefined 6 Undefined 5...

Page 1024: ...in the received character and parity bit combined 2 When odd parity is selected the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined Rec...

Page 1025: ...ard interface 0 1 Even parity 1 Odd parity 2 Parity Mode 0 1 0 1 0 1 clock 4 clock 16 clock 64 clock Clock Select Bit Initial value Read Write Note etu Elementary Time Unit Time for transfer of 1 bit...

Page 1026: ...it Rate Register 0 H FF79 SCI0 Smart Card Interface 0 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Sets the serial transfer bit rate Note For details see section 12 2 8 Bit Rate Reg...

Page 1027: ...s in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 1 Receive data full interrupt RXI request and receive error interrupt ERI request enabled 1 0 1 0 Notes 1 Outputs a...

Page 1028: ...output as SCK output pin Clock output as SCK output pin Fixed high output as SCK output pin Clock output as SCK output pin Note TEI clearing can be performed by reading 1 from the TDRE flag in SSR th...

Page 1029: ...3 page 999 of 1088 TDR0 Transmit Data Register 0 H FF7B SCI0 Smart Card Interface 0 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Stores data for serial transmission Bit Initial valu...

Page 1030: ...interrupt and reads data from RDR Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the DTC is activated by a TXI interrupt and writes data to TDR Setting conditions When the TE...

Page 1031: ...ction of parity error has been sent by receiving device Setting condition When the error signal is sampled at the low level Clearing condition When 0 is written to ORER after reading ORER 1 1 Setting...

Page 1032: ...R contents are transmitted LSB first Receive data is stored in RDR LSB first Smart Card Data Direction 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is Smart Card Da...

Page 1033: ...ote When 7 bit data is selected the MSB bit 7 of TDR is not transmitted With 7 bit data it is not possible to select LSB first or MSB first transfer 1 When even parity is selected the parity bit added...

Page 1034: ...elect Bit Initial value Read Write Note etu Elementary Time Unit Time for transfer of 1 bit 0 1 0 1 0 1 32 clocks 64 clocks 372 clocks 256 clocks Base Clock Pulse BCP1 BCP0 Base Clock Pulse 0 1 Normal...

Page 1035: ...it Rate Register 1 H FF81 SCI1 Smart Card Interface 1 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Note For details see section 12 2 8 Bit Rate Register BRR Sets the serial transfer...

Page 1036: ...gs in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 1 Receive data full interrupt RXI request and receive error interrupt ERI request enabled 1 0 1 0 Notes 1 Outputs a...

Page 1037: ...output as SCK output pin Clock output as SCK output pin Fixed high output as SCK output pin Clock output as SCK output pin Note TEI clearing can be performed by reading 1 from the TDRE flag in SSR th...

Page 1038: ...3 page 1008 of 1088 TDR1 Transmit Data Register 1 H FF83 SCI1 Smart Card Interface 1 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Stores data for serial transmission Bit Initial val...

Page 1039: ...interrupt and reads data from RDR Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the DTC is activated by a TXI interrupt and writes data to TDR Setting conditions When the TE...

Page 1040: ...ction of parity error has been sent by receiving device Setting condition When the error signal is sampled at the low level Clearing condition When 0 is written to ORER after reading ORER 1 1 Setting...

Page 1041: ...R contents are transmitted LSB first Receive data is stored in RDR LSB first Smart Card Data Direction 0 TDR contents are transmitted as they are Receive data is stored in RDR as it is Smart Card Data...

Page 1042: ...erter ADDRCL A D Data Register CL H FF95 A D Converter ADDRDH A D Data Register DH H FF96 A D Converter ADDRDL A D Data Register DL H FF97 A D Converter 15 AD9 0 R 14 AD8 0 R 13 AD7 0 R 12 AD6 0 R 11...

Page 1043: ...election Description 0 1 A D conversion stopped A D Start 0 A D End Flag Bit Initial value Read Write Single mode A D conversion is started Cleared to 0 automatically when conversion ends Scan mode A...

Page 1044: ...enabled A D conversion start by external trigger pin ADTRG is enabled TRGS1 TRGS1 0 1 0 1 0 1 Description Clock Select CKS1 is used in combination with CKS bit 3 in ADCSR Reserved Only 1 should be wri...

Page 1045: ...nnel 1 D A conversion disabled Channel 0 and 1 D A conversion enabled Channel 0 D A conversion disabled Channel 1 D A conversion enabled Channel 0 and 1 D A conversion enabled Channel 0 and 1 D A conv...

Page 1046: ...Enable 1 2 0 1 CS1 CS6 and CS7 output disabled can be used as I O ports CS1 CS6 and CS7 output enabled CS167 Enable 1 2 Reserved Only 0 should be written to these bits 7 0 R W 6 0 R W 5 CS167E 1 R W 4...

Page 1047: ...t falling edge 1 0 1 External clock counted at both rising and falling edges 1 Clock Select 0 1 CMFB interrupt requests CMIB are disabled CMFB interrupt requests CMIB are enabled Compare Match Interru...

Page 1048: ...y 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs 0 1 0 1 Output Select Bit Initial value Read Write Bit Initial value Read Wr...

Page 1049: ...egister B0 H FFB6 8 Bit Timer Channel 0 TCORB1 Time Constant Register B1 H FFB7 8 Bit Timer Channel 1 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 10 1 R W 9 1 R W 8 1 R W 7 1 R W 6 1 R W 5 1 R W 4 1...

Page 1050: ...mer Mode Select 0 1 TCNT is initialized to H 00 and halted TCNT counts Timer Enable Clock Select CKS2 CKS1 CKS0 Clock Overflow period when 20 MHz 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 64 128 512 2048 8192 327...

Page 1051: ...ion Cleared by reading RSTCSR when WOVF 1 then writing 0 to WOVF Watchdog Timer Overflow Flag Notes The method for writing to RSTCSR is different from that for general registers to prevent accidental...

Page 1052: ...l will be changed to the set initial output value Bit Initial value Read Write TSYR Timer Synchro Register H FFC1 TPU 7 0 6 0 5 SYNC5 0 R W 4 SYNC4 0 R W 3 SYNC3 0 R W 0 SYNC0 0 R W 2 SYNC2 0 R W 1 SY...

Page 1053: ...and SWE 1 Erase Setup 0 Erase setup cleared 1 Erase setup Setting condition When FWE 1 and SWE 1 Note Valid for addresses H 000000 to H 03FFFF in H8S 2318 F ZTAT H 000000 to H 01FFFF in H8S 2317 F ZTA...

Page 1054: ...g condition When SWE1 1 Software Write Enable 1 0 Writes disabled 1 Writes enabled Flash Write Enable Always read as 1 and cannot be written to Note Valid for addresses H 000000 to H 03FFFF Note Valid...

Page 1055: ...0 0 0 2 0 1 0 Bit Initial value Read Write Flash Memory Error 0 Flash memory is operating normally Flash memory program erase protection error protection is disabled Clearing condition Reset or hardwa...

Page 1056: ...n When SWE2 1 Software Write Enable 2 0 Writes disabled 1 Writes enabled Note Valid for addresses H 040000 to H 07FFFF Erase Verify 2 0 Erase verify mode cleared 1 Transition to erase verify mode Sett...

Page 1057: ...1 EB1 0 R W Bit EBR1 Initial value Read Write 7 EB15 3 0 R W 3 6 EB14 3 0 R W 3 5 EB13 2 0 R W 2 4 EB12 2 0 R W 2 3 EB11 1 0 R W 1 0 EB8 0 R W 2 EB10 1 0 R W 1 1 EB9 0 R W Bit EBR2 Initial value Read...

Page 1058: ...ting condition See section 17 25 3 Error Protection Source Program Copy Operation 0 1 Download of the on chip programming erasing program to the on chip RAM is not executed Clear condition When downlo...

Page 1059: ...n chip programming program is selected Reserved bits These bits are always read as 0 The write value should always be 0 FECS Flash Erase Code Select Register H FFC6 FLASH Valid only in the H8S 2319C F...

Page 1060: ...h MAT Select Register H FFC9 FLASH Valid only in the H8S 2319C F ZTAT 7 MS7 0 1 R W 6 MS6 0 0 R W 5 MS5 0 1 R W 4 MS4 0 0 R W 3 MS3 0 1 R W 0 MS0 0 0 R W 2 MS2 0 0 R W 1 MS1 0 1 R W Bit Initial value...

Page 1061: ...s H 00 H 01 H 02 Download start address is set to H FFBC00 Download start address is set to H FFCC00 Download start address is set to H FFDC00 H 03 Download start address is set to H FFEC00 H 04 to H...

Page 1062: ...TCLKC pin input External clock counts on TCLKD pin input Time Prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit Initial value Read Write Notes 1 Synchronous operation setting is performed by setting the SYNC...

Page 1063: ...Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1 2 MD3 is a reserved bit In a write it s...

Page 1064: ...000 and 1 is used as the TCNT1 count clock this setting is invalid and input capture does not occur Bit Initial value Read Write Initial output is 0 output TGR0A is input capture register Output disa...

Page 1065: ...ffer register Bit Initial value Read Write TGR0C is output compare register 1 Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare mat...

Page 1066: ...led Interrupt request TCIV by TCFV enabled Overflow Interrupt Enable TGR Interrupt Enable D TGR Interrupt Enable C TGR Interrupt Enable B 0 1 Interrupt request TGIA by TGFA bit disabled TGR Interrupt...

Page 1067: ...to TGFB after reading TGFB 1 Setting conditions When TCNT TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functi...

Page 1068: ...4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W Up counter TGR0A Timer General Register 0A H FFD8 TPU0 TGR0B Timer General Register 0B H FFDA TPU0 TGR0C Timer General Register 0C H FFDC TPU0 TGR0D Timer Gener...

Page 1069: ...6 Counts on TCNT2 overflow underflow Time Prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 0 TPSC0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Note This setting...

Page 1070: ...1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note MD3 is a reserved bit In a write it should always be written...

Page 1071: ...at both edges Initial output is 0 output TGR1A is input capture register Output disabled Initial output is 1 output Capture input source is TIOCA1 pin Capture input source is TGR0A compare match inpu...

Page 1072: ...equest Enable 0 1 Interrupt request TCIU by TCFU disabled Interrupt request TCIU by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B 0 1 Interrupt request TGIA by TGFA bit disabled TGR I...

Page 1073: ...is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Clearing conditions When DTC is activated b...

Page 1074: ...ite This timer counter can be used as an up down counter only in phase counting mode or when performing overflow underflow counting on another channel In other cases it functions as an up counter TGR1...

Page 1075: ...pin input Internal clock counts on 1024 Time Prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 0 TPSC0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Note This sett...

Page 1076: ...1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note MD3 is a reserved bit In a write it should always be written...

Page 1077: ...t capture at rising edge Input capture at falling edge Input capture at both edges Don t care Bit Initial value Read Write Output disabled Initial output is 0 output Output disabled Initial output is...

Page 1078: ...equest Enable 0 1 Interrupt request TCIU by TCFU disabled Interrupt request TCIU by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B 0 1 Interrupt request TGIA by TGFA bit disabled TGR I...

Page 1079: ...is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Clearing conditions When DTC is activated b...

Page 1080: ...own counter only in phase counting mode or when performing overflow underflow counting on another channel In other cases it functions as an up counter Up down counter Bit Initial value Read Write TGR2...

Page 1081: ...1n RDR1 RPOR1 Internal address bus Internal data bus Bus controller TPU module AmE bit Output compare output PWM output enable Output compare output PWM output Input capture input WDDR1 Write to P1DDR...

Page 1082: ...nternal address bus Bus controller TPU module AmE bit Output compare output PWM output enable Output compare output PWM output External clock input Input capture input WDDR1 Write to P1DDR WDR1 Write...

Page 1083: ...R C Q D P1n RDR1 RPOR1 Internal data bus TPU module Output compare output PWM output enable Output compare output PWM output Input capture input WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1 Read P1DR...

Page 1084: ...RDR1 RPOR1 Internal data bus TPU module Output compare output PWM output enable Output compare output PWM output External clock input Input capture input WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1...

Page 1085: ...R P2nDR C Q D P2n RDR2 RPOR2 TPU module Output compare output PWM output enable Output compare output PWM output Input capture input Internal data bus WDDR2 Write to P2DDR WDR2 Write to P2DR RDR2 Rea...

Page 1086: ...bus SCI module Serial transmit enable Serial transmit data P3nDR Reset WODR3 R C Q D P3nODR 1 2 WDDR3 Write to P3DDR WDR3 Write to P3DR WODR3 Write to P3ODR RDR3 Read P3DR RPOR3 Read port 3 RODR3 Rea...

Page 1087: ...I module Serial receive data enable Serial receive data P3nDR Reset WODR3 R C Q D P3nODR 1 2 WDDR3 Write to P3DDR WDR3 Write to P3DR WODR3 Write to P3ODR RDR3 Read P3DR RPOR3 Read port 3 RODR3 Read P3...

Page 1088: ...pt controller IRQ interrupt input P3nDR Reset WODR3 R C Q D P3nODR 1 2 Serial clock input WDDR3 Write to P3DDR WDR3 Write to P3DR WODR3 Write to P3ODR RDR3 Read P3DR RPOR3 Read port 3 RODR3 Read P3ODR...

Page 1089: ...module Analog input RPOR4 Read port 4 n 0 to 5 Figure C 4 a Port 4 Block Diagram Pins P40 to P45 RPOR4 Read port 4 n 6 or 7 P4n RPOR4 Internal data bus A D converter module Analog input D A converter...

Page 1090: ...Modes 4 and 5 C Q D PAnDDR Reset WODRA RPCRA R C Q D PAnODR 1 2 Mode 7 Modes 4 to 6 Internal data bus WDDRA Write to PADDR WDRA Write to PADR WODRA Write to PAODR WPCRA Write to PAPCR RDRA Read PADR...

Page 1091: ...RPORB Internal address bus PBnDR Reset WDDRB R C Q D PBnDDR RPCRB Mode 7 Modes 4 to 6 Internal data bus Modes 4 and 5 Modes 6 and 7 WDDRB Write to PBDDR WDRB Write to PBDR WPCRB Write to PBPCR RDRB Re...

Page 1092: ...RPORC Internal address bus PCnDR Reset WDDRC R C Q D PCnDDR RPCRC Mode 7 Modes 4 to 6 Internal data bus Modes 4 and 5 Modes 6 and 7 WDDRC Write to PCDDR WDRC Write to PCDR WPCRC Write to PCPCR RDRC Re...

Page 1093: ...e 7 Modes 4 to 6 External address write Modes 4 to 6 Mode 7 Reset R External address upper read External address lower read Internal upper data bus Internal lower data bus WDDRD Write to PDDDR WDRD Wr...

Page 1094: ...odes 4 to 6 Reset R External address lower read Internal upper data bus Internal lower data bus External address write 8 bit bus mode Mode 7 Bus controller Modes 4 to 6 WDDRE Write to PEDDR WDRE Write...

Page 1095: ...Bus controller BRLE bit Chip select Interrupt controller IRQ interrupt input Port CS25E bit PF0CS4S bit Modes 4 to 6 Internal data bus WDDRF Write to PFDDR WDRF Write to PFDR RDRF Read PFDR RPORF Read...

Page 1096: ...S Port F1 chip select 5 select BRLE Bus release enable R PF1DDR C Q D Reset WDDRF Modes 4 to 6 Reset WDRF R PF1DR C Q D PF1 RDRF RPORF Bus controller BRLE bit Chip select Internal data bus Bus request...

Page 1097: ...RF RPORF Bus request output enable Wait enable Wait input IRQ Interupt input Bus controller Interrupt controller Modes 4 to 6 Modes 4 to 6 Internal data bus WDDRF Write to PFDDR WDRF Write to PFDR RDR...

Page 1098: ...PF3 RDRF RPORF Bus controller LWR output Interrupt controller IRQ interrupt input LWROD bit Mode 7 Modes 4 to 6 Internal data bus Modes 4 to 6 WDDRF Write to PFDDR WDRF Write to PFDR RDRF Read PFDR R...

Page 1099: ...D Reset WDDRF Reset WDRF R PF4DR C Q D PF4 RDRF RPORF Bus controller HWR output Modes 4 to 6 Modes 4 to 6 Mode 7 Internal data bus WDDRF Write to PFDDR WDRF Write to PFDR RDRF Read PFDR RPORF Read por...

Page 1100: ...D Reset WDDRF Reset WDRF R PF5DR C Q D PF5 RDRF RPORF Bus controller RD output Modes 4 to 6 Modes 4 to 6 Mode 7 Internal data bus WDDRF Write to PFDDR WDRF Write to PFDR RDRF Read PFDR RPORF Read port...

Page 1101: ...des 4 to 6 Modes 4 to 6 Mode 7 Reset WDRF R PF6DR C Q D PF6 RDRF RPORF Bus controller AS output Internal data bus ASOD bit WDDRF Write to PFDDR WDRF Write to PFDR RDRF Read PFDR RPORF Read port F ASOD...

Page 1102: ...088 D WDDRF Reset Reset WDRF R PF7DR C Q D PF7 RDRF RPORF R S C Q D PF7DDR Internal data bus Modes 4 to 6 Mode 7 WDDRF Write to PFDDR WDRF Write to PFDR RDRF Read PFDR RPORF Read port F Figure C 10 h...

Page 1103: ...RG Reset WDRG R PG0DR C Q D PG0 RDRG RPORG A D convereter A D converter external trigger input Interrput controller IRQ interrupt input Internal data bus WDDRG Write to PGDDR WDRG Write to PGDR RDRG R...

Page 1104: ...RPORG Bus controller Chip select 3 Chip select 6 Port CS167E bit CS25E bit CSS36 bit Mode 7 Internal data bus Modes 4 to 6 WDDRG Write to PGDDR WDRG Write to PGDR RDRG Read PGDR RPORG Read port G CS25...

Page 1105: ...G Reset WDRG R PG2DR C Q D PG2 RDRG RPORG Bus controller Port Chip select 2 Mode 7 Internal data bus CS25E bit Modes 4 to 6 WDDRG Write to PGDDR WDRG Write to PGDR RDRG Read PGDR RPORG Read port G CS2...

Page 1106: ...ad PGDR RPORG Read port G CS167E CS167 enable CSS17 CS17 select R PG3DDR C Q D Reset WDDRG Reset WDRG R PG3DR C Q D PG3 RDRG RPORG Bus controller Chip select 1 Chip select 7 Port CS167E bit CSS17 bit...

Page 1107: ...R PG4DR C Q D PG4 RDRG RPORG Bus controller Chip select 0 Mode 7 Modes 4 to 6 Modes 4 and 5 Modes 6 and 7 D S R C Q PG4DDR Internal data bus WDDRG Write to PGDDR WDRG Write to PGDR RDRG Read PGDR RPO...

Page 1108: ...TIOCA1 4 to 7 T T kept kept I O port P13 TIOGD0 TCLKB A23 P12 TIOCC0 T CLKA A22 P11 TIOCB0 A21 P10 TIOCA0 A20 4 to 6 T T AnE 0 kept AnE DDR 1 kept AnE DDR OPE 1 T AnE DDR OPE 1 kept AnE 0 kept AnE DDR...

Page 1109: ...t DDR 1 Address output 7 T T kept kept I O port Port B 4 5 L T OPE 0 T OPE 1 kept T Address output 6 T T DDR OPE 0 T DDR OPE 1 kept T DDR 0 Input port DDR 1 Address output 7 T T kept kept I O port Por...

Page 1110: ...put PF6 AS 4 to 6 H T ASOD 1 kept ASOD OPE 1 T ASOD OPE 1 H ASOD 1 kept ASOD 0 T ASOD 1 I O port ASOD 0 AS 7 T T kept kept I O port PF5 RD PF4 HWR 4 to 6 H T OPE 0 T OPE 1 H T RD HWR 7 T T kept kept I...

Page 1111: ...kept BRLE DDR CS25E PF1CS5S 1 And OPE 0 T BRLE DDR CS25E PF1CS5S 1 And OPE 1 H BRLE 1 BACK L BRLE CS25E PF1CS5S 0 I O port BRLE DDR CS25E PF1CS5S 1 CS5 BRLE 1 BACK 7 T T kept kept I O port PF0 BREQ IR...

Page 1112: ...CS0 7 T T kept kept I O port PG3 CS1 CS7 4 to 6 T T CS167E 0 kept CS167E DDR 1 T CS167E DDR OPE 1 T CS167E DDR OPE 1 H CS167E 0 kept CS167E 1 T CS167E 0 I O port CS167E DDR 1 Input port CS167E CSS17...

Page 1113: ...CSS36 CS25E DDR 1 Input port CSS36 CS167E DDR 1 Input port CSS36 CS25E DDR 1 CS3 CSS36 CS167E DDR 1 CS6 7 T T kept kept I O port PG0 ADTRG IRQ6 4 to 7 T T kept kept I O port Legend H High level L Low...

Page 1114: ...317 Mask ROM version HD6432317 3 HD6432317TE 100 pin TQFP TFP 100B HD6432317F 100 pin QFP FP 100A HD6432317S 4 HD64F2317STE 100 pin TQFP TFP 100B HD6432317STF 100 pin TQFP TFP 100G HD64F2317SF 100 pin...

Page 1115: ...e E10 A emulator E10 A compatible version However some function modules and pin functions are unavailable when the on chip debug function is in use Refer to Figure 1 4 and Figure 1 5 Pin Arrangement 3...

Page 1116: ...lue TFP 100B Conforms 0 5 g Dimension including the plating thickness Base material dimension 16 0 0 2 14 0 08 0 10 0 5 0 1 16 0 0 2 0 5 0 10 0 10 1 20 Max 0 17 0 05 0 8 75 51 1 25 76 100 26 50 M 0 22...

Page 1117: ...nforms 0 4 g Dimension including the plating thickness Base material dimension 14 0 0 2 12 0 07 0 10 0 5 0 1 14 0 0 2 0 4 1 20 Max 0 17 0 05 0 8 75 51 1 25 76 100 26 50 M 0 18 0 05 1 0 1 2 0 16 0 04 0...

Page 1118: ...Dimension including the plating thickness Base material dimension 0 13 M 0 10 0 32 0 08 0 17 0 05 3 10 Max 1 2 0 2 24 8 0 4 20 80 51 50 31 30 1 100 81 18 8 0 4 14 0 15 0 65 2 70 2 4 0 20 0 10 0 20 0...

Page 1119: ...ion March 1999 Rev 5 00 December 15 2003 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Renesas Kodaira Semiconductor Co Ltd...

Page 1120: ...cher Str 3 D 85622 Feldkirchen Germany Tel 49 89 380 70 0 Fax 49 89 929 30 11 Renesas Technology Hong Kong Ltd 7 F North Tower World Finance Centre Harbour City Canton Road Hong Kong Tel 852 2265 6688...

Page 1121: ...H8S 2319 Group H8S 2318 Group Hardware Manual REJ09B0089 0500O...

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