Renesas H8S/2318 series, Hardware Manual

Page: 187 / 1121

Rev. 5.00, 12/03, page 157 of 1088
6.4 Basic Bus Interface
6.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table
6-3).
6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D
15
to D
8
) or lower data bus (D
7
to D
0
) is used according to the bus specifications
for the area being accessed (8-bit access space or 16-bit access space) and the data size.
8-Bit Access Space: Figure 6-4 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D
15
to D
8
) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word transfer instruction is performed as two
byte accesses, and a longword transfer instruction, as four byte accesses.
D
15
D
8
D
7
D
0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword size
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6-4 Access Sizes and Data Alignment Control (8-Bit Access Space)