Renesas H8S/2318 series, Hardware Manual

Page: 852 / 1121

Rev. 5.00, 12/03, page 822 of 1088
(4) Timing of On-Chip Supporting Modules
Table 20-16 Timing of On-Chip Supporting Modules
Condition C: V
CC
= 2.4 V to 3.6 V, AV
CC
= 2.4 V to 3.6 V, V
ref
= 2.4 V to AV
CC
, V
SS
= AV
SS
=
0 V,
φ
= 2 MHz to 14 MHz, T
a
= –20°C to 75°C (regular specifications)
Condition C
Item Symbol Min Max Unit Test Conditions
I/O ports Output data delay time t
PWD
— 70 ns Figure 20-13
Input data setup time t
PRS
40 — ns
Input data hold time t
PRH
40 — ns
TPU Timer output delay time t
TOCD
— 70 ns Figure 20-14
Timer input setup time t
TICS
40 — ns
Timer clock input setup time t
TCKS
40 — ns Figure 20-15
Timer clock
pulse width Single-edge
specification t
TCKWH
1.5 — t
cyc
Both-edge
specification t
TCKWL
2.5 — t
cyc
8-bit timer Timer output delay time t
TMOD
— 70 ns Figure 20-16
Timer reset input setup time t
TMRS
40 — ns Figure 20-18
Timer clock input setup time t
TMCS
40 — ns Figure 20-17
Timer clock
pulse width Single-edge
specification t
TMCWH
1.5 — t
cyc
Both-edge
specification t
TMCWL
2.5 — t
cyc
WDT Overflow output delay time t
WOVD
— 70 ns Figure 20-19
SCI Asynchronous t
Scyc
4 — t
cyc
Figure 20-20 Input clock
cycle
Synchronous 6 — t
cyc
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5 t
cyc
Transmit data delay time t
TXD
— 70 ns Figure 20-21
Receive data setup time
(synchronous) t
RXS
70 — ns
Receive data hold time
(synchronous) t
RXH
70 — ns
A/D
converter Trigger input setup time t
TRGS
30 — ns Figure 20-22