Renesas H8S/2318 series, Hardware Manual

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Rev. 5.00, 12/03, page 373 of 1088
9.7 Usage Notes
Note that the kinds of operation and contention described below can occur during TPU operation.
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not
operate properly with a narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9-48 shows the input clock
conditions in phase counting mode.
Overlap
Phase
differ-
ence
Phase
differ-
ence Overlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width Pulse width
Pulse width Pulse width
Notes: Phase difference and overlap
Pulse
width
: 1.5 states or more
: 2.5 states or more
Figure 9-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in
the final state in which it matches the TGR value (the point at which the count value matched by
TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
f =
φ
(N + 1)
Where f : Counter frequency
φ
: Operating frequency
N : TGR set value