Renesas H8S/2318 series, Hardware Manual

Page: 136 / 1121

Rev. 5.00, 12/03, page 106 of 1088
4.5 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4-4 shows the status of CCR and EXR after execution of trap instruction exception
handling.
Table 4-4 Status of CCR and EXR after Trap Instruction Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 1 — — —
2 1 — — 0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
4.6 Stack Status after Exception Handling
Figure 4-4 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP
SP CCR
PC
(24 bits)
CCR
PC
(24 bits)
Reserved
*
EXR
(a) Interrupt control mode 0 (b) Interrupt control mode 2
Note:
*
Ignored on return.
Figure 4-4 Stack Status after Exception Handling (Advanced Modes)