Renesas H8S/2318 series, Hardware Manual

Page: 543 / 1121

Rev. 5.00, 12/03, page 513 of 1088
13.4 Usage Notes
The following points should be noted when using the SCI as a smart card interface.
Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart
card interface mode, the SCI operates on a base clock with a frequency of 32, 64, 372, or 256
times the transfer rate (determined by bits BCP1 and BCP0).
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd,
186th, or 128th pulse of the base clock. Use of a 372-times clock is illustrated in figure 13-10.
Internal
base
clock
372 clocks
186 clocks
Receive
data (RxD)
Synchro-
nization
sampling
timing
D0 D1
Data
sampling
timing
185 371 0
371 185
0
0
Start bit
Figure 13-10 Receive Data Sampling Timing in Smart Card Mode
(When Using 372-Times Clock)