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STMicroelectronics RM0365, Reference Manual

The STMicroelectronics RM0365 Reference Manual is the comprehensive guide for successfully operating and maximizing the potential of your device. This invaluable resource is available for free download at manualshive.com, ensuring easy access to detailed instructions and information necessary for efficient product utilization.

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DocID025202 Rev 7

542/1080

RM0365

Advanced-control timers (TIM1)

549

20.4.19 TIM1 

DMA 

control register (TIMx_DCR)

Address offset: 0x48

Reset value: 0x0000

         

         

Bit 10

OSSI

:

 

Off-state selection for Idle mode

This bit is used when MOE=0 due to a break event or by a software write, on channels 
configured as outputs.
See OC/OCN enable description for more details (

Section 20.4.9: TIM1 capture/compare 

enable register (TIMx_CCER)

).

0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which 
is taken over by the GPIO logic and which imposes a Hi-Z state). 
1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their 
idle level after the deadtime. The timer maintains its control over the output.

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK 

bits in TIMx_BDTR register).

Bits 9:8

LOCK[1:0]

: Lock configuration

These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER 
register, as long as the related channel is configured in output through the CCxS bits) as well 
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in 
TIMx_CCMRx registers, as long as the related channel is configured in output through the 
CCxS bits) can no longer be written.

Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register 

has been written, their content is frozen until the next reset.

Bits 7:0

DTG[7:0]

: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary 
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t

dtg

 with t

dtg

=t

DTS

.

DTG[7:5]=10x => DT=(64+DTG[5:0])xt

dtg

 with T

dtg

=2xt

DTS

.

DTG[7:5]=110 => DT=(32+DTG[4:0])xt

dtg

 with T

dtg

=8xt

DTS

.

DTG[7:5]=111 => DT=(32+DTG[4:0])xt

dtg

 with T

dtg

=16xt

DTS

.

Example if T

DTS

=125ns (8MHz), dead-time possible values are:

0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps

Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed 

(LOCK bits in TIMx_BDTR register).

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Res.

Res.

Res.

DBL[4:0]

Res.

Res.

Res.

DBA[4:0]

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bits 15:13 Reserved, must be kept at reset value.

Summary of Contents for RM0365

Page 1: ...hroughout the document unless otherwise specified The STM32F302xx is a family of microcontrollers with different memory sizes packages and peripherals For ordering information mechanical and electrical device characteristics please refer to the STM32F302xB C STM32F302xD E and STM32F302x6 8 datasheets For information on the ARM Cortex M4 core with FPU refer to the STM32F3xx STM32F4xx programming ma...

Page 2: ...x 46 3 2 Memory organization 47 3 2 1 Introduction 47 3 2 2 Memory map and register boundary addresses 47 3 3 Embedded SRAM 55 3 3 1 Parity check 55 3 4 Flash memory overview 55 3 5 Boot configuration 56 3 5 1 Embedded boot loader 56 4 Embedded Flash memory 57 4 1 Flash main features 57 4 2 Flash memory functional description 57 4 2 1 Flash memory organization 57 4 2 2 Read operations 59 4 2 3 Fla...

Page 3: ...er map 76 5 Option byte description 78 6 Cyclic redundancy check calculation unit CRC 81 6 1 Introduction 81 6 2 CRC main features 81 6 3 CRC functional description 82 6 3 1 CRC block diagram 82 6 3 2 CRC internal signals 82 6 3 3 CRC operation 82 6 4 CRC registers 84 6 4 1 Data register CRC_DR 84 6 4 2 Independent data register CRC_IDR 84 6 4 3 Control register CRC_CR 85 6 4 4 Initial CRC value C...

Page 4: ...TI to DAC 96 7 3 19 From TIM to IRTIM 96 8 Power control PWR 97 8 1 Power supplies 97 8 1 1 Independent A D and D A converter supply and reference voltage 98 8 1 2 Battery backup domain 98 8 1 3 Voltage regulator 99 8 2 Power supply supervisor 100 8 2 1 Power on reset POR power down reset PDR 100 8 2 2 Programmable voltage detector PVD 101 8 3 Low power modes 102 8 3 1 Slowing down system clocks 1...

Page 5: ...M16 125 9 3 Low power modes 126 9 4 RCC registers 127 9 4 1 Clock control register RCC_CR 127 9 4 2 Clock configuration register RCC_CFGR 128 9 4 3 Clock interrupt register RCC_CIR 132 9 4 4 APB2 peripheral reset register RCC_APB2RSTR 134 9 4 5 APB1 peripheral reset register RCC_APB1RSTR 136 9 4 6 AHB peripheral clock enable register RCC_AHBENR 138 9 4 7 APB2 peripheral clock enable register RCC_A...

Page 6: ... LSE oscillator pins as GPIOs 163 10 3 14 Using the GPIO pins in the RTC supply domain 163 10 4 GPIO registers 164 10 4 1 GPIO port mode register GPIOx_MODER x A H 164 10 4 2 GPIO port output type register GPIOx_OTYPER x A H 164 10 4 3 GPIO port output speed register GPIOx_OSPEEDR x A H 165 10 4 4 GPIO port pull up pull down register GPIOx_PUPDR x A H 165 10 4 5 GPIO port input data register GPIOx...

Page 7: ... DMA implementation 183 12 4 DMA functional description 184 12 4 1 DMA transactions 184 12 4 2 Arbiter 185 12 4 3 DMA channels 185 12 4 4 Programmable data width data alignment and endians 187 12 4 5 Error management 188 12 4 6 DMA interrupts 188 12 4 7 DMA request mapping 188 12 5 DMA registers 196 12 5 1 DMA interrupt status register DMA_ISR 196 12 5 2 DMA interrupt flag clear register DMA_IFCR ...

Page 8: ...219 13 3 4 Falling trigger selection register EXTI_FTSR1 219 13 3 5 Software interrupt event register EXTI_SWIER1 220 13 3 6 Pending register EXTI_PR1 220 13 3 7 Interrupt mask register EXTI_IMR2 221 13 3 8 Event mask register EXTI_EMR2 221 13 3 9 Rising trigger selection register EXTI_RTSR2 222 13 3 10 Falling trigger selection register EXTI_FTSR2 222 13 3 11 Software interrupt event register EXT...

Page 9: ...276 14 6 8 NAND Flash PC Card controller registers 278 14 7 FMC register map 285 15 Analog to digital converters ADC 287 15 1 Introduction 287 15 2 ADC main features 288 15 3 ADC functional description 290 15 3 1 ADC block diagram 290 15 3 2 Pins and internal signals 291 15 3 3 Clocks 292 15 3 4 ADC1 2 connectivity 294 15 3 5 Slave AHB interface 295 15 3 6 ADC voltage regulator ADVREGEN 295 15 3 7...

Page 10: ...2 15 3 32 Monitoring the internal voltage reference 353 15 4 ADC interrupts 355 15 5 ADC registers for each ADC 356 15 5 1 ADC interrupt and status register ADCx_ISR x 1 2 356 15 5 2 ADC interrupt enable register ADCx_IER x 1 2 358 15 5 3 ADC control register ADCx_CR x 1 2 360 15 5 4 ADC configuration register ADCx_CFGR x 1 2 363 15 5 5 ADC sample time register 1 ADCx_SMPR1 x 1 2 367 15 5 6 ADC sa...

Page 11: ... 393 16 2 DAC1 main features 393 16 3 DAC output buffer enable 394 16 4 DAC channel enable 395 16 5 Single mode functional description 395 16 5 1 DAC data format 395 16 5 2 DAC channel conversion 395 16 5 3 DAC output voltage 396 16 5 4 DAC trigger selection 397 16 6 Noise generation 398 16 7 Triangle wave generation 399 16 8 DMA request 400 16 9 DAC registers 401 16 9 1 DAC control register DAC_C...

Page 12: ...ntrol and status register COMP2_CSR 415 17 5 3 COMP4 control and status register COMP4_CSR 418 17 5 4 COMP6 control and status register COMP6_CSR 420 17 5 5 COMP register map 422 18 Operational amplifier OPAMP 423 18 1 OPAMP introduction 423 18 2 OPAMP main features 423 18 3 OPAMP functional description 423 18 3 1 General description 423 18 3 2 Clock 424 18 3 3 Operational amplifiers and comparato...

Page 13: ...C_CR 446 19 6 2 TSC interrupt enable register TSC_IER 448 19 6 3 TSC interrupt clear register TSC_ICR 449 19 6 4 TSC interrupt status register TSC_ISR 450 19 6 5 TSC I O hysteresis control register TSC_IOHCR 450 19 6 6 TSC I O analog switch control register TSC_IOASCR 451 19 6 7 TSC I O sampling control register TSC_IOSCR 451 19 6 8 TSC I O channel control register TSC_IOCCR 452 19 6 9 TSC I O gro...

Page 14: ...3 23 Timer input XOR function 506 20 3 24 Interfacing with Hall sensors 506 20 3 25 Timer synchronization 509 20 3 26 ADC synchronization 513 20 3 27 DMA burst mode 513 20 3 28 Debug mode 514 20 4 TIM1 registers 515 20 4 1 TIM1 control register 1 TIMx_CR1 515 20 4 2 TIM1 control register 2 TIMx_CR2 516 20 4 3 TIM1 slave mode control register TIMx_SMCR 519 20 4 4 TIM1 DMA interrupt enable register ...

Page 15: ...gister map 547 21 General purpose timers TIM2 TIM3 TIM4 550 21 1 TIM2 TIM3 TIM4 introduction 550 21 2 TIM2 TIM3 TIM4 main features 550 21 3 TIM2 TIM3 TIM4 functional description 552 21 3 1 Time base unit 552 21 3 2 Counter modes 554 21 3 3 Clock selection 564 21 3 4 Capture compare channels 568 21 3 5 Input capture mode 570 21 3 6 PWM input mode 571 21 3 7 Forced output mode 572 21 3 8 Output comp...

Page 16: ...ister TIMx_ARR 613 21 4 13 TIMx capture compare register 1 TIMx_CCR1 614 21 4 14 TIMx capture compare register 2 TIMx_CCR2 614 21 4 15 TIMx capture compare register 3 TIMx_CCR3 615 21 4 16 TIMx capture compare register 4 TIMx_CCR4 615 21 4 17 TIMx DMA control register TIMx_DCR 616 21 4 18 TIMx DMA address for full transfer TIMx_DMAR 616 21 4 19 TIMx register map 617 22 General purpose timers TIM15...

Page 17: ...egister TIM15_EGR 661 22 5 7 TIM15 capture compare mode register 1 TIM15_CCMR1 662 22 5 8 TIM15 capture compare enable register TIM15_CCER 665 22 5 9 TIM15 counter TIM15_CNT 668 22 5 10 TIM15 prescaler TIM15_PSC 668 22 5 11 TIM15 auto reload register TIM15_ARR 668 22 5 12 TIM15 repetition counter register TIM15_RCR 669 22 5 13 TIM15 capture compare register 1 TIM15_CCR1 669 22 5 14 TIM15 capture c...

Page 18: ... 6 17 TIM16 TIM17 register map 691 23 Basic timers TIM6 693 23 1 TIM6 introduction 693 23 2 TIM6 main features 693 23 3 TIM6 functional description 694 23 3 1 Time base unit 694 23 3 2 Counting mode 696 23 3 3 UIF bit remapping 699 23 3 4 Clock source 699 23 3 5 Debug mode 700 23 4 TIM6 registers 700 23 4 1 TIM6 control register 1 TIMx_CR1 700 23 4 2 TIM6 control register 2 TIMx_CR2 702 23 4 3 TIM...

Page 19: ...oduction 713 26 2 IWDG main features 713 26 3 IWDG functional description 713 26 3 1 IWDG block diagram 713 26 3 2 Window option 714 26 3 3 Hardware watchdog 715 26 3 4 Behavior in Stop and Standby modes 715 26 3 5 Register access protection 715 26 3 6 Debug mode 715 26 4 IWDG registers 716 26 4 1 Key register IWDG_KR 716 26 4 2 Prescaler register IWDG_PR 717 26 4 3 Reload register IWDG_RLR 718 26...

Page 20: ...er RTC_DR 740 27 6 3 RTC control register RTC_CR 742 27 6 4 RTC initialization and status register RTC_ISR 745 27 6 5 RTC prescaler register RTC_PRER 748 27 6 6 RTC wakeup timer register RTC_WUTR 749 27 6 7 RTC alarm A register RTC_ALRMAR 750 27 6 8 RTC alarm B register RTC_ALRMBR 751 27 6 9 RTC write protection register RTC_WPR 752 27 6 10 RTC sub second register RTC_SSR 752 27 6 11 RTC shift con...

Page 21: ...us specific features 799 28 4 11 SMBus initialization 802 28 4 12 SMBus I2C_TIMEOUTR register configuration examples 804 28 4 13 SMBus slave mode 805 28 4 14 Wakeup from Stop mode on address match 813 28 4 15 Error conditions 813 28 4 16 DMA requests 815 28 4 17 Debug mode 816 28 5 I2C low power modes 816 28 6 I2C interrupts 816 28 7 I2C registers 818 28 7 1 Control register 1 I2C_CR1 818 28 7 2 C...

Page 22: ...9 5 7 Multiprocessor communication using USART 855 29 5 8 Modbus communication using USART 857 29 5 9 USART parity control 858 29 5 10 USART LIN local interconnection network mode 859 29 5 11 USART synchronous mode 861 29 5 12 USART Single wire Half duplex communication 864 29 5 13 USART Smartcard mode 864 29 5 14 USART IrDA SIR ENDEC block 869 29 5 15 USART continuous communication in DMA mode 87...

Page 23: ...30 5 1 General description 904 30 5 2 Communications between one master and one slave 905 30 5 3 Standard multi slave communication 907 30 5 4 Multi master communication 908 30 5 5 Slave select NSS pin management 909 30 5 6 Communication formats 910 30 5 7 Configuration of SPI 912 30 5 8 Procedure for enabling SPI 913 30 5 9 Data transmission and reception procedures 913 30 5 10 SPI status flags 9...

Page 24: ... S configuration register SPIx_I2SCFGR 956 30 9 9 SPIx_I2S prescaler register SPIx_I2SPR 958 30 9 10 SPI I2S register map 959 31 Controller area network bxCAN 960 31 1 Introduction 960 31 2 bxCAN main features 960 31 3 bxCAN general description 961 31 3 1 CAN 2 0B active core 961 31 3 2 Control status and configuration registers 961 31 3 3 Tx mailboxes 961 31 3 4 Acceptance filters 962 31 4 bxCAN ...

Page 25: ...terface USB 1004 32 1 Introduction 1004 32 2 USB main features 1004 32 3 USB implementation 1004 32 4 USB functional description 1005 32 4 1 Description of USB blocks 1006 32 5 Programming considerations 1007 32 5 1 Generic USB device programming 1008 32 5 2 System and power on reset 1008 32 5 3 Double buffered endpoints 1013 32 5 4 Isochronous transfers 1015 32 5 5 Suspend Resume events 1017 32 6...

Page 26: ...set idle states ID code 1048 33 8 4 DP and AP read write accesses 1048 33 8 5 SW DP registers 1049 33 8 6 SW AP registers 1050 33 9 AHB AP AHB access port valid for both JTAG DP and SW DP 1050 33 10 Core debug 1051 33 11 Capability of the debugger host to connect under system reset 1051 33 12 FPB Flash patch breakpoint 1052 33 13 DWT data watchpoint trigger 1053 33 14 MCU debug component DBGMCU 10...

Page 27: ...hronous mode 1062 33 15 8 TRACECLKIN connection inside the STM32F302xx 1063 33 15 9 TPIU registers 1064 33 15 10 Example of configuration 1065 33 16 DBG register map 1066 34 Device electronic signature 1067 34 1 Unique device ID register 96 bits 1067 34 2 Memory size data register 1068 34 2 1 Flash size data register 1068 35 Revision history 1072 ...

Page 28: ...Timer and EXTI signals triggering DAC1 conversions 96 Table 23 Low power mode summary 102 Table 24 Sleep now 104 Table 25 Sleep on exit 104 Table 26 Stop mode 106 Table 27 Standby mode 107 Table 28 PWR register map and reset values 112 Table 29 RCC register map and reset values 153 Table 30 Port bit configuration table 157 Table 31 GPIO register map and reset values 170 Table 32 SYSCFG register ma...

Page 29: ... bit NAND Flash 271 Table 76 16 bit PC Card 271 Table 77 Supported memories and transactions 272 Table 78 16 bit PC Card signals and access type 277 Table 79 ECC result relevant bits 284 Table 80 FMC register map 285 Table 81 ADC external channels mapping 288 Table 82 ADC internal channels summary 289 Table 83 ADC internal signals 291 Table 84 ADC pins 291 Table 85 Configuring the trigger polarity...

Page 30: ...alues 617 Table 122 TIMx Internal trigger connection 658 Table 123 Output control bits for complementary OCx and OCxN channels with break feature TIM15 667 Table 124 TIM15 register map and reset values 673 Table 125 Output control bits for complementary OCx and OCxN channels with break feature TIM16 17 684 Table 126 TIM16 TIM17 register map and reset values 691 Table 127 TIM6 register map and rese...

Page 31: ... Table 168 Receive mailbox mapping 974 Table 169 bxCAN register map and reset values 1000 Table 170 STM32F302xx USB implementation 1004 Table 171 Double buffering buffer flag definition 1014 Table 172 Bulk double buffering memory buffers usage 1014 Table 173 Isochronous memory buffers usage 1016 Table 174 Resume event detection 1018 Table 175 Reception status encoding 1029 Table 176 Endpoint type ...

Page 32: ...2xB C D E and STM32F302x6 8 DMA1 request mapping 190 Figure 25 STM32F302x6 8 DMA1 request mapping 191 Figure 26 STM32F302xB C DMA2 request mapping 194 Figure 27 External interrupt event block diagram 213 Figure 28 External interrupt event GPIO mapping 215 Figure 29 FMC block diagram 228 Figure 30 FMC memory banks 231 Figure 31 Mode1 read access waveforms 238 Figure 32 Mode1 write access waveforms ...

Page 33: ...f context by setting JADSTP 1 JQM 1 317 Figure 73 Flushing JSQR queue of context by setting ADDIS 1 JQM 0 318 Figure 74 Flushing JSQR queue of context by setting ADDIS 1 JQM 1 318 Figure 75 Example of JSQR queue of context when changing SW and HW triggers 319 Figure 76 Single conversions of a sequence software trigger 321 Figure 77 Continuous conversion of a sequence software trigger 321 Figure 78...

Page 34: ...ons 424 Figure 121 STM32F302x6 8 comparator and operational amplifier connections 425 Figure 122 Timer controlled Multiplexer mode 427 Figure 123 Standalone mode external gain setting mode 428 Figure 124 Follower configuration 429 Figure 125 PGA mode internal gain setting x2 x4 x8 x16 inverting input not used 430 Figure 126 PGA mode internal gain setting x2 x4 x8 x16 inverting input used for filte...

Page 35: ... Complementary output with dead time insertion 492 Figure 172 Dead time waveforms with delay greater than the negative pulse 492 Figure 173 Dead time waveforms with delay greater than the positive pulse 493 Figure 174 Various output behavior in response to a break event on BKIN OSSI 1 496 Figure 175 PWM output state following BKIN and BKIN2 pins assertion OSSI 1 497 Figure 176 PWM output state fol...

Page 36: ...nter aligned PWM waveforms ARR 8 576 Figure 221 Generation of 2 phase shifted PWM signals with 50 duty cycle 577 Figure 222 Combined PWM mode on channels 1 and 3 579 Figure 223 Clearing TIMx OCxREF 580 Figure 224 Example of one pulse mode 581 Figure 225 Retriggerable one pulse mode 583 Figure 226 Example of counter operation in encoder interface mode 584 Figure 227 Example of encoder interface mod...

Page 37: ...hange from 1 to 2 695 Figure 271 Counter timing diagram with prescaler division change from 1 to 4 695 Figure 272 Counter timing diagram internal clock divided by 1 696 Figure 273 Counter timing diagram internal clock divided by 2 697 Figure 274 Counter timing diagram internal clock divided by 4 697 Figure 275 Counter timing diagram internal clock divided by N 698 Figure 276 Counter timing diagram...

Page 38: ...hen oversampling by 16 or 8 845 Figure 320 Data sampling when oversampling by 16 849 Figure 321 Data sampling when oversampling by 8 849 Figure 322 Mute mode using Idle line detection 856 Figure 323 Mute mode using address mark detection 857 Figure 324 Break detection in LIN mode 11 bit break length LBDL bit is set 860 Figure 325 Break detection in LIN mode vs Framing error detection 861 Figure 32...

Page 39: ...smit 0x3478AE 935 Figure 370 Operations required to receive 0x3478AE 936 Figure 371 LSB justified 16 bit extended to 32 bit packet frame 936 Figure 372 Example of 16 bit data frame extended to 32 bit channel frame 936 Figure 373 PCM standard waveforms 16 bit 937 Figure 374 PCM standard waveforms 16 bit extended to 32 bit packet frame 937 Figure 375 Start sequence in master mode 938 Figure 376 Audi...

Page 40: ...1 2 Opamp2 Section 19 Touch sensing controller TSC Up to 24 Up to 24 Up to 17 Section 20 Advanced control timers TIM1 TIM1 TIM1 TIM1 Section 21 General purpose timers TIM2 TIM3 TIM4 TIM2 3 4 TIM2 3 4 TIM2 Section 22 General purpose timers TIM15 TIM16 TIM17 TIM15 16 17 TIM15 16 17 TIM15 16 17 Section 23 Basic timers TIM6 TIM6 TIM6 TIM6 Section 24 Infrared interface IRTIM Available Available Availab...

Page 41: ...I2 SPI3 SPI1 SPI2 SPI3 SPI4 SPI2 SPI3 with I2S Section 31 Controller area network bxCAN Available Available Available Section 32 Universal serial bus full speed device interface USB Available Available Available Table 1 Available features related to each product continued Peripherals STM32F302xB C STM32F302xD E STM32F302x6 8 ...

Page 42: ...ct configuration bits stored in the Flash memory OBL option byte loader AHB advanced high performance bus 2 3 Peripheral availability For peripheral availability and number across all sales types refer to the particular device datasheet read write rw Software can read and write to this bit read only r Software can only read this bit write only w Software can only write to this bit Reading this bit...

Page 43: ...Code Up to Internal 40 Kbyte SRAM FMC in STM32F302xD E AHB to APBx APB1 or APB2 which connect all the APB peripherals AHB dedicated to GPIO ports ADCs 1 2 The STM32F302x6 8 main system consists of Four masters Cortex M4 core I bus Cortex M4 core D bus Cortex M4 core S bus GP DMA1 general purpose DMA Six slaves Internal Flash memory on the DCode Internal Flash memory on ICode Up to Internal 16 Kbyt...

Page 44: ... 2 STM32F302x6 8 system architecture 06 9 7 65 0 XS WR GHGLFDWHG WR 3 2 SRUWV 5 76 5 DQG WR 3 DQG 3 EXV 6 EXV EXV 0 0 50 257 0 3 0 3 0 6 ELWV 2 2 XV0DWUL 6 0 0 0 0 0 0 0 6 6 6 6 6 7 65 0 XS WR GHGLFDWHG WR 3 2 SRUWV 5 76 5 DQG WR 3 DQG 3 EXV 6 EXV EXV 0 50 257 0 3 0 6 ELWV 2 2 XV0DWUL 6 0 0 0 0 0 0 0 6 6 6 6 06 9 ...

Page 45: ...The targets of this bus are the internal Flash memory and the SRAM 3 1 3 S2 S bus This bus connects the system bus of the Cortex M4 core to the BusMatrix This bus is used to access data located in the peripheral or SRAM area The targets of this bus are the SRAM the AHB to APB1 APB2 bridges the AHB IO port and the 2 ADCs 3 1 4 S3 S4 DMA bus This bus connects the AHB master interface of the DMA to t...

Page 46: ...tions between the AHB and the 2 APB buses APB1 is limited to 36 MHz APB2 operates at full speed 72 MHz Refer to Section 3 2 2 Memory map and register boundary addresses on page 47 for the address mapping of the peripherals connected to this bridge After each device reset all peripheral clocks are disabled except for the SRAM and FLITF Before using a peripheral user has to enable its clock in the R...

Page 47: ...fer to Memory map and register boundary addresses and peripheral sections 3 2 2 Memory map and register boundary addresses See the datasheet corresponding to your device for a comprehensive diagram of the memory map The following table gives the boundary addresses of the peripherals available in the devices Table 2 STM32F302xB C peripheral register boundary addresses 1 Bus Boundary address Size by...

Page 48: ... 4800 0x4001 4BFF 1 K TIM17 Section 22 6 17 on page 691 0x4001 4400 0x4001 47FF 1 K TIM16 0x4001 4000 0x4001 43FF 1 K TIM15 Section 22 5 18 on page 673 0x4001 3C00 0x4001 3FFF 1 K Reserved 0x4001 3800 0x4001 3BFF 1 K USART1 Section 3 7 12 on page 1130 0x4001 3400 0x4001 37FF 1 K Reserved 0x4001 3000 0x4001 33FF 1 K SPI1 Section 30 9 10 on page 959 0x4001 2C00 0x4001 2FFF 1 K TIM1 Section 20 4 25 o...

Page 49: ...4 6 on page 721 0x4000 2C00 0x4000 2FFF 1 K WWDG Section 25 4 4 on page 712 0x4000 2800 0x4000 2BFF 1 K RTC Section 27 6 20 on page 763 0x4000 1400 0x4000 27FF 5 K Reserved 0x4000 1000 0x4000 13FF 1 K TIM6 Section 23 4 9 on page 705 0x4000 0C00 0x4000 0FFF 1 K Reserved 0x4000 0800 0x4000 0BFF 1 K TIM4 Section 21 4 19 on page 617 0x4000 0400 0x4000 07FF 1 K TIM3 0x4000 0000 0x4000 03FF 1 K TIM2 0x2...

Page 50: ...00 0x4800 17FF 1 K GPIOF 0x4800 1000 0x4800 13FF 1 K GPIOE 0x4800 0C00 0x4800 0FFF 1 K GPIOD 0x4800 0800 0x4800 0BFF 1 K GPIOC 0x4800 0400 0x4800 07FF 1 K GPIOB 0x4800 0000 0x4800 03FF 1 K GPIOA 0x4002 4400 0x47FF FFFF 128 M Reserved AHB1 0x4002 4000 0x4002 43FF 1 K TSC Section 19 6 11 on page 454 0x4002 3400 0x4002 3FFF 3 K Reserved 0x4002 3000 0x4002 33FF 1 K CRC Section 6 4 6 on page 86 0x4002 ...

Page 51: ...x4001 3400 0x4001 37FF 1 K Reserved 0x4001 3000 0x4001 33FF 1 K SPI1 Section 30 9 10 on page 959 0x4001 2C00 0x4001 2FFF 1 K TIM1 Section 20 4 25 on page 547 0x4001 0800 0x4001 2BFF 8 K Reserved 0x4001 0400 0x4001 07FF 1 K EXTI Section 13 3 13 on page 225 0x4001 0000 0x4001 03FF 1 K SYSCFG COMP OPAMP Section 11 1 7 on page 182 Section 17 5 5 on page 422 Section 18 4 3 on page 436 0x4000 9C00 0x400...

Page 52: ... 26 4 6 on page 721 0x4000 2C00 0x4000 2FFF 1 K WWDG Section 25 4 4 on page 712 0x4000 2800 0x4000 2BFF 1 K RTC Section 27 6 20 on page 763 0x4000 1400 0x4000 27FF 5 K Reserved 0x4000 1000 0x4000 13FF 1 K TIM6 Section 23 4 9 on page 705 0x4000 0C00 0x4000 0FFF 1 K Reserved 0x4000 0800 0x4000 0BFF 1 K TIM4 Section 21 4 19 on page 617 0x4000 0400 0x4000 07FF 1 K TIM3 0x4000 0000 0x4000 03FF 1 K TIM2...

Page 53: ...0x4002 2FFF 3 K Reserved 0x4002 2000 0x4002 23FF 1 K Flash interface Section 4 6 on page 76 0x4002 1400 0x4002 1FFF 3 K Reserved 0x4002 1000 0x4002 13FF 1 K RCC Section 9 4 14 on page 153 0x4002 0400 0x4002 0FFF 3 K Reserved 0x4002 0000 0x4002 03FF 1 K DMA1 Section 12 5 7 on page 202 0x4001 8000 0x4001 FFFF 32 K Reserved APB2 0x4001 4C00 0x4001 7FFF 13 K Reserved 0x4001 4800 0x4001 4BFF 1 K TIM17 ...

Page 54: ...000 3BFF 1 K SPI2 I2S2 0x4000 3400 0x4000 37FF 1 K I2S2ext 0x4000 3000 0x4000 33FF 1 K IWDG Section 26 4 6 on page 721 0x4000 2C00 0x4000 2FFF 1 K WWDG Section 25 4 4 on page 712 0x4000 2800 0x4000 2BFF 1 K RTC Section 27 6 20 on page 763 0x4000 1400 0x4000 27FF 5 K Reserved 0x4000 1000 0x4000 13FF 1 K TIM6 Section 23 4 9 on page 705 0x4000 0400 0x4000 0FFF 3 K Reserved 0x4000 0000 0x4000 03FF 1 K...

Page 55: ...so be linked to the Break input of TIMER 1 15 16 and 17 by setting the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2 SYSCFG_CFGR2 In case of parity error the SRAM Parity Error flag SRAM_PEF is set in the SYSCFG configuration register 2 SYSCFG_CFGR2 For more details please refer to the SYSCFG configuration register 2 SYSCFG_CFGR2 The BYP_ADD_PAR bit in SYSCFG_CFGR2 register ca...

Page 56: ... memory space 0x0000 0000 but still accessible from its original memory space 0x0800 0000 In other words the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000 Boot from system memory the system memory is aliased in the boot memory space 0x0000 0000 but still accessible from its original memory space 0x1FFF D800 Boot from the embedded SRAM the SRAM is aliased in...

Page 57: ...mation block 1280 64 bits Flash memory interface FLITF features Read interface with prefetch buffer 2 64 bit words Option byte loader Flash program Erase operation Read Write protection low power mode 4 2 Flash memory functional description 4 2 1 Flash memory organization The Flash memory is organized as 64 bit wide memory cells that can be used for storing both code and data constants The memory ...

Page 58: ...ule organization 1 1 The gray color is used for reserved Flash memory addresses Flash area Flash memory addresses Size bytes Name Main memory 0x0800 0000 0x0800 07FF 2 K Page 0 0x0800 0800 0x0800 0FFF 2 K Page 1 0x0800 1000 0x0800 17FF 2 K Page 2 0x0800 1800 0x0800 1FFF 2 K Page 3 0x0803 F800 0x0807 FFFF 2 K Page 255 Information block 0x1FFF D800 0x1FFF F7FF 8 K System memory 0x1FFF F800 0x1FFF F8...

Page 59: ...ks wide where each block consists of 8 bytes The prefetch blocks are direct mapped A block can be completely replaced on a single read to the Flash memory as the size of the block matches the bandwidth of the Flash memory The implementation of this prefetch buffer makes a faster CPU execution possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer...

Page 60: ...it programming or in application programming The in circuit programming ICP method is used to update the entire contents of the Flash memory using the JTAG SWD protocol or the boot loader to load the user application into the microcontroller ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices In contrast to the ICP method in applicat...

Page 61: ...H_KEYR register 1 Write KEY1 0x45670123 2 Write KEY2 0xCDEF89AB Any wrong sequence locks up the FPEC and the FLASH_CR register until the next reset In the case of a wrong key sequence a bus error is detected and a Hard Fault interrupt is generated This is done after the first write cycle if KEY1 does not match or during the second write cycle if KEY1 has been correctly written but KEY2 does not ma...

Page 62: ... is correctly programmed to 0x0000 and the PGERR bit is not set If the addressed main Flash memory location is write protected by the FLASH_WRPR register the program operation is skipped and a warning is issued by the WRPRTERR bit in the FLASH_SR register The end of the program operation is indicated by the EOP bit in the FLASH_SR register The main Flash memory programming sequence in standard mod...

Page 63: ...SH_SR register is set Flash memory erase The Flash memory can be erased page by page or completely Mass Erase Page Erase To erase a page the procedure below should be followed 1 Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_CR register 2 Set the PER bit in the FLASH_CR register 3 Program the FLASH_AR register to select a page to erase 4 Set the STRT bit in th...

Page 64: ...et the MER bit in the FLASH_CR register 3 Set the STRT bit in the FLASH_CR register see below note 4 Wait for the BSY bit to be reset 5 Check the EOP flag in the FLASH_SR register it is set when the erase operation has succeeded and then clear it by software 6 Clear the EOP flag Note The software should start checking if the BSY bit equals 0 at least one CPU cycle after setting the STRT bit 5HDG 6...

Page 65: ...ng the FPEC the user has to authorize the programming of the option bytes by writing the same set of KEYS KEY1 and KEY2 to the FLASH_OPTKEYR register refer to Unlocking the Flash memory for key values Then the OPTWRE bit in the FLASH_CR register will be set by hardware and the user has to set the OPTPG bit in the FLASH_CR register and perform a half word write operation at the desired Flash addres...

Page 66: ...OPTPG bit in the FLASH_CR register Write the data half word to the desired address Wait for the BSY bit to be reset Read the programmed value and verify When the Flash memory read protection option is changed from protected to unprotected a Mass Erase of the main Flash memory is performed before reprogramming the read protection option If the user wants to change an option other than the read prot...

Page 67: ...stead of a system reset There are three levels of read protection from no protection level 0 to maximum protection or no debug level 2 The Flash memory is protected when the RDP option byte and its complement contain the pair of values shown in Table 7 The System memory area is read accessible whatever the protection level It is never accessible for program erase operation Level 0 no protection Re...

Page 68: ...sh status register FLASH_SR When the RDP is reprogrammed to the value 0xAA to move back to Level 0 a mass erase of main memory Flash is performed and the backup registers RTC_BKPxR in the RTC are reset Level 2 No debug In this level the protection level 1 is guaranteed In addition the Cortex M4 debug capabilities are disabled Consequently the debug port the boot from RAM boot RAM mode and the boot...

Page 69: ...H bit in the FLASH_CR register If a program or an erase operation is performed on a protected the Flash memory returns a WRPRTERR protection error flag in the Flash memory Status Register FLASH_SR Table 8 Access status versus protection level and execution modes Area Protection level User execution Debug BootFromRam BootFromLoader Read Write Erase Read Write Erase Main Flash memory 1 Yes Yes Yes N...

Page 70: ... boot loader Erase the entire option byte area by using the OPTER bit in the Flash memory control register FLASH_CR Set the OBL_LAUNCH bit in the Flash control register FLASH_CR to reload the option bytes and the new WRP 3 0 bytes and to disable the write protection 4 3 3 Option byte block write protection The option bytes are always read accessible and write protected by default To gain write acc...

Page 71: ... rw rw rw rw Bits 31 6 Reserved must be kept at reset value Bit 5 PRFTBS Prefetch buffer status This bit provides the status of the prefetch buffer 0 Prefetch buffer is disabled 1 Prefetch buffer is enabled Bit 4 PRFTBE Prefetch buffer enable 0 Prefetch is disabled 1 Prefetch is enabled Bit 3 HLFCYA Flash half cycle access enable 0 Half cycle is disabled 1 Half cycle is enabled Bits 2 0 LATENCY 2 ...

Page 72: ...ese bits represent the keys to unlock the OPTWRE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res EOP WRPRT ERR Res PG ERR Res BSY rw rw rw r Bits 31 6 Reserved must be kept at reset value Bit 5 EOP End of operation Set by hardware when a Flash operation prog...

Page 73: ...es ERRIE OPTWR E Res LOCK STRT OPTER OPT PG Res MER PER PG rw rw rw rw rw rw rw rw rw rw rw Bits 31 14 Reserved must be kept at reset value Bit 13 OBL_LAUNCH Force option byte loading When set to 1 this bit forces the option byte reloading This operation generates a system reset 0 Inactive 1 Active Bit 12 EOPIE End of operation interrupt enable This bit enables the interrupt generation when the EO...

Page 74: ...operation when set This bit is set only by software and reset when the BSY bit is reset Bit 5 OPTER Option byte erase Option byte erase chosen Bit 4 OPTPG Option byte programming Option byte programming chosen Bit 3 Reserved must be kept at reset value Bit 2 MER Mass erase Erase of all user pages chosen Bit 1 PER Page erase Page Erase chosen Bit 0 PG Programming Flash programming chosen 31 30 29 2...

Page 75: ...1 0 OPTERR r r r r r r r r r r r r r r r r r r r r r r r r Bits 31 24 Data1 Bits 23 16 Data0 Bits 15 8 OBR User Option Byte Bit 15 Reserved must be kept at reset value Bit 14 SRAM_PE Bit 13 VDDA_MONITOR Bit 12 nBOOT1 Bit 11 Reserved must be kept at reset value Bit 10 nRST_STDBY Bit 9 nRST_STOP Bit 8 WDG_SW Bits 7 3 Reserved must be kept at reset value Bit 2 1 RDPRT 1 0 Read protection Level status...

Page 76: ...s Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PRFTBS PRFTBE HLFCYA LATENCY 2 0 Reset value 1 1 0 0 0 0 0x004 FLASH_ KEYR FKEYR 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x008 FLASH_ OPTKEYR OPTKEYR 31 0 Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x00C FLASH_ SR Res Res Re...

Page 77: ...TOR nBOOT1 Res nRST_STDBY nRST_STOP WDG_SW Res RDPRT 1 0 OPTERR Reset value x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 x x x x 0x020 FLASH_ WRPR WRP 31 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 10 Flash interface register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 ...

Page 78: ... bytes can be read from the memory locations listed in Table 12 or from the Option byte register FLASH_OBR Note The new programmed option bytes user read write protection are loaded after a system reset Table 11 Option byte format 31 24 23 16 15 8 7 0 Complemented option byte1 Option byte 1 Complemented option byte0 Option byte 0 Table 12 Option byte organization Address 31 24 23 16 15 8 7 0 0x1FF...

Page 79: ...VDDA power supply supervisor enabled Bit 20 nBOOT1 Together with the BOOT0 pin this bit selects Boot mode from the main Flash memory SRAM or System memory Refer to Section 3 5 on page 56 Bit 19 Reserved must be kept at reset Bit 18 nRST_STDBY 0 Reset generated when entering Standby mode 1 No reset generated Bit 17 nRST_STOP 0 Reset generated when entering Stop mode 1 No reset generated Bit 16 WDG_...

Page 80: ...e protection active 1 Write protection not active Refer to Section 4 3 2 Write protection for more details Note Even if WRP2 and WRP3 are not available they must be kept at reset value 0x1FFF F80C WRPx Flash memory write protection option bytes available only on STM32F302xB C Bits 31 24 nWRP3 Bits 23 16 WRP3 stored in FLASH_WRPR 31 24 Bits 15 8 nWRP2 Bits 7 0 WRP2 stored in FLASH_WRPR 23 16 One bi...

Page 81: ...ans of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of the software during runtime to be compared with a reference signature generated at link time and stored at a given memory location 6 2 CRC main features Fully programmable polynomial with programmable size 7 8 16 32 bits Handles 8 16 32 bit data size Programmable CRC initial value Single input output ...

Page 82: ...itten The CRC_DR register can be accessed by word right aligned half word and right aligned byte For the other registers only 32 bit access is allowed The duration of the computation depends on data width 4 AHB clock cycles for 32 bit 2 AHB clock cycles for 16 bit 1 AHB clock cycles for 8 bit An input buffer allows to immediately write a second data without waiting for any wait states due to the p...

Page 83: ... initial CRC value can be programmed with the CRC_INIT register The CRC_DR register is automatically initialized upon CRC_INIT register write access The CRC_IDR register can be used to hold a temporary value related to CRC calculation It is not affected by the RESET bit in the CRC_CR register Polynomial programmability The polynomial coefficients are fully programmable through the CRC_POL register...

Page 84: ...to the CRC calculator It holds the previous CRC calculation result when it is read If the data size is less than 32 bits the least significant bits are used to write read the correct value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res IDR 7 0 rw Bits 31 8 Reserved...

Page 85: ...Bit order not affected 1 Bit reversed output format Bits 6 5 REV_IN 1 0 Reverse input data These bits control the reversal of the bit order of the input data 00 Bit order not affected 01 Bit reversal done by byte 10 Bit reversal done by half word 11 Bit reversal done by word Bits 4 3 POLYSIZE 1 0 Polynomial size These bits control the size of the polynomial 00 32 bit polynomial 01 16 bit polynomia...

Page 86: ...e is less than 32 bits the least significant bits have to be used to program the correct value Table 15 CRC register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 CRC_DR DR 31 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x04 CRC_IDR Res Res Res Res Res Res Res Res Res Res Res Res Res...

Page 87: ...atency and minimize GPIOs configuration Optimum number of available pins even with small packages Avoid the use of connectors and design an optimized PCB with less dissipated energy 7 2 Connection summary The following table presents the matrix for the peripheral interconnect Table 16 STM32F302xx peripherals interconnect matrix 1 Source Destination DMA1 DMA2 2 ADC1 ADC2 2 COMP1 2 COMP2 COMP4 COMP6...

Page 88: ...TIM16 x x x TIM17 x x x x TIM2 x x x x x x x x x x x TIM3 2 x x x x x x x x x x x TIM4 2 x x x x x x x TIM6 x x x x x SPI2 I2S x SPI3 I2S x USART2 x Table 16 STM32F302xx peripherals interconnect matrix 1 continued Source Destination DMA1 DMA2 2 ADC1 ADC2 2 COMP1 2 COMP2 COMP4 COMP6 OPAMP1 2 OPAMP2 TIM1 TIM15 TIM16 TIM17 TIM2 TIM3 2 TIM4 2 DAC1 IRTIM ...

Page 89: ... x x x I2C3 4 x TS x VBAT x Vrefint x x x x x x CSS x x PVD x x SRAM Parity error 2 x x CPU Hardfault x x HSE x HSI x Table 16 STM32F302xx peripherals interconnect matrix 1 continued Source Destination DMA1 DMA2 2 ADC1 ADC2 2 COMP1 2 COMP2 COMP4 COMP6 OPAMP1 2 OPAMP2 TIM1 TIM15 TIM16 TIM17 TIM2 TIM3 2 TIM4 2 DAC1 IRTIM ...

Page 90: ...to advanced control timers TIM1 A description of the ADC analog watchdog settings is provided in Section 15 3 28 Analog window watchdog AWD1EN JAWD1EN AWD1SGL AWD1CH AWD2CH AWD3CH AWD_HTx AWD_LTx AWDx The output from ADC is on signals ADC1_AWDx_OUT x 1 3 as there are 3 analog watchdogs per ADC and the input to timer on signal TIMx_ETR external trigger TIMx_ETR is connected to ADC1_AWDx_OUT through...

Page 91: ...an be used for OPAMP calibration For more details please refer to the Section Calibration in the OPAMP chapter Section 15 3 11 Channel selection SQRx JSQRx provides the exact ADC channels to be used 2 OPAMPx output x 1 2 can be connected to ADCy channels y 1 2 through the GPIOs See summary in the table below Refer to Section 18 3 4 Using the OPAMP outputs as ADC inputs 7 3 6 From TS to ADC Interna...

Page 92: ...s OCREF_CLR input Input capture To select which timer input must be connected to the comparator output the bits field COMPxOUTSEL in the COMPx_CSR register are used The following table gives an overview of all possible comparator outputs redirection to the timer inputs Table 19 Comparator outputs to timer inputs COMP output selection TIM1 TIM2 TIM3 1 TIM4 TIM15 TIM16 COMP1 1 TIM1_BRK_ACTH TIM1_BRK...

Page 93: ...x_CSR register More details on the blanking function can be found in Section 17 3 6 Comparator output blanking function 7 3 11 From DAC to COMP The comparators inverting input may be a DAC channel output DAC1_CH1 COMP4 TIM1_BRK TIM1_BRK2 N A TIM3_IC3 TIM3_OCrefClear TIM4_IC2 TIM15_OCrefClear TIM15_IC2 N A COMP6 TIM1_BRK_ACTH TIM1_BRK2 TIM2_IC2 TIM2_OCrefClear N A TIM4_IC4 N A TIM16_OCrefClear TIM1...

Page 94: ...controlled Multiplexer mode 7 3 15 From TIM to TIM Some STM32F3 timers are linked together internally for timer synchronization or chaining When one timer is configured in Master Mode it can reset start stop or clock the counter of another timer configured in Slave Mode A description of the feature with the various synchronization modes is available in Section 20 3 25 Timer synchronization for the...

Page 95: ...break feature are provided in Section 20 3 16 Using the break function for the advanced control timers TIM1 Section 22 4 13 Using the break function for the general purpose timers TIM15 TIM16 TIM17 7 3 17 From HSE HSI LSE LSI MCO RTC to TIM TIM16 can be used for the measurement of internal external clock sources TIM16 channel1 input capture is connected to HSE 32 GPIO RTC clock and MCO to output c...

Page 96: ...f DACs interconnections with timers This is described in Section 16 5 4 DAC trigger selection 7 3 19 From TIM to IRTIM General purpose timer TIM16 TIM17 output channels TIMx_OC1 are used to generate the waveform of infrared signal output The functionality is described in Section 24 Infrared interface IRTIM Table 22 Timer and EXTI signals triggering DAC1 conversions Timer DAC1 1 1 Only in STM32F302...

Page 97: ...m the VBAT voltage when the main VDD supply is powered off Figure 8 Power supply overview The following supply voltages are available VDD and VSS external power supply for I Os and core These supply voltages are provided externally through VDD and VSS pins VDD 2 0 to 3 6 V FRQYHUWHU FRQYHUWHU 7HPS VHQVRU 5HVHW EORFN 3 5 V 23 03 RPSDUDWRUV 9 9 7 966 2 ULQJ 9 6WDQGE FLUFXLWU DNHXS ORJLF 9ROWDJH UHJX...

Page 98: ...00 pin package connections only on STM32F302xB CD E To ensure a better accuracy on low voltage inputs and outputs a separate external reference voltage can be connected on VREF VREF is the highest voltage represented by the full scale value for an analog input ADC or output DAC signal 64 pin 49 pin 48 pin and 32 pin package connections On these packages the VREF and VREF pins are not available The...

Page 99: ...e used as GPIO pins PC13 PC14 and PC15 can be configured by RTC or LSE refer to Section 27 3 RTC functional description on page 724 Note Due to the fact that the switch only sinks a limited amount of current 3 mA the use of GPIOs PC13 to PC15 in output mode is restricted the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I Os must not be used as a current source e g to dri...

Page 100: ...t circuit The POR monitors only the VDD supply voltage During the startup phase VDDA must arrive first and be greater than or equal to VDD The PDR monitors both the VDD and VDDA supply voltages However if the application is designed with VDDA higher than or equal to VDD the VDDA power supply supervisor can be disabled by programming a dedicated VDDA_MONITOR option bit to reduce the power consumpti...

Page 101: ...status register PWR_CSR to indicate if VDD is higher or lower than the PVD threshold This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers The PVD output interrupt can be generated when VDD drops below the PVD threshold and or when VDD rises above the PVD threshold depending on EXTI line16 rising falling edge configuration As an e...

Page 102: ...the APB and AHB peripherals when they are unused 8 3 1 Slowing down system clocks In Run mode the speed of the system clocks SYSCLK HCLK PCLK can be reduced by programming the prescaler registers These prescalers can also be used to slow down peripherals before entering Sleep mode For more details refer to Section 9 4 2 Clock configuration register RCC_CFGR Table 23 Low power mode summary Mode nam...

Page 103: ...riority ISR In the Sleep mode all I O pins keep the same state as in the Run mode Refer to Table 24 and Table 25 for details on how to enter Sleep mode Exiting Sleep mode If the WFI instruction is used to enter Sleep mode any peripheral interrupt acknowledged by the nested vectored interrupt controller NVIC can wake up the device from Sleep mode If the WFE instruction is used to enter Sleep mode t...

Page 104: ...access is finished In Stop mode the following features can be selected by programming individual control bits Independent watchdog IWDG the IWDG is started by writing to its Key register or by hardware option Once started it cannot be stopped except by a Reset See Table 24 Sleep now Sleep now mode Description Mode entry WFI Wait for Interrupt or WFE Wait for Event while SLEEPDEEP 0 and SLEEPONEXIT...

Page 105: ...DAC can also consume power during the Stop mode unless they are disabled before entering it To disable the ADC the ADDIS bit must be set in the ADCx_CR register To disable the DAC the ENx bit in the DAC_CR register must be written to 0 Exiting Stop mode Refer to Table 26 for more details on how to exit Stop mode When exiting Stop mode by issuing an interrupt or a wakeup event the HSI RC oscillator...

Page 106: ...nter Stop mode all EXTI Line pending bits in Pending register EXTI_PR1 all peripherals interrupt pending bits and RTC Alarm flag must be reset Otherwise the Stop mode entry procedure is ignored and program execution continues If the application needs to disable the external oscillator external clock before entering Stop mode the system clock source must be first switched to HSI and then clear the ...

Page 107: ... etc The SBF status flag in the Power control status register PWR_CSR indicates that the MCU was in Standby mode Refer to Table 27 for more details on how to exit Standby mode I O states in Standby mode In Standby mode all I O pins are high impedance except Reset pad still available TAMPER pin if configured for tamper or calibration out WKUP pin if enabled Debug mode By default the debug connectio...

Page 108: ...ntrol register RCC_BDCR Low power 32 768 kHz external crystal oscillator LSE OSC This clock source provides a precise time base with very low power consumption less than 1µA added consumption in typical conditions Low power internal RC Oscillator LSI RC This clock source has the advantage of saving the cost of the 32 768 kHz crystal This internal RC Oscillator is designed to add minimum power cons...

Page 109: ...st parasitic write access This bit must be set to enable write access to these registers 0 Access to RTC and Backup registers disabled 1 Access to RTC and Backup registers enabled Note If the HSE divided by 128 is used as the RTC clock this bit must remain set to 1 Bits 7 5 PLS 2 0 PVD level selection These bits are written by software to select the voltage threshold detected by the Power Voltage ...

Page 110: ...de 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res EWUP3 EWUP2 EWUP1 Res Res Res Res Res PVDO SBF WUF rw rw rw r r r Bits 31 11 Reserved must be kept at reset value Bit 10 EWUP3 Enable WKUP3 pin This bit is set and cleared by software 0 WKUP3 pin is used for general purpose I O...

Page 111: ...ped by Standby mode For this reason this bit is equal to 0 after Standby or reset until the PVDE bit is set 2 Once the PVD is enabled and configured in the PWR_CR register PVDO can be used to generate an interrupt through the External Interrupt controller 3 Once the PVD_LOCK is enabled for CLASS B protection PVDO cannot be disabled anymore Bit 1 SBF Standby flag This bit is set by hardware and cle...

Page 112: ... reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 PWR_CR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DBP PLS 2 0 PVDE CSBF CWUF PDDS LPDS Reset value 0 0 0 0 0 0 0 0 0 0x004 PWR_CSR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res EWUP3 EWUP2 EW...

Page 113: ...vents occurs 1 A low level on the NRST pin external reset 2 Window watchdog event WWDG reset 3 Independent watchdog event IWDG reset 4 A software reset SW reset see Software reset 5 Low power management reset see Low power management reset 6 Option byte loader reset see Option byte loader reset 7 A power reset The reset source can be identified by checking the reset flags in the Control Status reg...

Page 114: ...ever a Stop mode entry sequence is successfully executed the device is reset instead of entering Stop mode For further information on the User Option Bytes refer to Section 4 Option bytes Option byte loader reset The option byte loader reset is generated when the OBL_LAUNCH bit bit 13 is set in the FLASH_CR register This bit is used to launch the option byte loading by software 9 1 3 RTC domain re...

Page 115: ... The maximum frequency of the AHB and APB2 domains is 72 MHz The maximum allowed frequency of the APB1 domain is 36 MHz All the peripheral clocks are derived from their bus clock HCLK PCLK1 or PCLK2 except The Flash memory programming interface clock FLITFCLK which is always the HSI clock The 48 MHz USB clock which is derived from the PLL VCO The option byte loader clock which is always the HSI cl...

Page 116: ...up to 144 MHz when the system clock source is the PLL Refer to Section 9 2 10 Timers TIMx clock 3 The ADC clock can be derived from the AHB clock of the ADC bus interface divided by a programmable factor 1 2 or 4 When the programmable factor is 1 the AHB prescaler must be equal to 1 0 6 26 26 B 1 26 B287 26 B 1 26 B287 0 6 5 WR 3 3 08 3 SUHVFDOHU 3 WR EXV FRUH PHPRU DQG 0 6 6 6 6 6 WR 57 3 65 6 6 ...

Page 117: ...source is the PLL and AHB 06 9 I 3 SUHVFDOHU HOVH 6 6 6 6 7 WR ODVK SURJUDPPLQJ LQWHUIDFH WR 665 6 6 W FORFN WR 6 86 SUHVFDOHU 86 WR 86 LQWHUIDFH WR EXV FRUH PHPRU DQG 0 WR RUWH V VWHP WLPHU RUWH IUHH UXQQLQJ FORFN 3 6 6 WR 7 0 WR 8 6 57 WR 7 0 WR 3 SHULSKHUDOV 3 WR 86 57 7 0 WR 6 5 N 0 6 26 57 WR 57 3 SUHVFDOHU 0 6 5 6 6 3 3 3 65 3 08 35 9 WR 0 6 6 6 WR 3 SHULSKHUDOV 3 I 3 SUHVFDOHU HOVH 3 6 6 6 ...

Page 118: ...PLL running at 144 MHz when the system clock source is the PLL and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively 3 The ADC clock can be derived from the AHB clock of the ADC bus interface divided by a programmable factor 1 2 or 4 0 6 26 26 B 1 26 B287 26 B 1 26 B287 0 6 5 WR 3 3 08 0 2 3 6 6 3 SUHVFDOHU 3 WR EXV FRUH PHPRU DQG 0 6 6 6 6 6 WR 57 3 65 6 0 2 6 6 57 57 6 6 6...

Page 119: ...from two possible clock sources HSE external crystal ceramic resonator HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time The loading capacitance values must be adjusted according to the selected oscillator Figure 15 HSE LSE clock sources Clock source Hardw...

Page 120: ... CSS which is able to switch OFF the oscillator even in this case External source HSE bypass In this mode an external clock source must be provided It can have a frequency of up to 32 MHz Select this mode by setting the HSEBYP and HSEON bits in the Clock control register RCC_CR The external clock signal square sinus or triangle with 40 60 duty cycle depending on the frequency refer to the datashee...

Page 121: ...tor It has the advantage of providing a low power but highly accurate clock source to the real time clock peripheral RTC for clock calendar or other timing functions The LSE crystal is switched on and off using the LSEON bit in RTC domain control register RCC_BDCR The crystal oscillator driving strength can be changed at runtime using the LSEDRV 1 0 bits in the RTC domain control register RCC_BDCR...

Page 122: ...tem clock it is not possible to stop it A switch from one clock source to another occurs only if the target clock source is ready clock stable after startup delay or PLL locked If a clock source which is not yet ready is selected the switch will occur when the clock source becomes ready Status bits in the Clock control register RCC_CR indicate which clock s is are ready and which clock is currentl...

Page 123: ... to get a PCLK frequency greater than or equal to the RTCCLK frequency for a proper operation of the RTC The LSE clock is in the RTC domain whereas the HSE and LSI clocks are not Consequently If LSE is selected as RTC clock The RTC continues to work even if the VDD supply is switched off provided the VBAT supply is maintained The RTC remains clocked and functional under system reset If LSI is sele...

Page 124: ...provided on I2S_CKIN pin The selection of the I2S clock source is performed using bit 23 I2SSRC of RCC_CFGR register 9 2 13 Clock out capability The microcontroller clock output MCO capability allows the clock to be output onto the external MCO pin The configuration registers of the corresponding GPIO port must be programmed in alternate function mode One of 5 clock signals can be selected as the ...

Page 125: ...e HSI should be used as the system clock source The number of HSI clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period Taking advantage of the high precision of LSE crystals typically a few tens of ppm s it is possible to determine the internal clock frequency with the same resolution and trim the source to compensate for manufacturing process an...

Page 126: ...have the capability to enable the HSI oscillator even when the MCU is in Stop mode if HSI is selected as the clock source for that peripheral All U S ARTs can also be driven by the LSE oscillator when the system is in Stop mode if LSE is selected as clock source for that peripheral and the LSE oscillator is enabled LSEON but they do not have the capability to turn on the LSE oscillator Standby mod...

Page 127: ...the PLL clock is used as system clock or is selected to become the system clock 0 PLL OFF 1 PLL ON Bits 23 20 Reserved must be kept at reset value Bit 19 CSSON Clock security system enable Set and cleared by software to enable the clock security system When CSSON is set the clock detector is enabled by hardware when the HSE oscillator is ready and disabled by hardware if a HSE clock failure is det...

Page 128: ... added to the HSICAL value should trim the HSI to 8 MHz 1 The trimming step Fhsitrim is around 40 kHz between two consecutive HSICAL steps Bit 2 Reserved must be kept at reset value Bit 1 HSIRDY HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable After the HSION bit is cleared HSIRDY goes low after 6 HSI oscillator clock cycles 0 HSI oscillator not ready 1 HSI oscillator...

Page 129: ...a new value It is set by hardware when the switch to the new MCO source is effective Note In the STM32F302x6 8 D E this bit is used with Bits 29 and 30 to select the Microcontroller Clock Output Prescaler Bit 27 Reserved must be kept at reset value Bits 26 24 MCO Microcontroller clock output Set and cleared by software 000 MCO output disabled no clock on MCO 001 Reserved 010 LSI clock selected 011...

Page 130: ...an be written only when the PLL is disabled Note This bit is the same as the LSB of PREDIV in Clock configuration register 2 RCC_CFGR2 for compatibility with other STM32 products 0000 HSE input to PLL not divided 0001 HSE input to PLL divided by 2 Bits 16 15 PLLSRC PLL entry clock source STM32F302xD E only Set and cleared by software to select PLL clock source These bits can be written only when P...

Page 131: ...8 1011 SYSCLK divided by 16 1100 SYSCLK divided by 64 1101 SYSCLK divided by 128 1110 SYSCLK divided by 256 1111 SYSCLK divided by 512 Note The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock Refer to section Read operations on page 59 for more details Bits 3 2 SWS System clock switch status Set and cleared by hardware to indicate which clock source is used...

Page 132: ...F flag Bits 22 21 Reserved must be kept at reset value Bit 20 PLLRDYC PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag 0 No effect 1 Clear PLLRDYF flag Bit 19 HSERDYC HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag 0 No effect 1 Clear HSERDYF flag Bit 18 HSIRDYC HSI ready interrupt clear This bit is set software to clear the HSIRDYF fl...

Page 133: ...re to enable disable interrupt caused by the LSI oscillator stabilization 0 LSI ready interrupt disabled 1 LSI ready interrupt enabled Bit 7 CSSF Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator Cleared by software setting the CSSC bit 0 No clock security interrupt caused by HSE clock failure 1 Clock security interrupt caused by HSE clock failur...

Page 134: ...YDIE is set Cleared by software setting the LSERDYC bit 0 No clock ready interrupt caused by the LSE oscillator 1 Clock ready interrupt caused by the LSE oscillator Bit 0 LSIRDYF LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set Cleared by software setting the LSIRDYC bit 0 No clock ready interrupt caused by the LSI oscillator 1 Clock ready interrupt c...

Page 135: ...reset Set and cleared by software 0 No effect 1 Reset USART1 Bit 13 Reserved must be kept at reset value Bit 12 SPI1RST SPI1 reset STM32F302xB C D E devices only Set and cleared by software 0 No effect 1 Reset SPI1 Bit 11 TIM1RST TIM1 timer reset Set and cleared by software 0 No effect 1 Reset TIM1 timer Bits 10 1 Reserved must be kept at reset value Bit 0 SYSCFGRST SYSCFG Comparators and operatio...

Page 136: ...w rw rw rw rw Bit 31 Reserved must be kept at reset value Bit 30 I2C3RST I2C3 reset Set and cleared by software 0 No effect 1 Reset I2C3 Bit 29 DAC1RST DAC1 interface reset Set and cleared by software 0 No effect 1 Reset DAC1 interface Bit 28 PWRRST Power interface reset Set and cleared by software 0 No effect 1 Reset power interface Bits 27 26 Reserved must be kept at reset value Bit 25 CANRST CA...

Page 137: ...set Set and cleared by software 0 No effect 1 Reset USART2 Bit 16 Reserved must be kept at reset value Bit 15 SPI3RST SPI3 reset Set and cleared by software 0 No effect 1 Reset SPI3 and I2S3 Bit 14 SPI2RST SPI2 reset Set and cleared by software 0 No effect 1 Reset SPI2 and I2S2 Bits 13 12 Reserved must be kept at reset value Bit 11 WWDGRST Window watchdog reset Set and cleared by software 0 No eff...

Page 138: ...TIM2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res ADC12EN Res Res Res TSCEN IOPG EN 1 IOPF EN IOPE EN IOPD EN IOPC EN IOPB EN IOPA EN IOPH EN 1 rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res CRC EN FMC EN 1 FLITF EN Res SRAM EN DMA2 EN DMA1 EN rw rw rw rw rw rw 1 Only on STM32F302xDxE Bits 31 29 Reserved must be kept at reset ...

Page 139: ...d by software 0 I O port B clock disabled 1 I O port B clock enabled Bit 17 IOPAEN I O port A clock enable Set and cleared by software 0 I O port A clock disabled 1 I O port A clock enabled Bit 16 IOPHEN IO port H clock enable Only on STM32F302xDxE Set and cleared by software 0 IO port H clock disabled 1 IO port H clock enabled Bits 15 7 Reserved must be kept at reset value Bit 6 CRCEN CRC clock e...

Page 140: ...ing Sleep mode Bit 1 DMA2EN DMA2 clock enable STM32F302xB C devices only Set and cleared by software 0 DMA2 clock disabled 1 DMA2 clock enabled Bit 0 DMA1EN DMA1 clock enable Set and cleared by software 0 DMA1 clock disabled 1 DMA1 clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res TIM17 EN TIM16 EN TIM15 EN rw rw rw 15 14 13 12 11 10 ...

Page 141: ...ck enable Set and cleared by software 0 USART1 clock disabled 1 USART1 clock enabled Bit 13 Reserved must be kept at reset value Bit 12 SPI1EN SPI1 clock enable STM32F302xB C devices only Set and cleared by software 0 SPI1 clock disabled 1 SPI1 clock enabled Bit 11 TIM1EN TIM1 timer clock enable Set and cleared by software 0 TIM1 timer clock disabled 1 TIM1 timer clock enabled Bits 10 1 Reserved m...

Page 142: ...able Set and reset by software 0 CAN clock disabled 1 CAN clock enabled Bit 24 Reserved must be kept at reset value Bit 23 USBEN USB clock enable Set and reset by software 0 USB clock disabled 1 USB clock enabled Bit 22 I2C2EN I2C2 clock enable Set and cleared by software 0 I2C2 clock disabled 1 I2C2 clock enabled Bit 21 I2C1EN I2C1 clock enable Set and cleared by software 0 I2C1 clock disabled 1 ...

Page 143: ...watchdog clock enable Set and cleared by software 0 Window watchdog clock disabled 1 Window watchdog clock enabled Bits 10 5 Reserved must be kept at reset value Bit 4 TIM6EN TIM6 timer clock enable Set and cleared by software 0 TIM6 clock disabled 1 TIM6 clock enabled Bit 3 Reserved must be kept at reset value Bit 2 TIM4EN TIM4 timer clock enable STM32F302xB C D E devices only Set and cleared by ...

Page 144: ...w Bits 31 17 Reserved must be kept at reset value Bit 16 BDRST RTC domain software reset Set and cleared by software 0 Reset not activated 1 Resets the entire RTC domain Bit 15 RTCEN RTC clock enable Set and cleared by software 0 RTC clock disabled 1 RTC clock enabled Bits 14 10 Reserved must be kept at reset value Bits 9 8 RTCSEL 1 0 RTC clock source selection Set by software to select the clock ...

Page 145: ...al low speed oscillator clock cycles 0 LSE oscillator not ready 1 LSE oscillator ready Bit 0 LSEON LSE oscillator enable Set and cleared by software 0 LSE oscillator OFF 1 LSE oscillator ON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR RSTF WWDG RSTF IW WDG RSTF SFT RSTF POR RSTF PIN RSTF OB LRSTF RMVF V18PW RRSTF Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res...

Page 146: ...urred Bit 25 OBLRSTF Option byte loader reset flag Set by hardware when a reset from the OBL occurs Cleared by writing to the RMVF bit 0 No reset from OBL occurred 1 Reset from OBL occurred Bit 24 RMVF Remove reset flag Set by software to clear the reset flags 0 No effect 1 Clear the reset flags Bit 23 V18PWRRSTF Reset flag of the 1 8 V domain Set by hardware when a POR PDR of the 1 8 V domain occ...

Page 147: ...T ADC1 and ADC2 reset only ADC1 on STM32F302x6 8 devices Set and reset by software 0 does not reset the ADC1 and ADC2 1 resets the ADC1 and ADC2 Bits 27 25 Reserved must be kept at reset value Bit 24 TSCRST Touch sensing controller reset Set and cleared by software 0 No effect 1 Reset TSC Bit 23 IOPGRST I O port G reset Only on STM32F302xDxE Set and cleared by software 0 No effect 1 Reset I O port...

Page 148: ...o effect 1 Reset I O port A Bit 16 IOPHRST I O port H reset Only on STM32F302xDxE Set and cleared by software 0 No effect 1 Reset I O port H Bits 15 6 Reserved must be kept at reset value Bit 5 FMCRST FMC reset Only on STM32F302xDxE Set and cleared by software 0 No effect 1 Reset FMC Bits 4 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res R...

Page 149: ...ese bits are set and cleared by software to select PREDIV division factor They can be written only when the PLL is disabled Note Bit 0 is the same bit as bit17 in Clock configuration register RCC_CFGR so modifying bit17 Clock configuration register RCC_CFGR also modifies bit 0 in Clock configuration register 2 RCC_CFGR2 for compatibility with other STM32 products 0000 HSE input to PLL not divided ...

Page 150: ...bit again in case of a new switch is required 0 PCLK2 clock doubled frequency when prescaled default 1 PLL vco output running up to 144 MHz Note STM32F302xDxE only Bit 24 TIM2SW Timer2 clock source selection Set and reset by software to select TIM2 clock source The bit is writable only when the following conditions occur clock system PLL and AHB or APB2 subsystem clocks are not divided by more tha...

Page 151: ... the bit again in case of a new switch is required 0 PCLK2 clock doubled frequency when prescaled default 1 PLL vco output running up to 144 MHz Note STM32F302x6 8 and STM32F302xD E devices only Bit 12 Reserved must be kept at reset value Bit 11 TIM16SW Timer16 clock source selection Set and reset by software to select TIM16 clock source The bit is writable only when the following conditions occur...

Page 152: ... by software to select the I2C3 clock source 0 HSI clock selected as I2C3 clock source default 1 SYSCLK clock selected as I2C3 clock Bit 5 I2C2SW I2C2 clock source selection This bit is set and cleared by software to select the I2C2 clock source 0 HSI clock selected as I2C2 clock source default 1 SYSCLK clock selected as I2C2 clock Bit 4 I2C1SW I2C1 clock source selection This bit is set and clear...

Page 153: ...2RSTR Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM16RST TIM15RST SPI4RST 3 USART1RST Res SPI1RST TIM1RST Res Res Res Res Res Res Res Res Res Res SYSCFGRST Reset value 0 0 0 0 0 0 0 0x010 RCC_ APB1RSTR Res I2C3RST 1 DAC1RST PWRRST Res Res CANRST Res USBRST I2C2RST I2C1RST UART5RST 2 UART4RST 2 USART3RST USART2RST Res SPI3RST SPI2RST Res Res WWDGRST Res Res Res Res Res Res TIM6RST Res...

Page 154: ...es Res TSCRST IOPGRST 3 IOPFRST IOPERST 2 IOPDRST IOPCRST IOPBRST IOPARST IOPHRST 3 Res Res Res Res Res Res Res Res Res Res FMCRST 3 Res Res Res Res Res Reset value 0 0 0 0 0 0 0 0 0x2C RCC_CFGR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res ADC12PRES 4 0 PREDIV 3 0 Reset value 0 0 0x30 RCC_CFGR3 Res Res Res Res Res Res TIM34SW 3 TIM2SW 3 UART5SW 1 0 2...

Page 155: ...n STM32F302xD E A B and D I O configuration in STM32F302xB C devices and port A B C D and F in STM32F302x6 8 devices Analog function Alternate function selection registers Fast toggle capable of changing every clock cycle Highly flexible pin multiplexing allows the use of I O pins as GPIOs or as one of several peripheral functions 10 3 GPIO functional description Subject to the specific hardware c...

Page 156: ...T LTERNATE FUNCTION INPUT 0USH PULL OPEN DRAIN OR DISABLED NPUT DATA REGISTER UTPUT DATA REGISTER 2EAD WRITE ROM ON CHIP PERIPHERAL 4O ON CHIP PERIPHERAL UTPUT CONTROL NALOG ON OFF 0ULL 0ULL DOWN ON OFF PIN 6 6 633 633 TRIGGER 633 6 0ROTECTION DIODE 0ROTECTION DIODE ON OFF NPUT DRIVER UTPUT DRIVER UP 0 3 3 2EAD IT SET RESET REGISTERS 7RITE NALOG AI LTERNATE FUNCTION OUTPUT LTERNATE FUNCTION INPUT ...

Page 157: ...x_IDR captures the data present on the I O pin at every AHB clock cycle Table 30 Port bit configuration table 1 1 GP general purpose PP push pull PU pull up PD pull down OD open drain AF alternate function MODER i 1 0 OTYPER i OSPEEDR i 1 0 PUPDR i 1 0 I O configuration 01 0 SPEED 1 0 0 0 GP output PP 0 0 1 GP output PP PU 0 1 0 GP output PP PD 0 1 1 Reserved 1 0 0 GP output OD 1 0 1 GP output OD ...

Page 158: ...eral has alternate functions mapped onto different I O pins to optimize the number of peripherals available in smaller packages To use an I O in a given configuration the user has to proceed as follows Debug function after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host GPIO configure the desired I O as output input or analog in the GPIO...

Page 159: ...n written to 1 bit BS i sets the corresponding ODR i bit When written to 1 bit BR i resets the ODR i corresponding bit Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR If there is an attempt to both set and reset a bit in GPIOx_BSRR the set action takes priority Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a ...

Page 160: ...The application can thus select any one of the possible functions for each I O The AF selection signal being common to the alternate function input and alternate function output a single channel is selected for the alternate function input output of a given I O To know which functions are multiplexed on each GPIO pin refer to the device datasheet 10 3 8 External interrupt wakeup lines All ports ha...

Page 161: ... activates the P MOS The Schmitt trigger input is activated The pull up and pull down resistors are activated depending on the value in the GPIOx_PUPDR register The data present on the I O pin are sampled into the input data register every AHB clock cycle A read access to the input data register gets the I O state A read access to the output data register gets the last written value Figure 20 show...

Page 162: ...A read access to the input data register gets the I O state Figure 21 shows the Alternate function configuration of the I O port bit Figure 21 Alternate function configuration 0USH PULL OR PEN DRAIN UTPUT CONTROL 6 633 44 3CHMITT TRIGGER ON NPUT DRIVER UTPUT DRIVER 0 3 3 NPUT DATA REGISTER UTPUT DATA REGISTER 2EAD WRITE 2EAD IT SET RESET REGISTERS 7RITE ON OFF PULL PULL ON OFF 6 633 633 6 PROTECTI...

Page 163: ...r LSE oscillator is switched ON by setting the HSEON or LSEON bit in the RCC_CSR register the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect When the oscillator is configured in a user external clock mode only the pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO 10 3 14 Using the GPIO pins in t...

Page 164: ... rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODER7 1 0 MODER6 1 0 MODER5 1 0 MODER4 1 0 MODER3 1 0 MODER2 1 0 MODER1 1 0 MODER0 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y 1 2y MODERy 1 0 Port x configuration bits y 0 15 These bits are written by software to configure the I O mode 00 Input mode reset state 01 General purpose output mode 10 Alter...

Page 165: ...EDR1 1 0 OSPEEDR0 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y 1 2y OSPEEDRy 1 0 Port x configuration bits y 0 15 These bits are written by software to configure the I O output speed x0 Low speed 01 Medium speed 11 High speed Note Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed 31 30 29 28 27 26 25 24 23 22 21 20...

Page 166: ...0 15 These bits are read only They contain the input value of the corresponding I O port 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be...

Page 167: ...er Only word access 32 bit long is allowed during this locking sequence Each lock bit freezes a specific configuration register control and alternate function registers Address offset 0x1C Reset value 0x0000 0000 Bits 31 16 BRy Port x reset bit y y 0 15 These bits are write only A read to these bits returns the value 0x0000 0 No action on the corresponding ODRx bit 1 Resets the corresponding ODRx ...

Page 168: ...e Note During the LOCK key write sequence the value of LCK 15 0 must not change Any error in the lock sequence aborts the lock After the first lock sequence on any bit of the port any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset Bits 15 0 LCKy Port x lock bit y y 0 15 These bits are read write but can only be written when the LCKK bit is 0 0 Port configura...

Page 169: ...in y y 8 15 These bits are written by software to configure alternate function I Os 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31 16 Reserved Bits 15 0 BRy Port x Reset bit y y 0 15 Thes...

Page 170: ... Res Res Res Res Res Res Res Res Res Res Res Res Res OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 GPIOA_OSPEEDR OSPEEDR15 1 0 OSPEEDR14 1 0 OSPEEDR13 1 0 OSPEEDR12 1 0 OSPEEDR11 1 0 OSPEEDR10 1 0 OSPEEDR9 1 0 OSPEEDR8 1 0 OSPEEDR7 1 0 OSPEEDR6 1 0 OSPEEDR5 1 0 OSPEEDR4 1 0 OSPEEDR3 1 0 OSPEEDR2 1 0 OSPEEDR1 1 0 OSPEEDR0 1 0 ...

Page 171: ...15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C GPIOx_LCKR where x see 1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res LCKK LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 Reset...

Page 172: ...onfigurations on memory remap Two bits are used to configure the type of memory accessible at address 0x0000 0000 These bits are used to select the physical remap by software and so bypass the BOOT pin and the option bit setting After reset these bits take the value selected by the BOOT pin BOOT0 and by the option bit BOOT1 Address offset 0x00 Reset value 0x7C00 000X X is the memory mode selected ...

Page 173: ...e Fm on I2C2 pins selected through AF selection bits 0 Fm mode is not enabled on I2C2 pins selected through AF selection bits 1 Fm mode is enabled on I2C2 pins selected through AF selection bits Bit 20 I2C1_FMP I2C1 Fm driving capability activation This bit is set and cleared by software It enables the Fm on I2C1 pins selected through AF selection bits 0 Fm mode is not enabled on I2C1 pins selecte...

Page 174: ... This bit is set and cleared by software It controls the mapping of the DAC trigger source 0 No remap 1 Remap DAC trigger is TIM3_TRGO Bit 6 TIM1_ITR3_RMP Timer 1 ITR3 selection This bit is set and cleared by software It controls the mapping of TIM1 ITR3 0 No remap TIM1_ITR3 TIM4_TRGO in STM32F302xB C D E devices 1 Remap TIM1_ITR3 TIM17_OC Bits 5 3 Reserved must be kept at reset value Bits 2 0 MEM...

Page 175: ...t the source input for the EXTI2 external interrupt x000 PA 2 pin x001 PB 2 pin x010 PC 2 pin x011 PD 2 pin x100 PE 2 pin x101 PF 2 pin other configurations reserved Bits 7 4 EXTI1 3 0 EXTI 1 configuration bits These bits are written by software to select the source input for the EXTI1 external interrupt x000 PA 1 pin x001 PB 1 pin x010 PC 1 pin x011 PD 1 pin x100 PE 1 pin x101 PF 1 pin other conf...

Page 176: ...010 PC 7 pin x011 PD 7 pin x100 PE 7 pin Other configurations reserved Bits 11 8 EXTI6 3 0 EXTI 6 configuration bits These bits are written by software to select the source input for the EXTI6 external interrupt x000 PA 6 pin x001 PB 6 pin x010 PC 6 pin x011 PD 6 pin x100 PE 6 pin x101 PF 6 pin Other configurations reserved Bits 7 4 EXTI5 3 0 EXTI 5 configuration bits These bits are written by sof...

Page 177: ... Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11 3 0 EXTI10 3 0 EXTI9 3 0 EXTI8 3 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 12 EXTI11 3 0 EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt x000 PA 11 pin x001 PB 11 pin x010 PC 11 p...

Page 178: ...11 PD 10 pin x100 PE 10 pin x101 PF 10 pin other configurations reserved Bits 7 4 EXTI9 3 0 EXTI 9 configuration bits These bits are written by software to select the source input for the EXTI9 external interrupt x000 PA 9 pin x001 PB 9 pin x010 PC 9 pin x011 PD 9 pin x100 PE 9 pin x101 PF 9 pin other configurations reserved Bits 3 0 EXTI8 3 0 EXTI 8 configuration bits These bits are written by so...

Page 179: ... pin x001 PB 15 pin x010 PC 15 pin x011 PD 15 pin x100 PE 15 pin Other configurations reserved Bits 11 8 EXTI14 3 0 EXTI14 configuration bits These bits are written by software to select the source input for the EXTI14 external interrupt x000 PA 14 pin x001 PB 14 pin x010 PC 14 pin x011 PD 14 pin x100 PE 14 pin Other configurations reserved Bits 7 4 EXTI13 3 0 EXTI13 configuration bits These bits ...

Page 180: ...tected It is cleared by software by writing 1 0 No SRAM parity error detected 1 SRAM parity error detected Bits 7 5 Reserved must be kept at reset value Bit 4 BYP_ADDR_PAR Bypass address bit 29 in parity calculation STM32F302xB C D E devices only This bit is set by software and cleared by a system reset It is used to prevent an unwanted parity error when the user writes a code in the RAM at addres...

Page 181: ...Y_LOCK SRAM parity lock bit STM32F302xB C D E devices only This bit is set by software and cleared by a system reset It can be used to enable and lock the SRAM parity error signal connection to TIM1 15 16 17 Break inputs 0 SRAM parity error signal disconnected from TIM1 15 16 17 Break inputs 1 SRAM parity error signal connected to TIM1 15 16 17 Break inputs Bit 0 LOCKUP_LOCK Cortex M4 LOCKUP Hardf...

Page 182: ...0 0 0 0 0 0 0 0 0 0 0 0 0 X X 0x08 SYSCFG_EXTICR1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res EXTI3 3 0 EXTI2 3 0 EXTI1 3 0 EXTI0 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C SYSCFG_EXTICR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res EXTI7 3 0 EXTI6 3 0 EXTI5 3 0 EXTI4 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 SYSCFG_EXTICR3 Res Res Res Re...

Page 183: ...supported on each channel This configuration is done by software Priorities between requests from the DMA channels are software programmable 4 levels consisting of very high high medium low or hardware in case of equality request 1 has priority over request 2 etc Independent source and destination transfer size byte half word word emulating packing and unpacking Source destination addresses must b...

Page 184: ...obin scheduling thus ensuring at least half of the system bus bandwidth both to memory and peripheral for the CPU 12 4 1 DMA transactions After an event the peripheral sends a request signal to the DMA Controller The DMA controller serves the request depending on the channel priorities As soon as the DMA Controller accesses the peripheral an Acknowledge is sent to the peripheral by the DMA Control...

Page 185: ...ority can be configured in the DMA_CCRx register There are four levels Very high priority High priority Medium priority Low priority Hardware if 2 requests have the same software priority level the channel with the lowest number will get priority versus the channel with the highest number For example channel 2 gets priority over channel 4 12 4 3 DMA channels Each channel can handle DMA transfer be...

Page 186: ...data to be transferred in the DMA_CNDTRx register After each peripheral event this value will be decremented 4 Configure the channel priority using the PL 1 0 bits in the DMA_CCRx register 5 Configure data transfer direction circular mode peripheral memory incremented mode peripheral memory data size and interrupt after half and or full transfer in the DMA_CCRx register 6 Activate the channel by s...

Page 187: ...B1B0 15 0 0x0 then WRITE B0 7 0 0x0 2 READ B3B2 15 0 0x2 then WRITE B2 7 0 0x1 3 READ B5B4 15 0 0x4 then WRITE B4 7 0 0x2 4 READ B7B6 15 0 0x6 then WRITE B6 7 0 0x3 0x0 B0 0x1 B2 0x2 B4 0x3 B6 16 16 4 0x0 B1B0 0x2 B3B2 0x4 B5B4 0x6 B7B6 1 READ B1B0 15 0 0x0 then WRITE B1B0 15 0 0x0 2 READ B3B2 15 0 0x2 then WRITE B3B2 15 0 0x2 3 READ B5B4 15 0 0x4 then WRITE B5B4 15 0 0x4 4 READ B7B6 15 0 0x6 then...

Page 188: ...rted to an APB word write operation of the data 0xB1B0B1B0 to 0x0 For instance to write the APB backup registers 16 bit registers aligned to a 32 bit address boundary the software must configure the memory source size MSIZE to 16 bit and the peripheral destination size PSIZE to 32 bit 12 4 5 Error management A DMA transfer error can be generated by reading from or writing to a reserved address spa...

Page 189: ...at on one channel only one request must be enabled at a time Refer to Figure 24 STM32F302xB C D E and STM32F302x6 8 DMA1 request mapping and Figure 25 STM32F302x6 8 DMA1 request mapping The peripheral DMA requests can be independently activated de activated by programming the DMA control bit in the registers of the corresponding peripheral ...

Page 190: ... VLJQDOV LJK SULRULW RZ SULRULW 0 06 9 UHTXHVW 0 0 0 0 ELW KDQQHO UHTXHVW KDQQHO UHTXHVW KDQQHO UHTXHVW 6 WULJJHU 0 0 0 0 ELW KDQQHO 0 0 0 0 ELW 6 WULJJHU 0 0 0 0 ELW 6 WULJJHU 6 WULJJHU UHTXHVW KDQQHO 6 WULJJHU 0 0 0 0 ELW UHTXHVW KDQQHO 6 WULJJHU 0 0 0 0 ELW UHTXHVW KDQQHO 6 WULJJHU 0 0 0 0 ELW 7 0 B 7 0 B 7 0 B 7 0 B83 63 B5 86 57 B7 7 0 B 7 0 B83 7 0 B 63 B7 86 57 B5 7 0 B 7 0 B 7 0 B83 7 0 B8...

Page 191: ...HVW L HG KDUGZDUH SULRULW 3HULSKHUDO UHTXHVW VLJQDOV LJK SULRULW RZ SULRULW 0 06 9 UHTXHVW 0 0 0 0 ELW KDQQHO UHTXHVW KDQQHO UHTXHVW KDQQHO UHTXHVW 6 WULJJHU 0 0 0 0 ELW KDQQHO 0 0 0 0 ELW 6 WULJJHU 0 0 0 0 ELW 6 WULJJHU 6 WULJJHU UHTXHVW KDQQHO 6 WULJJHU 0 0 0 0 ELW UHTXHVW KDQQHO 6 WULJJHU 0 0 0 0 ELW UHTXHVW KDQQHO 6 WULJJHU 0 0 0 0 ELW 7 0 B 7 0 B 7 0 B83 86 57 B7 7 0 B 7 0 B83 63 B7 86 57 B5 ...

Page 192: ...15_CH1 TIM15_UP TIM15_TRIG TIM15_COM TIM16 TIM16_CH1 TIM16_UP TIM16_CH1 TIM16_UP 2 TIM17 TIM17_CH1 TIM17_UP TIM17_CH1 TIM17_UP 2 1 Available in STM32F302xD E only 2 DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 register For more details please refer to Section 11 1 1 SYSCFG configuration register 1 SYSCFG_CFGR1 on page 172 Table 37 STM32F...

Page 193: ...vated de activated by programming the DMA control bit in the registers of the corresponding peripheral TIM15 TIM15_CH1 TIM15_UP TIM15_TRIG TIM15_COM TIM16 TIM16_CH1 TIM16_UP TIM16_CH1 TIM16_UP 1 TIM17 TIM17_CH1 TIM17_UP TIM17_CH1 TIM17_UP 1 1 DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 or SYSCFGR3 register For more details please refer ...

Page 194: ...register For more details please refer to Section 11 1 1 SYSCFG configuration register 1 SYSCFG_CFGR1 on page 172 UHTXHVW 0 0 0 0 ELW KDQQHO QWHUQDO 0 UHTXHVW L HG KDUGZDUH SULRULW 3HULSKHUDO UHTXHVW VLJQDOV LJK SULRULW RZ SULRULW 0 06 9 UHTXHVW KDQQHO UHTXHVW KDQQHO UHTXHVW 6 WULJJHU 0 0 0 0 ELW KDQQHO UHTXHVW KDQQHO 6 WULJJHU 0 0 0 0 ELW 0 0 0 0 ELW 6 WULJJHU 0 0 0 0 ELW 6 WULJJHU 6 WULJJHU 30 2...

Page 195: ...MA requests for each channel Table 38 STM32F302xB C D E summary of DMA2 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 ADC ADC2 SPI3 SPI3_RX SPI3_TX SPI4_RX 1 SPI4_TX 1 UART4 UART4_RX UART4_TX TIM6 DAC TIM6_UP DAC_CH1 1 Available in STM32F302xD E only ...

Page 196: ...s bit is set by hardware It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register 0 No transfer error TE on channel x 1 A transfer error TE occurred on channel x Bits 26 22 18 14 10 6 2 HTIFx Channel x half transfer flag x 1 7 This bit is set by hardware It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register 0 No half transfer HT event on...

Page 197: ...28 Reserved must be kept at reset value Bits 27 23 19 15 11 7 3 CTEIFx Channel x transfer error clear x 1 7 This bit is set by software 0 No effect 1 Clears the corresponding TEIF flag in the DMA_ISR register Bits 26 22 18 14 10 6 2 CHTIFx Channel x half transfer clear x 1 7 This bit is set by software 0 No effect 1 Clears the corresponding HTIF flag in the DMA_ISR register Bits 25 21 17 13 9 5 1 ...

Page 198: ...memory mode This bit is set and cleared by software 0 Memory to memory mode disabled 1 Memory to memory mode enabled Bits 13 12 PL 1 0 Channel priority level These bits are set and cleared by software 00 Low 01 Medium 10 High 11 Very high Bits 11 10 MSIZE 1 0 Memory size These bits are set and cleared by software 00 8 bits 01 16 bits 10 32 bits 11 Reserved Bits 9 8 PSIZE 1 0 Peripheral size These ...

Page 199: ...mory Bit 3 TEIE Transfer error interrupt enable This bit is set and cleared by software 0 TE interrupt disabled 1 TE interrupt enabled Bit 2 HTIE Half transfer interrupt enable This bit is set and cleared by software 0 HT interrupt disabled 1 HT interrupt enabled Bit 1 TCIE Transfer complete interrupt enable This bit is set and cleared by software 0 TC interrupt disabled 1 TC interrupt enabled Bit...

Page 200: ...ister can only be written when the channel is disabled Once the channel is enabled this register is read only indicating the remaining bytes to be transmitted This register decrements after each DMA transfer Once the transfer is completed this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in circular mode If this regis...

Page 201: ...8 27 26 25 24 23 22 21 20 19 18 17 16 MA 31 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MA 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 MA 31 0 Memory address Base address of the memory area from to which the data will be read written When MSIZE is 01 16 bit the MA 0 bit is ignored Access is automatically aligned to a half word address...

Page 202: ... 0 0 0 0 0 0 0 0 0 0 0 0 0x14 DMA_CMAR1 MA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x18 Reserved Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x1C DMA_CCR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res MEM2MEM PL 1 0 MSIZE 1 0 PSIZE 1 0 MINC PINC CIRC DI...

Page 203: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x64 DMA_CMAR5 MA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x68 Reserved Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x6C DMA_CCR6 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res MEM2MEM PL 1 0 MSI...

Page 204: ...0 0 0 0 0 0 0 0 0 0 0 0x8C DMA_CMAR7 MA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x90 0xA7 Reserved Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Table 39 DMA register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ...

Page 205: ...r to the PM0214 programming manual for Cortex M4 products 13 1 2 SysTick calibration value register The SysTick calibration value is set to 9000 which gives a reference time base of 1 ms with the SysTick clock set to 9 MHz max fHCLK 8 13 1 3 Interrupt and exception vectors Table 40 is the vector table for STM32F302xB C devices Table 41 is the vector table for STM32F302x6 8 devices Table 40 STM32F3...

Page 206: ...ble DMA1_Channel2 DMA1 channel 2 interrupt 0x0000 0070 13 20 settable DMA1_Channel3 DMA1 channel 3 interrupt 0x0000 0074 14 21 settable DMA1_Channel4 DMA1 channel 4 interrupt 0x0000 0078 15 22 settable DMA1_Channel5 DMA1 channel 5 interrupt 0x0000 007C 16 23 settable DMA1_Channel6 DMA1 channel 6 interrupt 0x0000 0080 17 24 settable DMA1_Channel7 DMA1 channel 7 interrupt 0x0000 0084 18 25 settable ...

Page 207: ...table USBWakeUp USB wakeup from Suspend EXTI line 18 0x0000 00E8 43 50 settable Reserved 0x0000 00EC 44 51 settable Reserved 0x0000 00F0 45 52 settable Reserved 0x0000 00F4 46 53 settable Reserved 0x0000 00F8 47 54 settable Reserved 0x0000 00FC 48 55 settable FMC 2 FMC global interrupt 0x0000 0100 49 56 Reserved 0x0000 0104 50 57 Reserved 0x0000 0108 51 58 settable SPI3 SPI3 global interrupt 0x000...

Page 208: ...8 75 82 settable USB_LP USB Low priority interrupt 0x0000 016C 76 83 settable USB_WakeUp_RMP see note 1 USB wake up from Suspend and EXTI Line 18 0x0000 0170 81 88 settable FPU Floating point interrupt 0x0000 0184 84 91 settable SPI4 SPI4 Global interrupt 2 0x0000 0190 1 It is possible to remap the USB interrupts USB_HP USB_LP and USB_WKUP on interrupt lines 74 75 and 76 respectively by setting th...

Page 209: ...RCC RCC global interrupt 0x0000 0054 6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 0058 7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C 8 15 settable EXTI2_TS EXTI Line2 and Touch sensing interrupts 0x0000 0060 9 16 settable EXTI3 EXTI Line3 0x0000 0064 10 17 settable EXTI4 EXTI Line4 0x0000 0068 11 18 settable DMA1_Channel1 DMA1 channel 1 interrupt 0x0000 006C 12 19 settable DMA1_Channel2 ...

Page 210: ...2_EV I2C2 event interrupt 0x0000 00C4 34 41 I2C2_ER I2C2 error interrupt 0x0000 00C8 35 42 Reserved 0x0000 00CC 36 43 SPI2 SPI2 global interrupt 0x0000 00D0 37 44 settable USART1 USART1 global interrupt EXTI Line 25 0x0000 00D4 38 45 settable USART2 USART2 global interrupt 0x0000 00D8 39 46 settable USART3 USART3 global interrupt 0x0000 00DC 40 47 settable EXTI15_10 EXTI Line 15 10 interrupts 0x00...

Page 211: ...terrupts respectively 0x0000 0144 67 74 Reserved 0x0000 014C 68 75 Reserved 0x0000 0150 69 76 Reserved 0x0000 0154 70 77 Reserved 0x0000 0158 71 78 Reserved 0x0000 015C 72 79 I2C3_EV I2C3 event interrupt EXTI Line27 interrupt 0x0000 0160 73 80 I2C3_ER I2C3 error interrupt 0x0000 0164 74 81 USB_HP USB High Priority global interrupt remap 0x0000 0168 75 82 USB_LP USB Low Priority global interrupt re...

Page 212: ...is always a simple pulse and it s used for triggering the core wake up For internal interrupts the pending status is assured by the generating peripheral so no need for a specific flag Each input line can be masked independently for interrupt or event generation in addition the internal lines are sampled only in STOP mode This controller allows also to emulate the only external events by software ...

Page 213: ...ending bit in the NVIC interrupt clear pending register have to be cleared or by configuring an external or internal EXTI line in event mode When the CPU resumes from WFE it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set 13 2 4 Asynchronous Internal Interrupts Some communication periph...

Page 214: ...ent mask register When the selected edge occurs on the event line an event pulse is generated The pending bit corresponding to the event line is not set For the external lines an interrupt event request can also be generated by software by writing a 1 in the software interrupt event register Note The interrupts or events associated to the internal lines can be triggered only when the system is in ...

Page 215: ... are internal including the reserved ones the remaining 28 lines are external The GPIOs are connected to the 16 external interrupt event lines in the following manner Figure 28 External interrupt event GPIO mapping 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84 84 84 84 BITS IN THE 393 84 2 REGISTER 84 BITS IN THE 393 84 2 REGISTER 84 BITS IN THE 393 84 2 REGISTER 3 6 ...

Page 216: ...line 23 is connected to I2C1 wakeup EXTI line 24 is connected to I2C2 wakeup EXTI line 25 is connected to USART1 wakeup EXTI line 26 is connected to USART2 wakeup STM32F302xB C D E only EXTI line 27 is connected to I2C3 wakeup STM32F302x6 8 devices only EXTI line 28 is connected to USART3 wakeup STM32F302xB C D E only EXTI line 29 is reserved EXTI line 30 is connected to Comparator 4 output EXTI l...

Page 217: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 Reserved must be kept at reset value Bit 30 MRx Interrupt Mask on external internal line x x 30 0 Interrupt request from Line x is masked 1 Interrupt request from Line x is not masked Bit 29 Reserved must be kept at reset value Bits 28 0 M...

Page 218: ...external internal line x x 30 0 Event request from Line x is masked 1 Event request from Line x is not masked Bit 29 Reserved must be kept at reset value Bits 28 0 MRx Event Mask on external internal line x 0 Event request from Line x is masked 1 Event request from Line x is not masked ...

Page 219: ...t of line x x 30 0 Rising trigger disabled for Event and Interrupt for input line 1 Rising trigger enabled for Event and Interrupt for input line Bits 29 23 Reserved must be kept at reset value Bits 22 0 TRx Rising trigger event configuration bit of line x x 22 to 0 0 Rising trigger disabled for Event and Interrupt for input line 1 Rising trigger enabled for Event and Interrupt for input line 31 3...

Page 220: ...rw rw rw rw rw rw Bit 31 Reserved must be kept at reset value Bit 30 SWIERx Software interrupt on line x x 30 If the interrupt is enabled on this line in the EXTI_IMR writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation This bit is cleared by clearing the corresponding bit in the EXTI_PR register by writing a 1 into the ...

Page 221: ...en the selected edge event arrives on the external interrupt line This bit is cleared by writing a 1 to the bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res MR35 MR34 Res MR32 rw rw rw Bits 31 4 Reserved must be kept at reset value Bits 3 2 MRx In...

Page 222: ...est from Line x is masked 1 Event request from Line x is not masked Bit 1 Reserved must be kept at reset value Bit 0 MR32 Event mask on external internal line x x 32 0 Event request from Line x is masked 1 Event request from Line x is not masked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res ...

Page 223: ...for Event and Interrupt for input line 1 Falling trigger enabled for Event and Interrupt for input line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res SWIER 32 rw Bits 31 1 Reserved must be kept at reset value Bit 0 SWIERx Software inter...

Page 224: ...Reserved must be kept at reset value Bit 0 PRx Pending bit on line x x 32 0 No trigger request occurred 1 Selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line This bit is cleared by writing a 1 into the bit ...

Page 225: ...s TR 22 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 EXTI_SWIER1 Res SWIER30 Res Res Res Res Res Res Res SWIER 17 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 EXTI_PR1 Res PR30 Res Res Res Res Res Res Res PR 22 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 EXTI_IMR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res ...

Page 226: ...s Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res SWIER32 Reset value 0 0x34 EXTI_PR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PR32 Reset value 0 Table 42 External interrupt event controller register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 227: ...terface with static memory mapped devices including Static random access memory SRAM NOR Flash memory OneNAND Flash memory PSRAM 4 memory banks 16 bit PC Card compatible devices Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of data Burst mode support for faster access to synchronous devices such as NOR Flash memory PSRAM Programmable continuous clock output for asynchron...

Page 228: ...However the settings can be changed at any time 14 2 Block diagram The FMC consists of the following main blocks The AHB interface including the FMC configuration registers The NOR Flash PSRAM SRAM controller The NAND Flash PC Card controller The external device interface The block diagram is shown in Figure 29 Figure 29 FMC block diagram 06 9 125 365 0 VLJQDOV 0 B1 0 B1 RU 1 9 0 B 0 B12 0 B1 0 B1...

Page 229: ...Bank 1 to 4 which is not enabled When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the FMC_BCRx register When reading or writing to the PC Card banks while the FMC_CD input pin Card Presence Detection is low The effect of an AHB error depends on the AHB master which has attempted the R W access If the access has been attempted by the Cortex M4 with FPU CPU a hard fault...

Page 230: ...lash memories This situation occurs when a byte access is requested to a 16 bit wide Flash memory Since the device cannot be accessed in byte mode only 16 bit words can be read written from to the Flash memory Write transactions and Read transactions are allowed the controller reads the entire 16 bit memory word and uses only the required byte Configuration registers The FMC can be configured thro...

Page 231: ...ata width as shown in the following table Figure 30 FMC memory banks 06 9 125 365 0 65 0 6XSSRUWHG PHPRU W SH DQN GGUHVV 3 DUG 1 1 ODVK PHPRU DQN 0 DQN 0 DQN 0 DQN 0 Table 43 NOR PSRAM bank selection HADDR 27 26 1 1 HADDR are internal AHB address lines that are translated to external memory Selected bank 00 Bank 1 NOR PSRAM 1 01 Bank 1 NOR PSRAM 2 10 Bank 1 NOR PSRAM 3 11 Bank 1 NOR PSRAM 4 Table ...

Page 232: ...d section To specify the NAND Flash address that must be read or written the software must write the address value to any memory location in the address section Since an address can be 4 or 5 bytes long depending on the actual memory size several 1 In case of a 16 bit external memory width the FMC will internally use HADDR 25 1 to generate the address for external memory FMC_A 24 0 Whatever the ex...

Page 233: ...Programmable bus turnaround cycles up to 15 Programmable output enable and write enable delays up to 15 Independent read and write timings and protocol to support the widest variety of memories and timings Programmable continuous clock FMC_CLK output The FMC Clock FMC_CLK is a submultiple of the HCLK clock It can be delivered to the selected external device either during synchronous accesses only ...

Page 234: ...setup Duration of the address setup phase Asynchronous AHB clock cycle HCLK 0 15 Address hold Duration of the address hold phase Asynchronous muxed I Os AHB clock cycle HCLK 1 15 Data setup Duration of the data setup phase Asynchronous AHB clock cycle HCLK 1 256 Bust turn Duration of the bus turnaround phase Asynchronousand synchronous read write AHB clock cycle HCLK 0 15 Clock divide ratio Number...

Page 235: ...nable NWE O Write enable NL NADV O Latch enable this signal is called address valid NADV by some NOR Flash devices NWAIT I NOR Flash wait input signal to the FMC Table 50 Non multiplexed I Os PSRAM SRAM FMC signal name I O Function CLK O Clock only for PSRAM synchronous access A 25 0 O Address bus D 15 0 I O Data bidirectional bus NE x O Chip Select x 1 4 called NCE by PSRAM Cellular RAM i e CRAM ...

Page 236: ...ellular RAM i e CRAM NOE O Output enable NWE O Write enable NL NADV O Address valid PSRAM input memory signal name NADV NWAIT I PSRAM wait input signal to the FMC NBL 1 0 O Byte lane output Byte 0 and Byte 1 control upper and lower byte enable Table 51 16 Bit multiplexed I O PSRAM continued FMC signal name I O Function Table 52 NOR Flash PSRAM Example of supported memories and transactions Device ...

Page 237: ...exed I Os Asynchronous R 8 16 Y Asynchronous W 8 16 Y Use of byte lanes NBL 1 0 Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FMC accesses Asynchronous W 32 16 Y Split into 2 FMC accesses Asynchronous page R 16 N Mode is not supported Synchronous R 8 16 N Synchronous R 16 16 Y Synchronous R 32 16 Y Synchronous W 8 16 Y Use of byte lanes NBL 1 0 Synchronous W 16 ...

Page 238: ...e available It is possible to mix A B C and D modes for read and write operations For example read operation can be performed in mode A and write in mode B If the extended mode is disabled EXTMOD bit is reset in the FMC_BCRx register the FMC can operate in Mode1 or Mode2 as follows Mode 1 is the default mode when SRAM PSRAM memory type is selected MTYP 0x0 or 0x01 in the FMC_BCRx register Mode 2 i...

Page 239: ... Bit number Bit name Value to set 31 21 Reserved 0x000 20 CCLKEN As needed 19 CBURSTRW 0x0 no effect in asynchronous mode 18 16 Reserved 0x0 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x0 13 WAITEN 0x0 no effect in asynchronous mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0...

Page 240: ...ATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST 1 HCLK cycles for write accesses DATAST HCLK cycles for read accesses 7 4 ADDHLD Don t care 3 0 ADDSET Duration of the first access phase ADDSET HCLK cycles Minimum value for ADDSET is 0 Table 53 FMC_BCRx bit fields continued Bit number Bit nam...

Page 241: ...gling Figure 33 ModeA read access waveforms 1 NBL 1 0 are driven low during the read access Figure 34 ModeA write access waveforms 3 4 4 34 EMORY TRANSACTION X CYCLES CYCLES 7 DATA DRIVEN BY MEMORY 3 6 IGH Ϯϱ Ϭ EK d d d н ϭͿ DĞŵŽƌLJ ƚƌĂŶƐĂĐƚŝŽŶ E dž ϭϱ Ϭ ĐLJĐůĞƐ ĐLJĐůĞƐ Et E ϭ Ϭ ĚĂƚĂ ĚƌŝǀĞŶ ďLJ D D ϯϰϰϴϬsϭ ϭ ...

Page 242: ...hronous mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don t care 5 4 MWID As needed 3 2 MTYP As needed exclude 0x2 NOR Flash memory 1 MUXEN 0x0 0 MBKEN 0x1 Table 56 FMC_BTRx bit fields Bit number Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x0 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16...

Page 243: ...9 28 ACCMOD 0x0 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST HCLK cycles for write accesses 7 4 ADDHLD Don t care 3 0 ADDSET Duration of the first access phase ADDSET HCLK cycles for write accesses Minimum value for ADDSET is 0 12 6 7 7 67 0HPRU WUDQVDFWLRQ 1 F FOHV F FOHV 1 1 9 GD...

Page 244: ... Figure 37 ModeB write access waveforms The differences with mode1 are the toggling of NWE and the independent read and write timings when extended mode is set Mode B 3 4 4 34 EMORY TRANSACTION X CYCLES CYCLES 7 6 DATA DRIVEN BY MEMORY 3 6 IGH 12 6 7 7 67 0HPRU WUDQVDFWLRQ 1 F FOHV F FOHV 1 1 9 GDWD GULYHQ E 0 06 9 ...

Page 245: ...G Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5 4 MWID As needed 3 2 MTYP 0x2 NOR Flash memory 1 MUXEN 0x0 0 MBKEN 0x1 Table 59 FMC_BTRx bit fields Bit number Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x1 if extended mode is set 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low...

Page 246: ...umber Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x1 if extended mode is set 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the access second phase DATAST HCLK cycles for write accesses 7 4 ADDHLD Don t care 3 0 ADDSET Duration of the access first phase ADDSET HCLK cycles for write accesses Minimum valu...

Page 247: ...ed 0x000 20 CCLKEN As needed 19 CBURSTRW 0x0 no effect in asynchronous mode 18 16 Reserved 0x0 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x1 13 WAITEN 0x0 no effect in asynchronous mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5 4 MWID As needed 3 2 MTYP 0x...

Page 248: ...ADDSET Duration of the first access phase ADDSET HCLK cycles for read accesses Minimum value for ADDSET is 0 Table 63 FMC_BWTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x2 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST HCLK cycles for write accesses 7 ...

Page 249: ...synchronous access with extended address Figure 40 ModeD read access waveforms Figure 41 ModeD write access waveforms 3 4 4 34 EMORY TRANSACTION X CYCLES CYCLES 7 6 DATA DRIVEN BY MEMORY 3 6 IGH CYCLES 12 6 7 7 67 0HPRU WUDQVDFWLRQ 1 F FOHV F FOHV 1 1 9 GDWD GULYHQ E 60 06 9 F FOHV ...

Page 250: ...mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Set according to memory support 5 4 MWID As needed 3 2 MTYP As needed 1 MUXEN 0x0 0 MBKEN 0x1 Table 65 FMC_BTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x3 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time betwee...

Page 251: ...ATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Duration of the second access phase DATAST 1 HCLK cycles for write accesses 7 4 ADDHLD Duration of the middle phase of the write access ADDHLD HCLK cycles 3 0 ADDSET Duration of the first access phase ADDSET HCLK cycles for write accesses Minimum value for ADDSET is 1 3 4 4 34 EMORY TRA...

Page 252: ...N As needed 19 CBURSTRW 0x0 no effect in asynchronous mode 18 16 Reserved 0x0 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x0 13 WAITEN 0x0 no effect in asynchronous mode 12 WREN As needed 11 WAITCFG Don t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5 4 MWID As needed 3 2 MTYP 0x2 NOR Flash memor...

Page 253: ...not WAIT sensitive and so they are not prolonged The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles before the end of the memory transaction The following cases must be considered 1 MUXEN 0x1 0 MBKEN 0x1 Table 68 FMC_BTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x0 27 24 DATLAT Don t care 23 20 CLKDIV Don t care 19 16 BUSTURN Time bet...

Page 254: ...and Figure 45 show the number of HCLK clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory independently of the above cases Figure 44 Asynchronous wait during a read access waveforms 1 NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register DATAST 4 HCLK max_wait_assertion_time max_wait_assertion_time address_phase hold_phase DATAST 4 ...

Page 255: ... specify a minimum time from NADV assertion to CLK high To meet this constraint the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access before NADV assertion This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse Data latency versus NOR memory latency The data latency is the number of cycles to wait...

Page 256: ...AHB transfer is 32 bits and de assert the Chip Select signal when the last data is strobed Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations Nevertheless a random asynchronous access would first require to re program the memory access mode which would altogether last longer Wait management For synchronous NOR Flash memories NWAIT is evaluated aft...

Page 257: ...e static memory controller FSMC RM0365 257 1080 DocID025202 Rev 7 Figure 46 Wait configuration waveforms DGGU GDWD GDWD DGGU 0HPRU WUDQVDFWLRQ EXUVW RI KDOI ZRUGV 1 9 1 7 7 LQVHUWHG ZDLW VWDWH GDWD 1 7 7 DL F ...

Page 258: ...RY TRANSACTION BURST OF HALF WORDS X 7 IGH 6 7 4 7 4 CLOCK CYCLE CLOCK CYCLE 4 4 INSERTED WAIT STATE ATA STROBES AI E CYCLES DATA DATA ATA STROBES Table 69 FMC_BCRx bit fields Bit No Bit name Value to set 31 21 Reserved 0x000 20 CCLKEN As needed 19 CBURSTRW No effect on synchronous read 18 15 Reserved 0x0 14 EXTMOD 0x0 13 WAITEN to be set to 1 if the memory supports this feature to be kept at 0 ot...

Page 259: ... or 0x2 1 MUXEN As needed 0 MBKEN 0x1 Table 70 FMC_BTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x0 27 24 DATLAT Data latency 27 24 DATLAT Data latency 23 20 CLKDIV 0x0 to get CLK HCLK Not supported 0x1 to get CLK 2 HCLK 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Don t care 7 4 ADDHLD Don t care 3 0 ADDSET Don t care Table 69 FMC_BCRx bi...

Page 260: ... Lane NBL outputs are not shown they are held low while NEx is active DDR DATA ADDR EMORY TRANSACTION BURST OF HALF WORDS X 7 I 6 7 4 7 4 CLOCK CLOCK 4 4 INSERTED WAIT STATE AI F CYCLES DATA Table 71 FMC_BCRx bit fields Bit No Bit name Value to set 31 20 Reserved 0x000 20 CCLKEN As needed 19 CBURSTRW 0x1 18 15 Reserved 0x0 14 EXTMOD 0x0 13 WAITEN to be set to 1 if the memory supports this feature ...

Page 261: ...As needed 3 2 MTYP 0x1 1 MUXEN As needed 0 MBKEN 0x1 Table 72 FMC_BTRx bit fields Bit No Bit name Value to set 31 30 Reserved 0x0 29 28 ACCMOD 0x0 27 24 DATLAT Data latency 23 20 CLKDIV 0x0 to get CLK HCLK not supported 0x1 to get CLK 2 HCLK 19 16 BUSTURN Time between NEx high to NEx low BUSTURN HCLK 15 8 DATAST Don t care 7 4 ADDHLD Don t care 3 0 ADDSET Don t care Table 71 FMC_BCRx bit fields co...

Page 262: ...K clock is activated when the CCLKEN is set Note The CCLKEN bit of the FMC_BCR2 4 registers is don t care It is only enabled through the FMC_BCR1 register Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock Note If CCLKEN bit is set the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register CLKDIV in FMC_BWTR1 is don t care Note If the synchron...

Page 263: ...iming configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state 0 NWAIT signal is active one data cycle before wait state default after reset 1 NWAIT signal is ...

Page 264: ...se Bits 3 2 MTYP Memory type Defines the type of external memory attached to the corresponding memory bank 00 SRAM default after reset for Bank 2 4 01 PSRAM CRAM 10 NOR Flash OneNAND Flash default after reset for Bank 1 11 reserved Bit 1 MUXEN Address data multiplexing enable bit When this bit is set the address and data values are multiplexed on the data bus valid only with NOR and PSRAM memories...

Page 265: ... 2 to issue to the memory before reading writing the first data This timing parameter is not expressed in HCLK periods but in FMC_CLK periods For asynchronous access this value is don t care 0000 Data latency of 2 CLK clock cycles for first burst access 1111 Data latency of 17 CLK clock cycles for first burst access default value after reset Bits 23 20 CLKDIV Clock divide ratio for FMC_CLK signal ...

Page 266: ...des muxed and D There is a bus turnaround delay of 1 FMC clock cycle between Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for modes muxed and D An asynchronous modes 1 2 A B or C read and a read from another static bank There is a bus tur...

Page 267: ...re 31 to Figure 43 Example Mode1 write access DATAST 1 Data phase duration DATAST 1 2 HCLK clock cycles Note In synchronous accesses this value is don t care Bits 7 4 ADDHLD Address hold phase duration These bits are written by software to define the duration of the address hold phase refer to Figure 31 to Figure 43 used in mode D or multiplexed accesses 0000 Reserved 0001 ADDHLD phase duration 1 ...

Page 268: ...USTURN Bus turnaround phase duration The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous synchronous read or write transfer to or from a static bank The bank can be the same or different in case of read in case of write the bank can be different expect for muxed or mode D In some cases whatever the programmed BUSTRUN values the bus turn...

Page 269: ...on 2 HCLK clock cycles 1111 1111 DATAST phase duration 255 HCLK clock cycles default value after reset Bits 7 4 ADDHLD Address hold phase duration These bits are written by software to define the duration of the address hold phase refer to Figure 31 to Figure 43 used in asynchronous multiplexed accesses 0000 Reserved 0001 ADDHLD phase duration 1 HCLK clock cycle 0010 ADDHLD phase duration 2 HCLK c...

Page 270: ...5 Memory wait Minimum duration in HCLK clock cycles of the command assertion Read Write AHB clock cycle HCLK 2 256 Memory hold Number of clock cycles HCLK during which the address must be held as well as the data if a write access is performed after the command de assertion Read Write AHB clock cycle HCLK 1 254 Memory databus high Z Number of clock cycles HCLK during which the data bus is kept in ...

Page 271: ...the FMC Table 76 16 bit PC Card FMC signal name I O Function A 10 0 O Address bus NIORD O Output enable for I O space NIOWR O Write enable for I O space NREG O Register signal indicating if access is in Common or Attribute space D 15 0 I O Bidirectional databus NCE4_1 O Chip Select 1 NCE4_2 O Chip Select 2 indicates if access is 16 bit or 8 bit NOE O Output enable in Common and in Attribute space ...

Page 272: ...d to define number of HCLK cycles for the three phases of any PC Card CompactFlash or NAND Flash access plus one parameter that defines the timing for starting driving the data bus when a write access is performed Figure 49 shows the timing parameter definitions for common memory accesses knowing that Attribute and I O only for PC Card memory space access timings are similar Table 77 Supported mem...

Page 273: ...a bus width of the NAND Flash PTYP 1 PWAITEN 0 or 1 as needed see section Section 14 4 2 NAND Flash memory PC Card address mapping for timing configuration 4 The CPU performs a byte write to the common memory space with data byte equal to one Flash command byte for example 0x00 for Samsung NAND Flash devices The LE input of the NAND Flash memory is active during the write strobe low pulse on NWE t...

Page 274: ...n described in step 5 a new random address can be accessed by restarting the operation at step 3 a new command can be sent to the NAND Flash device by restarting at step 2 14 6 5 NAND Flash prewait functionality Some NAND Flash devices require that after writing the last part of the address the controller waits for the R NB signal to go low see Figure 50 Figure 50 Access to non CE don t care NAND ...

Page 275: ... ECC blocks are identical and associated with Bank 2 and Bank 3 As a consequence no hardware ECC computation is available for memories connected to Bank 4 The ECC algorithm implemented in the FMC can perform 1 bit error correction and 2 bit error detection per 256 512 1 024 2 048 4 096 or 8 192 bytes read or written from to the NAND Flash memory It is based on the Hamming coding algorithm and cons...

Page 276: ...rformed nCE2 accesses the odd byte on D15 8 and nCE1 accesses the even byte on D7 0 if A0 0 or the odd byte on D7 0 if A0 1 The full word is accessed on D15 0 if both nCE2 and nCE1 are low The memory space is selected by asserting low nOE for read accesses or nWE for write accesses combined with the low assertion of nCE2 nCE1 and nREG If pin nREG 1 during the memory access the common memory space ...

Page 277: ... nCE2 nCE1 nREG nOE nWE nIORD nIOWR A10 A9 A7 1 A0 Space Access type Allowed not Allowed 1 0 1 0 1 X X X X X Common Memory Space Read Write byte on D7 D0 YES 0 1 1 0 1 X X X X X Read Write byte on D15 D8 Not supported 0 0 1 0 1 X X X X 0 Read Write word on D15 D0 YES X 0 0 0 1 0 1 X X 0 Attribute Space Read or Write Configuration Registers YES X 0 0 0 1 0 0 X X 0 Read or Write CIS Card Information...

Page 278: ...WAITEN Res rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 20 Reserved must be kept at reset value Bits 19 17 ECCPS ECC page size Defines the page size for the extended ECC 000 256 bytes 001 512 bytes 010 1024 bytes 011 2048 bytes 100 4096 bytes 101 8192 bytes Bits 16 13 TAR ALE to RE delay Sets time from ALE low to RE low in number of AHB clock cycles HCLK Time is t_ar TAR SET 2 THCLK ...

Page 279: ...1 reserved do not use Bit 3 PTYP Memory type Defines the type of device attached to the corresponding memory bank 0 PC Card CompactFlash CF or PCMCIA 1 NAND Flash default after reset Bit 2 PBKEN PC Card NAND Flash memory bank enable bit Enables the memory bank Accessing a disabled memory bank causes an ERROR on AHB bus 0 Corresponding memory bank is disabled default after reset 1 Corresponding mem...

Page 280: ...ion request disabled 1 Interrupt high level detection request enabled Bit 3 IREN Interrupt rising edge detection enable bit 0 Interrupt rising edge detection request disabled 1 Interrupt rising edge detection request enabled Bit 2 IFS Interrupt falling edge status The flag is set by hardware and reset by software 0 No interrupt falling edge occurred 1 Interrupt falling edge occurred Note If this b...

Page 281: ...d and data for write accesses after the command is deasserted NWE NOE for NAND Flash read or write access to common memory space on socket x 0000 0000 reserved 0000 0001 1 HCLK cycle for write access 3 HCLK cycles for read access 1111 1110 254 HCLK cycles for write access 256 HCLK cycles for read access 1111 1111 Reserved Bits 15 8 MEMWAITx Common memory x wait time Defines the minimum number of H...

Page 282: ... HCLK cycle for write access 3 HCLK cycles for read access 1111 1110 254 HCLK cycles for write access 256 HCLK cycles for read access 1111 1111 Reserved Bits 15 8 ATTWAIT Attribute memory x wait time Defines the minimum number of HCLK 1 clock cycles to assert the command NWE NOE for PC Card NAND Flash read or write access to attribute memory space on socket x The duration for command assertion is ...

Page 283: ...served 0000 0001 1 HCLK cycle 1111 1111 255 HCLK cycles Bits 15 8 IOWAITx I O x wait time Defines the minimum number of HCLK 1 clock cycles to assert the command SMNWE SMNOE for PC Card read or write access to I O space on socket x The duration for command assertion is extended if the wait signal NWAIT is active low at the end of the programmed value of HCLK 0000 0000 reserved do not use this valu...

Page 284: ...ding to the ECCPS field in the FMC_PCRx registers the CPU must read the computed ECC value from the FMC_ECCx registers It then verifies if these computed parity data are the same as the parity value recorded in the spare area to determine whether a page is valid and to correct it otherwise The FMC_ECCRx registers should be cleared after being read by setting the ECCEN bit to 0 To compute a new dat...

Page 285: ...ET 0x14 FMC_BTR3 Res Res ACCM OD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x1C FMC_BTR4 Res Res ACCM OD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x104 FMC_BWTR1 Res Res ACCM OD Res Res Res Res Res Res Res Res Res Res Res Res DATAST ADDHLD ADDSET 0x10C FMC_BWTR2 Res Res ACCM OD Res Res Res Res Res Res Res Res Res Res Res Res DATAST ADDHLD ADDSET 0x114 FMC_BWTR3 Res Res ACCM OD Res Res Res Res R...

Page 286: ...Zx MEMHOLDx MEMWAITx MEMSETx 0x6C FMC_PATT2 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 0x8C FMC_PATT3 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 0xAC FMC_PATT4 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 0xB0 FMC_PIO4 IOHIZx IOHOLDx IOWAITx IOSETx 0x74 FMC_ECCR2 ECCx 0x94 FMC_ECCR3 ECCx Table 80 FMC register map continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 287: ...channels A D conversion of the various channels can be performed in single continuous scan or discontinuous mode The result of the ADC is stored in a left aligned or right aligned 16 bit data register The ADCs are mapped on the AHB bus to allow fast data handling The analog watchdog features allow the application to detect if the input voltage goes outside the user defined high or low thresholds A...

Page 288: ...rammable sampling time Up to four injected channels analog inputs assignment to regular or injected channels is fully configurable Hardware assistant to prepare the context of the injected channels to allow fast context switching Data alignment with in built data coherency Data can be managed by GP DMA for regular channel conversions 4 dedicated data registers for the injected channels Low power f...

Page 289: ...injected end of sequence conversion regular or injected analog watchdog 1 2 or 3 or overrun events 3 analog watchdogs per ADC ADC supply requirements 1 80 V to 3 6 V ADC input range VREF VIN VREF Figure 51 shows the block diagram of one ADC Table 82 ADC internal channels summary Product ADC1 ADC2 Total of internal ADC channels STM32F302xB C D E 1 channel connected to temperature sensor 1 channel c...

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Page 291: ...ence voltage output from internal operational amplifier 2 VTS Input Output voltage from internal temperature sensor VREFINT Input Output voltage from internal reference voltage VBAT Input supply External battery voltage supply Table 84 ADC pins Name Signal type Comments VREF Input analog reference positive The higher positive reference voltage for the ADC 1 8 V VREF VDDA VDDA Input analog supply A...

Page 292: ...cheme bits CKMODE 1 0 of the ADCx_CCR register must be different from 00 Note Software can use option b by writing CKMODE 1 0 01 only if the AHB prescaler of the RCC is set to 1 the duty cycle of the AHB clock must be 50 in this configuration Option a has the advantage of reaching the maximum ADC clock frequency whatever the AHB clock scheme selected The ADC clock can eventually be divided by the ...

Page 293: ...etween the ADC clock and the AHB clock except if some injected channels are programmed In this case it is mandatory to respect the following ratio FHCLK FADC 4 if the resolution of all channels are 12 bit or 10 bit FHCLK FADC 3 if there are some channels with resolutions equal to 8 bit and none with lower resolutions FHCLK FADC 2 if there are some channels with resolutions equal to 6 bit ...

Page 294: ...VORZ FKDQQHO VORZ FKDQQHO VORZ FKDQQHO VORZ FKDQQHO B 1 B 1 B 1 B 1 B 1 B 1 B 1 UHVHUYHG VORZ FKDQQHO VORZ FKDQQHO VORZ FKDQQHO 06Y 9 95 95 KDQQHO 6HOHFWLRQ KDQQHO 6HOHFWLRQ 6LQJOH HQGHG 0RGH 9 11 9 13 9 11 9 13 95 95 95 95 95 95 95 95 6LQJOH HQGHG 0RGH 923 03 95 17 95 17 9 7 976 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13 9 11 9 13...

Page 295: ...power supply After ADC operations are complete the ADC is disabled ADEN 0 It is possible to save power by disabling the ADC voltage regulator refer to the ADC voltage regulator disable sequence Note When the internal voltage regulator is disabled the internal analog calibration is kept ADVREG enable sequence To enable the ADC voltage regulator perform the sequence below 1 Change ADVREGEN 1 0 bits ...

Page 296: ... During the calibration procedure the application must not use the ADC and must wait until calibration is complete Calibration is preliminary to any ADC operation It removes the offset error which may vary from chip to chip due to process or bandgap variation The calibration factor to be applied for single ended input conversions is different from the factor to be applied for differential input co...

Page 297: ...d 2 Ensure that ADEN 0 3 Select the input mode for this calibration by setting ADCALDIF 0 Single ended input or ADCALDIF 1 Differential input 4 Set ADCAL 1 5 Wait until ADCAL 0 6 The calibration factor can be read from ADCx_CALFACT register Figure 54 ADC calibration Software procedure to re inject a calibration factor into the ADC 1 Ensure ADEN 1 and ADSTART 0 and JADSTART 0 ADC enabled and no con...

Page 298: ...odes with ADCALDIF 1 This updates the register CALFACT_D 6 0 4 Enable the ADC configure the channels and launch the conversions Each time there is a switch from a single ended to a differential inputs channel and vice versa the calibration will automatically be injected into the analog ADC Figure 56 Mixing single ended and differential channels 5 7 B 7 VWDWH 7B6 QWHUQDO FDOLEUDWLRQ IDFWRU 6WDUW FR...

Page 299: ... when an external trigger event occurs if triggers are enabled Injected conversions start by setting JADSTART 1 or when an external injected trigger event occurs if injected triggers are enabled Software procedure to enable the ADC 1 Set ADEN 1 2 Wait until ADRDY 1 ADRDY is set after the ADC startup time This can be done using the associated interrupt setting ADRDYIE 1 Note ADEN bit cannot be set ...

Page 300: ...st be equal to 0 The software is allowed to write the control bits ADSTP or JADSTP of the ADCx_CR register only if the ADC is enabled and eventually converting and if there is no pending request to disable the ADC ADSTART or JADSTART must be equal to 1 and ADDIS to 0 The software can write the register ADCx_JSQR at any time when the ADC is enabled ADEN 1 Note There is no hardware protection to pre...

Page 301: ... be first stopped by writing ADSTP 1 refer to Section 15 3 17 Stopping an ongoing conversion ADSTP JADSTP It is possible to modify the ADCx_JSQR registers on the fly while injected conversions are occurring Refer to Section 15 3 21 Queue of context for injected conversions 15 3 12 Channel wise programmable sampling time SMPR1 SMPR2 Before starting a conversion the ADC must establish a direct conne...

Page 302: ...The JEOC end of injected conversion flag is set An interrupt is generated if the JEOCIE bit is set After the regular sequence is complete The EOS end of regular sequence flag is set An interrupt is generated if the EOSIE bit is set After the injected sequence is complete The JEOS end of injected sequence flag is set An interrupt is generated if the JEOSIE bit is set Then the ADC stops until a new ...

Page 303: ...1 When JADSTART is set the conversion starts Immediately if JEXTEN 0x0 software trigger At the next active edge of the selected injected hardware trigger if JEXTEN 0x0 Note In auto injection mode JAUTO 1 use ADSTART bit to start the regular conversions followed by the auto injected conversions JADSTART must be kept cleared ADSTART and JADSTART also provide information on whether any ADC operation ...

Page 304: ...and injected conversions ongoing by setting JADSTP 1 Stopping conversions will reset the ongoing ADC operation Then the ADC can be reconfigured ex changing the channel selection or the trigger ready for a new operation Note that it is possible to stop injected conversions while regular conversions are still operating and vice versa This allows for instance re configuration of the injected conversi...

Page 305: ...in case of regular conversion or JADSTP JADSTART in case of injected conversion are cleared by hardware and the software must wait until ADSTART 0 or JADSTART 0 before starting a new conversion Note In auto injection mode JAUTO 1 setting ADSTP bit aborts both regular and injected conversions JADSTP must not be used Figure 59 Stopping ongoing regular conversions 06 9 7ULJJHU VWDWH 5 RQYHUW K 1 5 5 ...

Page 306: ...RT 0 any regular hardware triggers which occur are ignored If bit JADSTART 0 any injected hardware triggers which occur are ignored Table 85 provides the correspondence between the EXTEN 1 0 and JEXTEN 1 0 values and the trigger polarity 3AMPLE H 2 9 2 4 2 9 340 34 24 2 5 2 6 23 3 ONGOING ONVERT H 2EGULAR TRIGGER 3AMPLE H NJECTED TRIGGER 4 2 9 SOFTWARE IS NOT ALLOWED TO CONFIGURE REGULAR CONVERSIO...

Page 307: ...tion can be anticipated and changed on the fly Refer to Section 15 3 21 Queue of context for injected conversions on page 311 Each ADC master shares the same input triggers with its ADC slave as described in Figure 61 Figure 61 Triggers are shared between ADC master ADC slave Table 86 Configuring the trigger polarity for injected external triggers JEXTEN 1 0 Source 00 Hardware Trigger with detecti...

Page 308: ...M2_TRGO event Internal signal from on chip timers 1011 EXT12 TIM4_TRGO event Internal signal from on chip timers 1100 EXT13 TIM6_TRGO event Internal signal from on chip timers 1101 EXT14 TIM15_TRGO event Internal signal from on chip timers 1110 EXT15 TIM3_CC4 event Internal signal from on chip timers 1111 Table 88 ADC1 ADC2 External trigger for injected channels Name Source Type JEXTSEL 3 0 JEXT0 ...

Page 309: ... interval between triggers must be 29 ADC clock cycles Auto injection mode If the JAUTO bit in the ADCx_CFGR register is set then the channels in the injected group are automatically converted after the regular group of channels This can be used to convert a sequence of up to 20 conversions programmed in the ADCx_SQR and ADCx_JSQR registers In this mode the ADSTART bit in the ADCx_CR register must...

Page 310: ...ersions in the sequence are done The total sequence length is defined by the L 3 0 bits in the ADCx_SQR1 register Example DISCEN 1 n 3 channels to be converted 1 2 3 6 7 8 9 10 11 1st trigger channels converted are 1 2 3 an EOC event is generated at each conversion 2nd trigger channels converted are 6 7 8 an EOC event is generated at each conversion 3rd trigger channels converted are 9 10 11 an EO...

Page 311: ...elected in the ADCx_JSQR registers until all the conversions in the sequence are done The total sequence length is defined by the JL 1 0 bits in the ADCx_JSQR register Example JDISCEN 1 channels to be converted 1 2 3 1st trigger channel 1 converted a JEOC event is generated 2nd trigger channel 2 converted a JEOC event is generated 3rd trigger channel 3 converted and a JEOC event a JEOS event are g...

Page 312: ...un operations the Queue always maintains the last active context and any further valid start of injected sequence will be served according to the last active context If JQM 1 the Queue can be empty after the end of an injected sequence or if the Queue is flushed When this occurs there is no more context in the queue and both injected software and hardware triggers are disabled Therefore any furthe...

Page 313: ...ware trigger 1 P3 sequence of 4 conversions hardware trigger 1 Figure 64 Example of JSQR queue of context trigger change 1 Parameters P1 sequence of 2 conversions hardware trigger 1 P2 sequence of 1 conversion hardware trigger 2 P3 sequence of 4 conversions hardware trigger 1 06 9 3 3 3 037 RQYHUVLRQ RQYHUVLRQ RQYHUVLRQ 3 3 3 3 3 3 3 3 3 3 037 5 5 5 RQYHUVLRQ 645 TXHXH ULWH 645 7ULJJHU VWDWH FRQWH...

Page 314: ... sequence of 4 conversions hardware trigger 1 Figure 66 Example of JSQR queue of context with overflow during conversion 1 Parameters P1 sequence of 2 conversions hardware trigger 1 P2 sequence of 1 conversion hardware trigger 2 P3 sequence of 3 conversions hardware trigger 1 P4 sequence of 4 conversions hardware trigger 1 06 9 645 TXHXH ULWH 645 3 3 037 7ULJJHU VWDWH RQYHUVLRQ 5 RQYHUVLRQ 5 3 429...

Page 315: ...er 1 Note When writing P3 the context changes immediately However because of internal resynchronization there is a latency and if a trigger occurs just after or before writing P3 it can happen that the conversion is launched considering the context P2 To avoid this situation the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately Figure 68 Ex...

Page 316: ...TP 1 JQM 0 Case when JADSTP occurs during an ongoing conversion and a new trigger occurs 1 Parameters P1 sequence of 1 conversion hardware trigger 1 P2 sequence of 1 conversion hardware trigger 1 P3 sequence of 1 conversion hardware trigger 1 06 9 645 TXHXH ULWH 645 3 3 3 037 7ULJJHU VWDWH 5 673 3 3 3 3 3 5 3 037 673 3 5 4XHXH LV IOXVKHG DQG PDLQWDLQV WKH ODVW DFWLYH FRQWH W 3 LV ORVW 67 57 FRQWH ...

Page 317: ...M 1 1 Parameters P1 sequence of 1 conversion hardware trigger 1 P2 sequence of 1 conversion hardware trigger 1 P3 sequence of 1 conversion hardware trigger 1 06 9 645 TXHXH ULWH 645 3 3 3 037 7ULJJHU VWDWH 5 673 3 3 3 3 3 5 3 037 673 3 5 WKH ODVW DFWLYH FRQWH W 3 LV ORVW 67 57 FRQWH W UHWXUQHG E UHDGLQJ 645 6HW E 6 5HVHW E RQYHUVLRQ 5HVHW E 6HW E 6 312 QUEUE 7RITE 312 0 0 0 049 4RIGGER STATE 2 9 3...

Page 318: ...er to software injected trigger it is necessary to stop the injected conversions by setting JADSTP 1 after the last hardware triggered conversions This is necessary to re enable the software trigger a rising edge on JADSTART is necessary to start a software injected conversion Refer to Figure 75 When changing the context from software trigger to hardware injected trigger after the last software tr...

Page 319: ... 7 Set JADSTP 8 Wait until JADSTART is reset 9 Set JADSTART 15 3 22 Programmable resolution RES fast conversion mode It is possible to perform faster conversion by reducing the ADC resolution The resolution can be configured to be either 12 10 8 or 6 bits by programming the control bits RES 1 0 Figure 80 Figure 81 Figure 82 and Figure 83 show the conversion result format with respect to the resolu...

Page 320: ... by writing 1 to it An interrupt can be generated if bit EOSMPIE is set 15 3 24 End of conversion sequence EOS JEOS The ADC notifies the application for each end of regular sequence EOS and for each end of injected sequence JEOS event The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is available in the ADCx_DR register An interrupt can be generated if bit EOSIE...

Page 321: ...6 Single conversions of a sequence software trigger 1 EXTEN 0x0 CONT 0 2 Channels selected 1 9 10 17 AUTDLY 0 Figure 77 Continuous conversion of a sequence software trigger 1 EXTEN 0x0 CONT 1 2 Channels selected 1 9 10 17 AUTDLY 0 5 67 57 2 26 VWDWH E V Z E K Z 5 5 B 5 06 9 QGLFDWLYH WLPLQJV 67 57 2 26 673 VWDWH B 5 3 6 5 673 5 E V Z E K Z QGLFDWLYH WLPLQJV ...

Page 322: ...t At the end of each regular conversion channel when EOC event occurs the result of the converted data is stored into the ADCx_DR data register which is 16 bits wide At the end of each injected conversion channel when JEOC event occurs the result of the converted data is stored into the corresponding ADCx_JDRy data register which is 16 bits wide The ALIGN bit in the ADCx_CFGR register selects the ...

Page 323: ... the possible resolutions for analog watchdog 1 When reading data from ADCx_DR regular channel or from ADCx_JDRy injected channel y 1 2 3 4 corresponding to the channel i If one of the offsets is enabled bit OFFSETy_EN 1 for the corresponding channel the read data is signed If none of the four offsets is enabled for this channel the read data is not signed Figure 80 Figure 81 Figure 82 and Figure ...

Page 324: ...81 Right alignment offset enabled signed value ELW GDWD ELW GDWD ELW GDWD ELW GDWD ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW 06 9 6 7 6 7 6 7 6 7 ELW GDWD ELW GDWD 6 7 6 7 6 7 6 7 6 7 6 7 ELW GDWD ELW GDWD ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW 06 9 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 ...

Page 325: ...isabled unsigned value Figure 83 Left alignment offset enabled signed value ELW GDWD ELW GDWD ELW GDWD ELW GDWD ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW 06 9 ELW GDWD ELW GDWD ELW GDWD ELW GDWD ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW ELW 06 9 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 ...

Page 326: ...ersion is discarded and lost If OVR remains at 1 any further conversions will occur but the result data will be also discarded OVRMOD 1 The data register is overwritten with the last conversion result and the previous unread data is lost If OVR remains at 1 any further conversions will operate normally and the ADCx_DR register will always contain the latest converted data Figure 84 Example of over...

Page 327: ...new conversion is not transferred by the DMA Which means that all the data transferred to the RAM can be considered as valid Depending on the configuration of OVRMOD bit the data is either preserved or overwritten refer to Section ADC overrun OVR OVRMOD The DMA transfer requests are blocked until the software clears the OVR bit Two different DMA modes are proposed depending on the application use ...

Page 328: ...nce of injected conversions whatever JDISCEN 0 or 1 Note There is no delay inserted between each conversions of the injected sequence except after the last one During a conversion a hardware trigger event for the same group of conversions occurring during this delay is ignored Note This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTAR...

Page 329: ...It is however considered pending if it occurs after this delay even if it occurs during an injected sequence of the delay that follows it The conversion then starts at the end of the delay of the injected sequence In AUTDLY mode a hardware injected trigger event is ignored if it occurs during an already ongoing injected sequence or during the delay that follows the last injected conversion of the ...

Page 330: ... 1 2 Regular configuration EXTEN 0x1 HW trigger CONT 0 DISCEN 0 CHANNELS 1 2 3 3 Injected configuration JEXTEN 0x1 HW Trigger JDISCEN 0 CHANNELS 5 6 06 9 QMHFWHG WULJJHU UHJXODU 26 B 5 B 5 5HJXODU WULJJHU LQMHFWHG UHJXODU UHJXODU LQM 1RW LJQRUHG RFFXUV GXULQJ LQMHFWHG VHTXHQFH JQRUHG UHJXODU JQRUHG B 5 2 26 B 5 UHDG DFFHVV E V Z E K Z QGLFDWLYH WLPLQJV 5 LQMHFWHG UHJXODU VWDWH ...

Page 331: ...figuration EXTEN 0x1 HW trigger CONT 0 DISCEN 1 DISCNUM 1 CHANNELS 1 2 3 3 Injected configuration JEXTEN 0x1 HW Trigger JDISCEN 1 CHANNELS 5 6 JQRUHG JQRUHG 06 9 QMHFWHG WULJJHU UHJXODU 26 B 5 B 5 5HJXODU WULJJHU LQMHFWHG UHJXODU UHJXODU LQM 1RW LJQRUHG RFFXUV GXULQJ LQMHFWHG VHTXHQFH JQRUHG UHJXODU B 5 2 26 VWDWH B 5 UHDG DFFHVV E V Z E K Z QGLFDWLYH WLPLQJV 5 5 5 5 UHJXODU LQMHFWHG 5 5 ...

Page 332: ...e JAUTO 1 1 AUTDLY 1 2 Regular configuration EXTEN 0x0 SW trigger CONT 1 DISCEN 0 CHANNELS 1 2 3 Injected configuration JAUTO 1 CHANNELS 5 6 ŐŶŽƌĞĚ ŶũĞĐƚĞĚ ƚƌŝŐŐĞƌ ƌĞŐƵůĂƌ K ͺ Zϭ ͺ ZϮ ŝŶũĞĐƚĞĚ ƌĞŐƵůĂƌ z ϭͿ z ϮͿ z ŝŶũͿ ƌĞŐƵůĂƌ ͺ Z K K ƐƚĂƚĞ ͺ Z ƌĞĂĚ ĂĐĐĞƐƐ ďLJ Ɛ ǁ ďLJ Ś ǁ ŶĚŝĐĂƚŝǀĞ ƚŝŵŝŶŐƐ Z z ϭ z ϱ Ϯ z ϲ z z ϭ ϯ ϭ Ϯ ϯ ϲ ϱ ƌĞŐƵůĂƌ ŝŶũĞĐƚĞĚ z ϯͿ D ϯϭϬϮϯsϮ d Zd ϭͿ ƌĞŐƵůĂƌ K ͺ Zϭ ͺ ZϮ ŝŶũĞĐƚĞĚ ƌĞŐƵůĂƌ z...

Page 333: ... This watchdog monitors whether either one selected channel or all enabled channels 1 remain within a configured voltage range window Table 91 shows how the ADCx_CFGR registers should be configured to enable the analog watchdog on one or more channels The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold Table 9...

Page 334: ...he comparison is performed for all the possible resolutions Table 92 Analog watchdog 1 comparison Resolution bit RES 1 0 Analog watchdog comparison between Comments Raw converted data left aligned 1 1 The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets the data which is compared is not signed Thresholds 00 12 bit DATA 11 0...

Page 335: ... the programmed thresholds ADCy_AWDx_OUT is also reset when disabling the ADC when setting ADDIS 1 Note that stopping regular or injected conversions setting ADSTP 1 or JADSTP 1 has no influence on the generation of ADCy_AWDx_OUT Note AWDx flag is set by hardware and reset by software AWDx flag has no influence on the generation of ADCy_AWDx_OUT ex ADCy_AWDx_OUT can toggle while AWDx flag remains ...

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Page 337: ... bits in the slave ADC are always equal to the corresponding bits of the master ADC To start a conversion in dual mode the user must program the bits EXTEN EXTSEL JEXTEN JEXTSEL of the master ADC only to configure a software or hardware trigger and a regular or injected trigger the bits EXTEN 1 0 and JEXTEN 1 0 of the slave ADC are don t care In regular simultaneous or interleaved modes once the u...

Page 338: ...ster ADCx_CDR contains both the master and slave ADC regular converted data 06Y 9 5HJXODU GDWD UHJLVWHU ELWV QMHFWHG GDWD UHJLVWHUV ELWV QMHFWHG FKDQQHOV 5HJXODU FKDQQHOV 5HJXODU GDWD UHJLVWHU ELWV QMHFWHG GDWD UHJLVWHUV ELWV QMHFWHG FKDQQHOV 5HJXODU FKDQQHOV GGUHVV GDWD EXV 3 2 SRUWV B 1 B 1 B 1 XDO PRGH FRQWURO 0DVWHU 6ODYH 6WDUW WULJJHU PX UHJXODU JURXS 6WDUW WULJJHU PX LQMHFWHG JURXS 95 17 9 7...

Page 339: ...nerated if enabled At the end of injected sequence of conversion event JEOS on the slave ADC the converted data is stored into the slave ADCx_JDRy registers and a JEOS interrupt is generated if enabled If the duration of the master injected sequence is equal to the duration of the slave injected one like in Figure 96 it is possible for the software to enable only one of the two JEOS interrupt ex m...

Page 340: ...nterrupt is generated if EOCIE is enabled and software can read the ADCx_DR of the master ADC At the end of each conversion event EOC on the slave ADC a slave EOC interrupt is generated if EOCIE is enabled and software can read the ADCx_DR of the slave ADC If the duration of the master regular sequence is equal to the duration of the slave one like in Figure 97 it is possible for the software to e...

Page 341: ...AUTDLY mode assuming that multi DMA mode is used bits MDMA must be set to 0b10 or 0b11 When regular simultaneous mode is combined with AUTDLY mode it is mandatory for the user to ensure that The number of conversions in the master s sequence is equal to the number of conversions in the slave s For each simultaneous conversions of the sequence the length of the conversion of the slave ADC is inferi...

Page 342: ... ADC a slave EOC interrupt is generated if EOCIE is enabled and software can read the ADCx_DR of the slave ADC Note It is possible to enable only the EOC interrupt of the slave and read the common data register ADCx_CDR But in this case the user must ensure that the duration of the conversions are compatible to ensure that inside the sequence a master conversion is always followed by a slave conve...

Page 343: ...ence require a regular trigger event to occur In this mode injected conversions are supported When injection is done either on master or on slave both the master and the slave regular conversions are aborted and the sequence is re started from the master see Figure 100 below 3 6 0 67 5 7ULJJHU 6DPSOLQJ RQYHUVLRQ F FOHV F FOHV 6 9 QG RI FRQYHUVLRQ RQ VODYH QG RI FRQYHUVLRQ RQ PDVWHU 06 9 0 67 5 7UL...

Page 344: ...converted 2 When the 2nd trigger occurs all injected slave ADC channels in the group are converted 3 And so on A JEOS interrupt if enabled is generated after all injected channels of the master ADC in the group have been converted A JEOS interrupt if enabled is generated after all injected channels of the slave ADC in the group have been converted JEOC interrupts if enabled can also be generated a...

Page 345: ...bled for both master and slave ADCs When the 1st trigger occurs the first injected channel of the master ADC is converted When the 2nd trigger occurs the first injected channel of the slave ADC is converted And so on A JEOS interrupt if enabled is generated after all injected channels of the master ADC in the group have been converted A JEOS interrupt if enabled is generated after all injected cha...

Page 346: ...conversion of a regular group to start the alternate trigger conversion of an injected group Figure 103 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion The injected alternate conversion is immediately started after the injected event If a regular conversion is already running in order to ensure synchronization after the injected conversion the regular conv...

Page 347: ...gger is served Figure 104 shows the behavior in this case note that the 6th trigger is ignored because the associated alternate conversion is not complete Figure 104 Case of trigger occurring during injected conversion 0 67 5 UHJ 0 67 5 LQM 6 9 UHJ 6 9 LQM VW WULJJHU QG WULJJHU V QFKUR QRW ORVW DL 9 P 0 67 5 UHJ 0 67 5 LQM 6 9 UHJ 6 9 LQM VW WULJJHU QG WULJJHU DL 9 WK WULJJHU UG WULJJHU WK WULJJHU...

Page 348: ...ster and slave EOC events have occurred At that time two data items are available and the 32 bit register ADCx_CDR contains the two half words representing two ADC converted data items The slave ADC data take the upper half word and the master ADC data take the lower half word This mode is used in interleaved mode and in regular simultaneous mode when resolution is 10 bit or 12 bit Example Interle...

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Page 350: ...of this ADC contains valid data DMA one shot mode DMA circular mode when MDMA mode is selected When MDMA mode is selected 0b10 or 0b11 bit DMACFG of the ADCx_CCR register must also be configured to select between DMA one shot mode and circular mode as explained in section Section Managing conversions using the DMA bits DMACFG of master and slave ADCx_CFGR are not relevant Stopping the conversions ...

Page 351: ...rted temperature range 40 to 125 C Precision 2 C The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor s output voltage to a digital value Refer to the electrical characteristics section of STM32F302xx datasheet for the sampling time value to be applied when converting the internal temperature sensor When not in use the sensor can be put ...

Page 352: ...after waking from power down mode before it can output VTS at the correct level The ADC also has a startup time after power on so to minimize the delay the ADEN and TSEN bits should be set at the same time 15 3 31 VBAT supply monitoring The VBATEN bit in the ADC12_CCR register is used to switch to the battery voltage As the VBAT voltage could be higher than VDDA to ensure the correct operation of ...

Page 353: ...ference is internally connected to the input channel 18 of the two ADCs ADCx_IN18 Refer to the electrical characteristics section of the STM32F302xx datasheet for the sampling time value to be applied when converting the internal voltage reference voltage Figure 109 shows the block diagram of the VREFINT sensing feature Figure 110 VREFINT channel block diagram Note The VREFEN bit into ADC12_CCR re...

Page 354: ...cation use cases it is necessary to convert this ratio into a voltage independent of VDDA For applications where VDDA is known and ADC converted values are right aligned user can use the following formula to get this absolute value For applications where VDDA value is not known user must use the internal voltage reference and VDDA can be replaced by the expression provided in the section Calculati...

Page 355: ...g EOSMP When the data overrun occurs flag OVR When the injected sequence context queue overflows flag JQOVF Separate interrupt enable bits are available for flexibility Table 94 ADC interrupts per each ADC Interrupt event Event flag Enable control bit ADC ready ADRDY ADRDYIE End of conversion of a regular group EOC EOCIE End of sequence of conversions of a regular group EOS EOSIE End of conversion...

Page 356: ...nverted voltage crosses the values programmed in the fields LT3 7 0 and HT3 7 0 of ADCx_TR3 register It is cleared by software writing 1 to it 0 No analog watchdog 3 event occurred or the flag event was already acknowledged and cleared by software 1 Analog watchdog 3 event occurred Bit 8 AWD2 Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programme...

Page 357: ...g 1 to it 0 Regular Conversions sequence not complete or the flag event was already acknowledged and cleared by software 1 Regular Conversions sequence complete Bit 2 EOC End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADCx_DR register It is cleared by software writing 1 to it or by reading the ADCx_DR regist...

Page 358: ...rupt 0 Analog watchdog 3 interrupt disabled 1 Analog watchdog 3 interrupt enabled Note Software is allowed to write this bit only when ADSTART 0 and JADSTART 0 which ensures that no conversion is ongoing Bit 8 AWD2IE Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable disable the analog watchdog 2 interrupt 0 Analog watchdog 2 interrupt disabled 1 Analog watchdog 2...

Page 359: ...he EOS bit is set Note Software is allowed to write this bit only when ADSTART 0 which ensures that no regular conversion is ongoing Bit 2 EOCIE End of regular conversion interrupt enable This bit is set and cleared by software to enable disable the end of a regular conversion interrupt 0 EOC interrupt disabled 1 EOC interrupt enabled An interrupt is generated when the EOC bit is set Note Software...

Page 360: ...r calibration This bit is set and cleared by software to configure the single ended or differential inputs mode for the calibration 0 Writing ADCAL will launch a calibration in Single ended inputs Mode 1 Writing ADCAL will launch a calibration in Differential inputs Mode Note Software is allowed to write this bit only when the ADC is disabled and is not calibrating ADCAL 0 JADSTART 0 JADSTP 0 ADST...

Page 361: ...ad 1 means that an ADSTP command is in progress Note Software is allowed to set ADSTP only when ADSTART 1 and ADDIS 0 ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC Note In auto injection mode JAUTO 1 setting ADSTP bit aborts both regular and injected conversions do not use JADSTP Note In dual ADC regular simultaneous mode and inter...

Page 362: ...tion mode JAUTO 1 regular and auto injected conversions are started by setting bit ADSTART JADSTART must be kept cleared Bit 1 ADDIS ADC disable command This bit is set by software to disable the ADC ADDIS command and put it into power down state OFF state It is cleared by hardware once the ADC is effectively disabled ADEN is also cleared by hardware at this time 0 no ADDIS command ongoing 1 Write...

Page 363: ... ensures that no conversion is ongoing Bit 25 JAUTO Automatic injected group conversion This bit is set and cleared by software to enable disable automatic injected group conversion after regular group conversion 0 Automatic injected group conversion disabled 1 Automatic injected group conversion enabled Note Software is allowed to write this bit only when ADSTART 0 and JADSTART 0 which ensures th...

Page 364: ... slave ADC is no more writable and its content is equal to the bit JQM of the master ADC Bit 20 JDISCEN Discontinuous mode on injected channels This bit is set and cleared by software to enable disable discontinuous mode on the injected channels of a group 0 Discontinuous mode on injected channels disabled 1 Discontinuous mode on injected channels enabled Note Software is allowed to write this bit...

Page 365: ...are is allowed to write this bit only when ADSTART 0 and JADSTART 0 which ensures that no conversion is ongoing Note When dual mode is enabled bits DUAL of ADCx_CCR register are not equal to zero the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC Bit 13 CONT Single continuous conversion mode for regular conversions This bit is set and c...

Page 366: ...the external event used to trigger the start of conversion of a regular group 0000 Event 0 0001 Event 1 0010 Event 2 0011 Event 3 0100 Event 4 0101 Event 5 0110 Event 6 0111 Event 7 1111 Event 15 Note Software is allowed to write these bits only when ADSTART 0 which ensures that no regular conversion is ongoing Bit 5 ALIGN Data alignment This bit is set and cleared by software to select right or l...

Page 367: ...evant and replaced by control bit DMACFG of the ADCx_CCR register Bit 0 DMAEN Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests This allows to use the GP DMA to manage automatically the converted data For more details refer to Section Managing conversions using the DMA 0 DMA disabled 1 DMA enabled Note Software is allowed to write this bit...

Page 368: ...dually for each channel During sample cycles the channel selection bits must remain unchanged 000 1 5 ADC clock cycles 001 2 5 ADC clock cycles 010 4 5 ADC clock cycles 011 7 5 ADC clock cycles 100 19 5 ADC clock cycles 101 61 5 ADC clock cycles 110 181 5 ADC clock cycles 111 601 5 ADC clock cycles Note Software is allowed to write these bits only when ADSTART 0 and JADSTART 0 which ensures that n...

Page 369: ...at reset value Bits 26 0 SMPx 2 0 Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel During sampling cycles the channel selection bits must remain unchanged 000 1 5 ADC clock cycles 001 2 5 ADC clock cycles 010 4 5 ADC clock cycles 011 7 5 ADC clock cycles 100 19 5 ADC clock cycles 101 61 5 ADC clock cycles 110 181 5 ADC c...

Page 370: ...nd JADSTART 0 which ensures that no conversion is ongoing 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res HT2 7 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res LT2 7 0 rw rw rw rw rw rw rw rw Bits 31 24 Reserved must be kept at reset value Bits 23 16 HT2 7 0 Analog watchdog 2 higher threshold These bits are written by ...

Page 371: ...itten by software to define the higher threshold for the analog watchdog 3 Refer to Section 15 3 28 Analog window watchdog AWD1EN JAWD1EN AWD1SGL AWD1CH AWD2CH AWD3CH AWD_HTx AWD_LTx AWDx Note Software is allowed to write these bits only when ADSTART 0 and JADSTART 0 which ensures that no conversion is ongoing Bits 15 8 Reserved must be kept at reset value Bits 7 0 LT3 7 0 Analog watchdog 3 lower ...

Page 372: ...ngoing Note Analog input channel 0 is not mapped value 00000 should not be used Bit 23 Reserved must be kept at reset value Bits 22 18 SQ3 4 0 3rd conversion in regular sequence These bits are written by software with the channel number 1 18 assigned as the 3rd in the regular conversion sequence Note Software is allowed to write these bits only when ADSTART 0 which ensures that no regular conversi...

Page 373: ...is ongoing 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res SQ9 4 0 Res SQ8 4 0 Res SQ7 4 rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ7 3 0 Res SQ6 4 0 Res SQ5 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 29 Reserved must be kept at reset value Bits 28 24 SQ9 4 0 9th conversion in regular sequence These bits are written by software with the channel ...

Page 374: ... sequence These bits are written by software with the channel number 1 18 assigned as the 6th in the regular conversion sequence Note Software is allowed to write these bits only when ADSTART 0 which ensures that no regular conversion is ongoing Note Analog input channel 0 is not mapped value 00000 should not be used Bit 5 Reserved must be kept at reset value Bits 4 0 SQ5 4 0 5th conversion in reg...

Page 375: ... regular conversion is ongoing Note Analog input channel 0 is not mapped value 00000 should not be used Bit 17 Reserved must be kept at reset value Bits 16 12 SQ12 4 0 12th conversion in regular sequence These bits are written by software with the channel number 1 18 assigned as the 12th in the regular conversion sequence Note Software is allowed to write these bits only when ADSTART 0 which ensur...

Page 376: ...s are written by software with the channel number 1 18 assigned as the 16th in the regular conversion sequence Note Software is allowed to write these bits only when ADSTART 0 which ensures that no regular conversion is ongoing Note Analog input channel 0 is not mapped value 00000 should not be used Bit 5 Reserved must be kept at reset value Bits 4 0 SQ15 4 0 15th conversion in regular sequence Th...

Page 377: ...es Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA 15 0 r r r r r r r r r r r r r r r r Bits 31 16 Reserved must be kept at reset value Bits 15 0 RDATA 15 0 Regular Data converted These bits are read only They contain the conversion result from the last converted regular channel The data are left or right aligned as described in Section 15 3 26 D...

Page 378: ...onversion in the injected sequence These bits are written by software with the channel number 1 18 assigned as the 3rd in the injected conversion sequence Note Software is allowed to write these bits at any time once the ADC is enabled ADEN 1 Note Analog input channel 0 is not mapped value 00000 should not be used Bit 19 Reserved must be kept at reset value Bits 18 14 JSQ2 4 0 2nd conversion in th...

Page 379: ...omes empty the software and hardware triggers of the injected sequence are both internally disabled refer to Section 15 3 21 Queue of context for injected conversions Bits 5 2 JEXTSEL 3 0 External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group 0000 Event 0 0001 Event 1 0010 Event 2 0011 Event 3 0100 Event 4 010...

Page 380: ...ware is allowed to write these bits only when ADSTART 0 and JADSTART 0 which ensures that no conversion is ongoing Note Analog input channel 0 is not mapped value 00000 should not be used Bits 25 12 Reserved must be kept at reset value Bits 11 0 OFFSETy 11 0 Data offset y for the channel programmed into bits OFFSETy_CH 4 0 These bits are written by software to define the offset y to be subtracted ...

Page 381: ... 3 26 Data management 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res AWD2CH 18 16 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AWD2CH 15 1 Res rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 19 Reserved must be kept at reset value Bits 18 1 AWD2CH 18 1 Analog watchdog 2 channel selection These bits are set and cleared by software They ena...

Page 382: ... channel selection These bits are set and cleared by software They enable and select the input channels to be guarded by the analog watchdog 3 AWD3CH i 0 ADC analog input channel i is not monitored by AWD3 AWD3CH i 1 ADC analog input channel i is monitored by AWD3 When AWD3CH 18 1 000 0 the analog Watchdog 3 is disabled Note The channels selected by AWD3CH must be also selected into the SQRi or JS...

Page 383: ...3 2 1 0 Res Res Res Res Res Res Res Res Res CALFACT_S 6 0 rw rw rw rw rw rw rw Bits 31 23 Reserved must be kept at reset value Bits 22 16 CALFACT_D 6 0 Calibration Factors in differential mode These bits are written by hardware or by software Once a differential inputs calibration is complete they are updated by hardware with the calibration factors Software can write these bits with a new calibra...

Page 384: ...r r r r r r r r Bits 31 27 Reserved must be kept at reset value Bit 26 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADCx_ISR register Bit 25 AWD3_SLV Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx_ISR register Bit 24 AWD2_SLV Analog watchdog 2 flag of the slave ADC This...

Page 385: ... flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADCx_ISR register Bit 6 JEOS_MST End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADCx_ISR register Bit 5 JEOC_MST End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADCx_ISR register Bit 4 OVR_MST Overrun flag...

Page 386: ...0 VBAT channel disabled 1 VBAT channel enabled Note Software is allowed to write this bit only when the ADCs are disabled ADCAL 0 JADSTART 0 ADSTART 0 ADSTP 0 ADDIS 0 and ADEN 0 Bit 23 TSEN Temperature sensor enable This bit is set and cleared by software to enable disable the temperature sensor channel 0 Temperature sensor channel disabled 1 Temperature sensor channel enabled Note Software is all...

Page 387: ...nly when the ADCs are disabled ADCAL 0 JADSTART 0 ADSTART 0 ADSTP 0 ADDIS 0 and ADEN 0 Bits 15 14 MDMA 1 0 Direct memory access mode for dual ADC mode This bit field is set and cleared by software Refer to the DMA controller section for more details 00 MDMA mode disabled 01 reserved 10 MDMA mode enabled for 12 and 10 bit resolution 11 MDMA mode enabled for 8 and 6 bit resolution Note Software is a...

Page 388: ...taneous mode only 00110 Regular simultaneous mode only 00111 Interleaved mode only 01001 Alternate trigger mode only All other combinations are reserved and must not be programmed Note Software is allowed to write these bits only when the ADCs are disabled ADCAL 0 JADSTART 0 ADSTART 0 ADSTP 0 ADDIS 0 and ADEN 0 Table 95 DELAY bits versus ADC resolution DELAY bits 12 bit resolution 10 bit resolutio...

Page 389: ...l ADC modes STM32F302xB C D E only The data alignment is applied as described in Section Data register data alignment and offset ADCx_DR OFFSETy OFFSETy_CH ALIGN Bits 15 0 RDATA_MST 15 0 Regular data of the master ADC In dual mode these bits contain the regular data of the master ADC Refer to Section 15 3 29 Dual ADC modes STM32F302xB C D E only The data alignment is applied as described in Sectio...

Page 390: ...P13 2 0 SMP12 2 0 SMP11 2 0 SMP10 2 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C Reserved Res 0x20 ADCx_TR1 Res Res Res Res HT1 11 0 Res Res Res Res LT1 11 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0x24 ADCx_TR2 Res Res Res Res Res Res Res Res HT2 7 0 Res Res Res Res Res Res Res Res LT2 7 0 Reset value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0x28 ADCx_TR3 Re...

Page 391: ...JDR3 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res JDATA3 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x8C ADCx_JDR4 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res JDATA4 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x8C 0x9C Reserved Res 0xA0 ADCx_AWD2CR Res Res Res Res Res Res Res Res Res Res Res Res Res AWD2CH 18 1 Res Reset value 0 0 0 0 0 0 0 0 0 0 ...

Page 392: ...JQOVF_SLV AWD3_SLV AWD2_SLV AWD1_SLV JEOS_SLV JEOC_SLV OVR_SLV EOS_SLV EOC_SLV EOSMP_SLV ADRDY_SLV Res Res Res Res Res JQOVF_MST AWD3_MST AWD2_MST AWD1_MST JEOS_MST JEOC_MST OVR_MST EOS_MST EOC_MST EOSMP_MST ADRDY_MST slave ADC2 master ADC1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 Reserved Res 0x08 ADCx_CCR Res Res Res Res Res Res Res VBATEN TSEN VREFEN Res Res Res Res CKMODE 1 0 M...

Page 393: ...EF shared with ADC is available The output can optionally be buffered for higher current drive 16 2 DAC1 main features DAC1 integrates one 12 bit DAC channel DAC1_OUT1 The DAC main features are the following Left or right data alignment in 12 bit mode Synchronized update capability Noise wave generation Triangular wave generation DMA capability for each channel DMA underrun error detection Externa...

Page 394: ...sed to reduce the output impedance on DAC1_OUT1 output and to drive external loads directly without having to add an external operational amplifier The DAC channel output buffer can be enabled and disabled through the BOFF1 bit in the DAC_CR register Table 99 DACx pins Name Signal type Remarks VDDA Input analog supply Analog power supply VSSA Input analog supply ground Ground for analog power supp...

Page 395: ...and stored into the corresponding DHRx data holding registerx which are internal non memory mapped registers The DHRx register is then loaded into the DORx register either automatically by software trigger or by an external event trigger Figure 112 Data registers in single DAC channel mode 16 5 2 DAC channel conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channe...

Page 396: ... single triangle generation To configure the DAC in this conversion mode see Section 16 7 Triangle wave generation the following sequence is required 1 Set the DAC channelx trigger enable TENx bits 2 Configure the trigger source by setting TSELx 2 0 bits 3 Configure the DAC channelx WAVEx 1 0 bits as 1x and the same maximum amplitude value in the MAMPx 3 0 bits 4 Load the DAC channelx data into th...

Page 397: ...register is updated three APB1 cycles after the trigger occurs If the software trigger is selected the conversion starts once the SWTRIG bit is set SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents Note TSELx 2 0 bit cannot be changed when the ENx bit is set When software trigger is selected the transfer from the DAC_DHRx register to the DAC...

Page 398: ...gure 114 DAC LFSR register calculation algorithm The LFSR value that may be masked partially or totally by means of the MAMPx 3 0 bits in the DAC_CR register is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register If LFSR is 0x0000 a 1 is injected into it antilock up mechanism It is possible to reset LFSR wave generation by resetting the WAVEx...

Page 399: ...egister The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx 3 0 bits Once the configured amplitude is reached the counter is decremented down to 0 then incremented again and so on It is possible to reset triangle wave generation by resetting the WAVEx 1 0 bits Figure 116 DAC triangle wave generation Figure 117 DAC conversion SW trigger enabled ...

Page 400: ... request then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set reporting the error condition DMA data transfers are then disabled and no further DMA request is treated The DAC channelx continues to convert old data The software should clear the DMAUDRx flag by writing 1 clear the DMAEN bit of the used DMA stream and re initialize both DMA and DAC ch...

Page 401: ...AMP1 3 0 DAC channel1 mask amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode 0000 Unmask bit0 of LFSR triangle amplitude equal to 1 0001 Unmask bits 1 0 of LFSR triangle amplitude equal to 3 0010 Unmask bits 2 0 of LFSR triangle amplitude equal to 7 0011 Unmask bits 3 0 of LFSR triangle amplitude equal to 15 0100 U...

Page 402: ...le disable DAC channel1 trigger 0 DAC channel1 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR1 register 1 DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR1 register Note When software trigger is selected the transfer from the DAC_DHRx register to the ...

Page 403: ...reset value Bit 0 SWTRIG1 DAC channel1 software trigger This bit is set and cleared by software to enable disable the software trigger 0 Software trigger disabled 1 Software trigger enabled Note This bit is cleared by hardware one APB1 clock cycle later once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Re...

Page 404: ...erved must be kept at reset value Bits 15 4 DACC1DHR 11 0 DAC channel1 12 bit left aligned data These bits are written by software which specifies 12 bit data for DAC channel1 Bits 3 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res ...

Page 405: ... Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res DMAUDR1 Res Res Res Res Res Res Res Res Res Res Res Res Res rc_w1 Bits 31 14 Reserved must be kept at reset value Bit 13 DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software by writing it to 1 0 No DMA underrun error condition occurred for DAC channel1 1 DMA underrun error condition occ...

Page 406: ...Res Res Res Res Res Res Res Res Res Res Res SWTRIG1 Reset value 0 0x08 DAC_ DHR12R1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DACC1DHR 11 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x0C DAC_ DHR12L1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DACC1DHR 11 0 Res Res Res Res Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x10 DAC_ DHR8R1 Res Res Res Res Res R...

Page 407: ... combined with the DAC and a PWM output from a timer 17 2 COMP main features Rail to rail comparators Each comparator has positive and configurable negative inputs used for flexible voltage selection Multiplexed I O pins DAC1 channel 1 Internal reference voltage and three submultiple values 1 4 1 2 3 4 provided by scaler buffered voltage divider Programmable speed consumption only on STM32F302xBxC...

Page 408: ... analog mode in the GPIOs registers The comparator output can be connected to the I Os using the alternate function channel given in Alternate function mapping table in the datasheet The table below summarizes the I Os that can be used as comparators inputs and outputs 06 9 3 3 3 B 95 17 ô 95 17 ò 95 17 ó 95 17 3RODULW VHOHFWLRQ 203 7 0 B 1 7 0 B2 5 B 5 7 0 B 7 0 B 7 0 B2 5 B 5 7 0 B 7 0 B2 5 B 5 ...

Page 409: ...s COMP1 COMP2 COMP4 COMP6 Comparator inverting input connection to internal signals DAC1_CH1 Vrefint Vrefint Vrefint Vrefint Comparator inputs connected to I Os non inverting input inverting input PA1 PA0 PA4 PA5 PA3 1 PA7 PA2 PA4 PA5 1 Only on STM32F302xB C devices PB0 PE7 1 PB2 PE8 PA4 PA5 PB11 PD11 1 PB15 PD10 PA4 PA5 Comparator outputs motor control protection T1BKIN T1BKIN2 T1BKIN2 Outputs on...

Page 410: ...such as over current or thermal protection For applications having specific functional safety requirements it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption Table 103 STM32F302x6 8 comparator input outputs summary Comparator input outputs COMP2 COMP4 COMP6 Comparator inverting Input connection to internal s...

Page 411: ... to be able to force the hysteresis value using external components 17 3 6 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period typically the recovery current in power switches anti parallel diodes It consists of a selection of a blanking window which is a timer output comp...

Page 412: ...gisters can be programmed as follows 00 High speed full power 01 Medium speed medium power 10 Low speed low power 11 Very low speed ultra low power 17 4 COMP interrupts The comparator outputs are internally connected to the Extended interrupts and events controller Each comparator has its own EXTI line and can generate either interrupts or events The same mechanism is used to exit from low power m...

Page 413: ...ite 1 COMP1_CSR is read only Bit 30 COMP1OUT Comparator 1 output This read only bit is a copy of comparator 1output state 0 Output is low non inverting input below inverting input 1 Output is high non inverting input above inverting input Bits 29 21 Reserved must be kept at reset value Bits 20 18 COMP1_BLANKING Comparator 1 blanking source These bits select which Timer output controls the comparat...

Page 414: ...SEL 2 0 Comparator 1 inverting input selection These bits allows to select the source connected to the inverting input of the comparator 1 000 1 4 of Vrefint 001 1 2 of Vrefint 010 3 4 of Vrefint 011 Vrefint 100 PA4 or DAC1 output if enabled 101 PA5 110 PA0 111 Reserved Bits 3 2 COMP1MODE 1 0 Comparator 1 mode These bits control the operating mode of the comparator1 and allows to adjust the speed ...

Page 415: ...or 2 output This read only bit is a copy of comparator 1output state 0 Output is low non inverting input below inverting input 1 Output is high non inverting input above inverting input Bits 29 21 Reserved must be kept at reset value Bits 20 18 COMP2_BLANKING 2 0 Comparator 2 output blanking source These bits select which Timer output controls the comparator 1 output blanking 000 No blanking 001 T...

Page 416: ...n STM32F302xB C devices This bit selects the window mode Both non inverting inputs of comparators share the non inverting input of Comparator 1 PA1 0 Comparators 1 and 2 can not be used in window mode 1 Comparators 1 and 2 can be used in window mode Bit 8 Reserved must be kept at reset value Bit 7 COMP2INPSEL Comparator 2 non inverting input selection Only in STM32F302xB C devices 0 PA7 is selecte...

Page 417: ... low power Bit 1 COMP2_INP_DAC Comparator 2 non inverting input connection to DAC output STM32F302x6 8 devices only This bit closes a switch between comparator 2 non inverting input and DAC out I O 0 Switch open 1 Switch closed This switch is solely intended to redirect signals onto high impedance input such as COMP2 non inverting input highly resistive switch Bit 0 COMP2EN Comparator 2 enable Thi...

Page 418: ... inverting input 1 Output is high non inverting input above inverting input Bits 29 Reserved must be kept at reset value Bits 20 18 COMP4_BLANKING Comparator 4 blanking source These bits select which Timer output controls the comparator 4 output blanking 000 No blanking 001 TIM3 OC4 selected as blanking source 010 Reserved 011 TIM15 OC1 selected as blanking source Other configurations reserved mus...

Page 419: ...on inverting input selection 0 PB0 1 PE7 Note On STM32F302x6 8 and STM32F302xD E this bit is reserved COMP4_VINP is available on PB0 whatever value is written in bit 7 Bits 6 4 COMP4INMSEL 2 0 Comparator 4 inverting input selection These bits allows to select the source connected to the inverting input of the comparator 4 0000 1 4 of Vrefint 0001 1 2 of Vrefint 0010 3 4 of Vrefint 0011 Vrefint 010...

Page 420: ...ting input 1 Output is high non inverting input above inverting input Bits 29 Reserved must be kept at reset value Bits 20 18 COMP6_BLANKING Comparator 6 blanking source These bits select which Timer output controls the comparator 6 output blanking 000 No blanking 001 Reserved 010 Reserved 011 TIM2 OC4 selected as blanking source 100 TIM15 OC2 selected as blanking source Other configurations reser...

Page 421: ...ion 0 PD11 1 PB11 Note On STM32F302x6 8 and STM32F302xD E this bit is reserved COMP6_VINP is available on PB11 whatever value is written on bit 7 Bits 6 4 COMP6INMSEL 2 0 Comparator 6 inverting input selection These bits allows to select the source connected to the inverting input of the comparator 6 0000 1 4 of Vrefint 0001 1 2 of Vrefint 0010 3 4 of Vrefint 0011 Vrefint 0100 PA4 or DAC1_CH1 outp...

Page 422: ... Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 COMP2_CSR COMP2LOCK COMP2OUT Res Res Res Res Res Res Res Res Res COMP2_BLANKING Res COMP2POL Res COMP2OUT SEL 3 0 COMP2WINMODE Res COMP2INSEL COMP2INMSEL 2 0 COMP2MODE 1 0 COMP2_INP_DAC COMP2EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x28 COMP4_CSR COMP4LOCK COMP4OUT Res Res Res Res Res Res Res Res Res COMP4_BLANKING Res COMP4POL Res ...

Page 423: ...on inverting input Input multiplexer can be triggered by a timer and synchronized with a PWM signal 18 3 OPAMP functional description 18 3 1 General description On every OPAMP there is one 4 1 multiplexer on the non inverting input and one 2 1 multiplexer on the inverting input The inverting and non inverting inputs selection is made using the VM_SEL and VP_SEL bits respectively in the OPAMPx_CSR ...

Page 424: ...onnections between the operational amplifiers and the comparators are useful in motor control applications These connections are summarized in the following figures Figure 120 STM32F302xB C D E comparator and operational amplifier connections 7 0 B2 UHI OHDU 7 0 B2 5HI OHDU 203 LQWHUUXSW QWHUUXSW 7 0 B2 5HI OHDU 7 0 B2 UHI OHDU 7 0 B2 5HI OH 203 QWHUUXSW 7 0 B2 5HI OH 3 3 95 17 7 0 B 1 7 0 B 7 0 B...

Page 425: ... 10 is used on OPAMP2 18 3 5 Calibration The OPAMP interface continuously sends trimmed offset values to the 4 operational amplifiers At startup these values are initialized with the preset factory trimming value Furthermore each operational amplifier offset can be trimmed by the user 06Y 9 KDW ŝŶƚĞƌƌƵƉƚ KDW ŝŶƚĞƌƌƵƉƚ KDW ŶƚĞƌƌƵƉƚ н Ͳ 3RODULW 6HOHFWLRQ н Ͳ н Ͳ н Ͳ 203 W ϭϬ W ϲ 3 W ϭϭ 95 17 95 17 9...

Page 426: ... differences the TRIMOFFSETP bits fields are used and the CALSEL bits must be programmed to 01 an internal low voltage reference 0 1 x VDDA is generated and applied on the inverting and non inverting OPAMP inputs connected together Note During calibration mode to get the correct OUTCAL value please make sure the OFFTRIMmax delay specified in the datasheet electrical characteristics section has ela...

Page 427: ...amplifier is configured as a PGA and only connected to the ADC channel Note The impedance of the signal must be maintained below a level which avoids the input leakage to create significant artefacts due to a resistive drop in the source Please refer to the electrical characteristics section in the datasheet for further details Standalone mode external gain setting mode The external gain setting m...

Page 428: ... option is possible including comparator mode Follower configuration mode The amplifier can be configured as a follower by setting the VM_SEL bits to 11 in the OPAMPx_CR register This allows you for instance to buffer signals with a relatively high impedance In this case the inverting inputs are free and the corresponding ports can be used as regular I Os 670 2S PS S S 06 9 60 60 60 60 6 6 ...

Page 429: ...onnection in this mode An alternative option in PGA mode allows you to route the central point of the resistive network on one of the I Os connected to the non inverting input This is enabled using the PGA_GAIN bits in OPAMPx_CR register 10xx values are setting the gain and connect the central point to one of the two available inputs 11xx values are setting the gain and connect the central point t...

Page 430: ...nput not used Figure 126 PGA mode internal gain setting x2 x4 x8 x16 inverting input used for filtering 670 2S PS S S WBJMBCMF 0T OZD V FRQQHFWHG WR 23 03 RXWSXW FDQ EH XVHG GXULQJ GHEXJ 06 9 60 60 60 60 6 6 670 2S PS S S OORZV RSWLRQDO ORZ SDVV ILOWHULQJ 1 JDLQ GHSHQGV RQ FXW RII IUHTXHQF TXLYDOHQW WR 3 QHWZRUN 06 9 60 60 60 60 6 6 ...

Page 431: ...s bit is write once It is set by software It can only be cleared by a system reset This bit is used to configure the OPAMP1_CSR register as read only 0 OPAMP1_CSR is read write 1 OPAMP1_CSR is read only Bit 30 OUTCAL OPAMP output status flag when the OPAMP is used as comparator during calibration 0 Non inverting inverting 1 Non inverting inverting Bit 29 TSTREF This bit is set and cleared by softw...

Page 432: ...mode connecting VM and VP to the OPAMP internal reference voltage 0 Calibration mode disabled 1 Calibration mode enabled Bits 10 9 VPS_SEL OPAMP1 Non inverting input secondary selection These bits are set and cleared by software They are used to select the OPAMP1 non inverting input when TCM_EN 1 00 PA7 used as OPAMP1 non inverting input 01 PA5 used as OPAMP1 non inverting input 10 PA3 used as OPA...

Page 433: ...It is used to enable the OPAMP1 0 OPAMP1 is disabled 1 OPAMP1 is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LOCK OUT CAL TSTR EF TRIMOFFSETN TRIMOFFSETP USER_ TRIM PGA_GAIN rw r rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PGA_GAIN CALSEL CAL ON VPS_SEL VMS_ SEL TCM_ EN VM_SEL Res VP_SEL FORCE _VP OPAMP 2EN rw rw rw rw rw rw rw rw rw rw Bit 31 LOCK OPAMP 2 lock This bit is wri...

Page 434: ...or FORCE_VP 1 00 VREFOPAMP 3 3 VDDA 01 VREFOPAMP 10 VDDA 10 VREFOPAMP 50 VDDA 11 VREFOPAMP 90 VDDA Bit 11 CALON Calibration mode enable This bit is set and cleared by software It is used to enable the calibration mode connecting VM and VP to the OPAMP internal reference voltage 0 calibration mode disabled 1 calibration mode enabled Bits 10 9 VPS_SEL OPAMP2 Non inverting input secondary selection T...

Page 435: ...oftware They are used to select the OPAMP2 non inverting input 00 PD14 used as OPAMP2 non inverting input STM32F302xB C D E devices only 01 PB14 used as OPAMP2 non inverting input 10 PB0 used as OPAMP2 non inverting input 11 PA7 used as OPAMP2 non inverting input Bit 1 FORCE_VP This bit forces a calibration reference voltage on non inverting input and disables external connections 0 Normal operati...

Page 436: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x38 OPAMP1_CSR LOCK OUTCAL TSTREF TRIMOFFSETN TRIMOFFSETP USER_TRIM PGA_GAIN CALSEL CALON VPS_SEL VMS_SEL TCM_EN VM_SEL Res VP_SEL FORCE_VP OPAMP1EN Reset value X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3C OPAMP2_CSR LOCK OUTCAL TSTREF TRIMOFFSETN TRIMOFFSETP USER_TRIM PGA_GAIN CALSEL CALON VPS_SEL VMS...

Page 437: ...urface charge transfer acquisition principle Supports up to 24 capacitive sensing channels on STM32F302xBxC devices and 18 on STM32F302x6 x8 devices Up to 8 capacitive sensing channels on STM32F302xBxC devices and 6 on STM32F302x6 x8 devices can be acquired in parallel offering a very good response time Spread spectrum feature to improve system robustness in noisy environments full hardware manage...

Page 438: ...th a single ended electrode type This acquisition is designed around an analog I O group which is composed of four GPIOs see Figure 128 Several analog I O groups are available to allow the acquisition of several capacitive sensing channels simultaneously and to support a larger number of capacitive sensing channels Within a same analog I O group the acquisition of the capacitive sensing channels i...

Page 439: ...an electrode capacitance CX and transferring a part of the accumulated charge into a sampling capacitor CS This sequence is repeated until the voltage across CS reaches a given threshold VIH in our case The number of charge transfers required to reach the threshold is a direct representation of the size of the electrode capacitance The Table 107 details the charge transfer acquisition sequence of ...

Page 440: ...k Controller RCC provides dedicated bits to enable the touch sensing controller clock and to reset this peripheral For more information please refer to Section 9 Reset and clock control RCC Table 107 Acquisition sequence summary State G1_IO1 electrode G1_IO2 sampling G1_IO3 electrode G1_IO4 electrode State description 1 Input floating with analog switch closed Output open drain low with analog swi...

Page 441: ...loating state is inserted between the pulse high and low states to ensure an optimum charge transfer acquisition sequence This state duration is 2 periods of HCLK At the end of the pulse high state and if the spread spectrum feature is enabled a variable number of periods of the SSCLK clock are added The reading of the sampling capacitor I O to determine if the voltage across CS has reached the gi...

Page 442: ...ure can be disabled enabled using the SSE bit in the TSC_CR register The frequency deviation is also configurable to accommodate the device HCLK clock frequency and the selected charge transfer frequency through the SSPSC and SSD 6 0 bits in the TSC_CR register 19 3 6 Max count error The max count error prevents long acquisition times resulting from a faulty capacitive sensing channel It consists ...

Page 443: ...Sampling capacitor I O mode To allow the control of the sampling capacitor I O by the TSC peripheral the corresponding GPIO must be first set to alternate output open drain mode and then the corresponding Gx_IOy bit in the TSC_IOSCR register must be set Only one sampling capacitor per analog I O group must be enabled at a time Channel I O mode To allow the control of the channel I O by the TSC per...

Page 444: ...I O groups is complete all GxS bits of all enabled analog I O groups are set the EOAF flag in the TSC_ISR register is set An interrupt request is generated if the EOAIE bit in the TSC_IER register is set In the case that a max count error is detected the ongoing acquisition is stopped and both the EOAF and MCEF flags in the TSC_ISR register are set Interrupt requests can be generated for both even...

Page 445: ...rupts cause the device to exit Sleep mode Stop TSC registers are frozen The TSC stops its operation until the Stop or Standby mode is exited Standby Table 111 Interrupt control bits Interrupt event Enable control bit Event flag Clear flag bit Exit the Sleep mode Exit the Stop mode Exit the Standby mode End of acquisition EOAIE EOAIF EOAIC yes no no Max count error MCEIE MCEIF MCEIC yes no no ...

Page 446: ... charge transfer pulse charge of CX 0000 1x tPGCLK 0001 2x tPGCLK 1111 16x tPGCLK Note These bits must not be modified when an acquisition is ongoing Bits 27 24 CTPL 3 0 Charge transfer pulse low These bits are set and cleared by software They define the duration of the low state of the charge transfer pulse transfer of charge from CX to CS 0000 1x tPGCLK 0001 2x tPGCLK 1111 16x tPGCLK Note These ...

Page 447: ...tions are forbidden Please refer to the Section 19 3 4 Charge transfer acquisition sequence for details Bits 11 8 Reserved must be kept at reset value Bits 7 5 MCV 2 0 Max count value These bits are set and cleared by software They define the maximum number of charge transfer pulses that can be generated before a max count error is generated 000 255 001 511 010 1023 011 2047 100 4095 101 8191 110 ...

Page 448: ...Bit 0 TSCE Touch sensing controller enable This bit is set and cleared by software to enable disable the touch sensing controller 0 Touch sensing controller disabled 1 Touch sensing controller enabled Note When the touch sensing controller is disabled TSC registers settings have no effect 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Re...

Page 449: ...IC rw rw Bits 31 2 Reserved must be kept at reset value Bit 1 MCEIC Max count error interrupt clear This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset Writing a 0 has no effect 0 No effect 1 Clears the corresponding MCEF of the TSC_ISR register Bit 0 EOAIC End of acquisition interrupt clear This bit is set by software to clear the end...

Page 450: ...he acquisition of all enabled group is complete all GxS bits of all enabled analog I O groups are set or when a max count error is detected It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register 0 Acquisition is ongoing or not started 1 Acquisition is complete 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3...

Page 451: ... These bits control the I O analog switch whatever the I O control mode is even if controlled by standard GPIO registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO...

Page 452: ...O1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 Gx_IOy Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I O 0 Gx_IOy unused 1 Gx_IOy used as channel Note These bits must not be modified when an acquisition is ongoing During the acquisition phase and even if the TSC peripheral alternate function is not enabl...

Page 453: ...emaining GxS bits of the enabled analog I O groups are not set Bits 15 8 Reserved must be kept at reset value Bits 7 0 GxE Analog I O group x enable These bits are set and cleared by software to enable disable the acquisition counter is counting on the corresponding analog I O group x 0 Acquisition on analog I O group x disabled 1 Acquisition on analog I O group x enabled 31 30 29 28 27 26 25 24 2...

Page 454: ...SCR G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x001C Reserved 0x0020 TSC_IOSCR G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 ...

Page 455: ... Res Res Res Res Res Res Res Res Res Res CNT 13 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0048 TSC_IOG6CR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CNT 13 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x004C TSC_IOG7CR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CNT 13 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0050 TSC_IOG8CR Res Res Res Re...

Page 456: ...wn auto reload counter 16 bit programmable prescaler allowing dividing also on the fly the counter clock frequency either by any factor between 1 and 65536 Up to 6 independent channels for Input Capture but channels 5 and 6 Output Compare PWM generation Edge and Center aligned Mode One pulse mode output Complementary outputs with programmable dead time Synchronization circuit to control the timer ...

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Page 458: ...reload enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow or underflow when downcounting and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the update event is described in detailed for each configuration The counter is clocked by the prescaler output CK_CNT which is enabled only when the cou...

Page 459: ...r timing diagram with prescaler division change from 1 to 4 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU 06 9 06 9 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU ...

Page 460: ...ad registers Then no update event occurs until the UDIS bit has been written to 0 However the counter restarts from 0 as well as the counter of the prescaler but the prescale rate does not change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sent T...

Page 461: ... internal clock divided by 1 Figure 136 Counter timing diagram internal clock divided by 2 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 462: ...agram internal clock divided by 4 Figure 138 Counter timing diagram internal clock divided by N 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 463: ...Mx_ARR preloaded ϯϲ 06 9 ͺW dŝŵĞƌĐůŽĐŬ с ͺ Ed ŽƵŶƚĞƌ ƌĞŐŝƐƚĞƌ hƉĚĂƚĞ ĞǀĞŶƚ h sͿ ŽƵŶƚĞƌ ŽǀĞƌĨůŽǁ hƉĚĂƚĞ ŝŶƚĞƌƌƵƉƚ ĨůĂŐ h Ϳ ϬϬ ϬϮ Ϭϯ Ϭϰ Ϭϱ Ϭϲ Ϭϳ ϯϮ ϯϯ ϯϰ ϯϱ ϯϲ ϯϭ Ϭϭ E ƵƚŽͲƌĞůŽĂĚ ƉƌĞůŽĂĚ ƌĞŐŝƐƚĞƌ tƌŝƚĞ Ă ŶĞǁ ǀĂůƵĞ ŝŶ d Ddžͺ ZZ 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 1 XWR UHORDG SUHORDG UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B 55 XWR UHORDG VKDGRZ U...

Page 464: ...However the counter restarts from the current auto reload value whereas the counter of the prescaler restarts from 0 but the prescale rate doesn t change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sent This is to avoid generating both update and...

Page 465: ...rnal clock divided by 1 Figure 142 Counter timing diagram internal clock divided by 2 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ FQWBXGI 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 466: ...gram internal clock divided by 4 Figure 144 Counter timing diagram internal clock divided by N 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 467: ...updated by hardware and gives the current direction of the counter The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register by software or by using the slave mode controller also generates an update event In this case the counter restarts counting from 0 as well as the counter of the prescaler The UEV update event ca...

Page 468: ...Mx_PSC register The auto reload active register is updated with the preload value content of the TIMx_ARR register Note that if the update source is a counter overflow the auto reload is updated before the counter is reloaded so that the next period is the expected one the counter is loaded with the new value The following figures show some examples of the counter behavior for different clock freq...

Page 469: ...Counter timing diagram internal clock divided by 4 TIMx_ARR 0x36 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 1RWH HUH FHQWHUBDOLJQHG PRGH RU LV XSGDWHG ZLWK DQ 8 RQ RYHUIORZ ...

Page 470: ...ter timing diagram update event with ARPE 1 counter underflow 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 1 XWR UHORDG SUHORDG UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B 55 XWR UHORDG DFWLYH UHJLVWHU ...

Page 471: ...counter underflow in downcounting mode At each counter overflow and at each counter underflow in center aligned mode Although this limits the maximum number of repetition to 32768 PWM cycles it makes it possible to update the duty cycle twice per PWM period When refreshing compare registers only once per PWM period in center aligned mode maximum resolution is 2xTck due to the symmetry of the patte...

Page 472: ...curs on the underflow For example for RCR 3 the UEV is generated each 4th overflow or underflow event depending on when the RCR was written Figure 152 Update rate examples depending on mode and TIMx_RCR register settings 06Y 9 8 9 8 9 8 9 8 9 8 9 RXQWHU DOLJQHG PRGH GJH DOLJQHG PRGH 8SFRXQWLQJ RZQFRXQWLQJ E 6 E 6 E 6 7 0 B5 5 DQG UH V QFKURQL DWLRQ 7 0 B5 5 7 0 B5 5 7 0 B5 5 7 0 B5 5 RXQWHU 7 0 B ...

Page 473: ...current regulation see Section 20 3 7 Figure 153 below describes the ETR input conditioning The input polarity is defined with the ETP bit in TIMxSMCR register The trigger can be prescaled with the divider programmed by the ETPS 1 0 bitfield and digitally filtered with the ETF 3 0 bitfield Figure 153 External trigger input block 06 9 7R WKH 2XWSXW PRGH FRQWUROOHU 7R WKH B36 FLUFXLWU 7R WKH 6ODYH P...

Page 474: ...EGR register are actual control bits and can be changed only by software except UG which remains cleared automatically As soon as the CEN bit is written to 1 the prescaler is clocked by the internal clock CK_INT Figure 154 shows the behavior of the control circuit and the upcounter in normal mode without prescaler Figure 154 Control circuit in normal mode internal clock divided by 1 External clock...

Page 475: ...onfigure the timer in external clock mode 1 by writing SMS 111 in the TIMx_SMCR register 5 Select TI2 as the trigger input source by writing TS 110 in the TIMx_SMCR register 6 Enable the counter by writing CEN 1 in the TIMx_CR1 register Note The capture prescaler is not used for triggering so the user does not need to configure it When a rising edge occurs on TI2 the counter counts once and the TI...

Page 476: ...nput ETR The Figure 157 gives an overview of the external trigger input block Figure 157 External trigger input block For example to configure the upcounter to count each 2 rising edges on ETR use the following procedure RXQWHU FORFN B 17 B36 RXQWHU UHJLVWHU 7 17B 1 7 ULWH 7 06 9 WHUQDO FORFN PRGH QWHUQDO FORFN PRGH 75 B 17 B36 7 0 B60 5 606 06 9 LQWHUQDO FORFN 7 RU 7 RU RU QFRGHU PRGH WHUQDO FORF...

Page 477: ...ng ETP 0 in the TIMx_SMCR register 4 Enable external clock mode 2 by writing ECE 1 in the TIMx_SMCR register 5 Enable the counter by writing CEN 1 in the TIMx_CR1 register The counter counts once each 2 ETR rising edges The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal Figure 158 Control circuit in external clock...

Page 478: ...erate a filtered signal TIxF Then an edge detector with polarity selection generates a signal TIxFPx which can be used as trigger input by the slave mode controller or as the capture command It is prescaled before the capture register ICxPS Figure 159 Capture compare channel example channel 1 input stage The output stage generates an intermediate waveform which is then used for reference OCxRef ac...

Page 479: ...DUH VKDGRZ UHJLVWHU RPSDUDWRU DSWXUH FRPSDUH SUHORDG UHJLVWHU RXQWHU 36 6 6 DSWXUH QSXW PRGH 6 5 5HDG 5 5HDG 5 UHDGBLQBSURJUHVV FDSWXUHBWUDQVIHU 6 6 6 5 ZULWH 5 ZULWH 5 ZULWHBLQBSURJUHVV 2XWSXW PRGH 8 9 2 3 IURP WLPH EDVH XQLW FRPSDUHBWUDQVIHU 3 XV KLJK ORZ LI ELW 0 8 SHULSKHUDO LQWHUIDFH 7 0 B 05 2 3 17 5 17 5 7 0 B 5 06 9 ...

Page 480: ... 0 B 05 2 0 2 5 2 HDG WLPH JHQHUDWRU 2 B 7 2 1B 7 7 7 0 B 75 µ µ 7 0 B 5 1 3 7 0 B 5 13 7 0 B 5 2 2XWSXW HQDEOH FLUFXLW 2 1 7 0 B 5 1 266 7 0 B 75 02 2665 2XWSXW VHOHFWRU 2 5 2 5 7R WKH PDVWHU PRGH FRQWUROOHU 2XWSXW HQDEOH FLUFXLW 2 5 RFUHIBFOUBLQW 2 5 B 5 75 2 6 7 0 B60 5 06 9 2XWSXW PRGH FRQWUROOHU 17 5 17 5 7 0 B 05 2 0 3 7 0 B 5 2XWSXW HQDEOH FLUFXLW 2 7 0 B 5 7R WKH PDVWHU PRGH FRQWUROOHU 2 5...

Page 481: ... CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register CCxOF is cleared when you write it to 0 The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises To do this use the following procedure Select the active input TIMx_CCR1 must be linked to the TI1 input so write the CC1S bits to 01 in the TIMx_C...

Page 482: ...curs The TIMx_CCR1 register gets the value of the counter on the active transition CC1IF flag is set interrupt flag CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared An interrupt is generated depending on the CC1IE bit A DMA request is generated depending on the CC1DE bit In order to handle the overcapture it is recommended to read the data before the...

Page 483: ...ter TI1FP1 selected Configure the slave mode controller in reset mode write the SMS bits to 0100 in the TIMx_SMCR register Enable the captures write the CC1E and CC2E bits to 1 in the TIMx_CCER register Figure 164 PWM input mode timing 20 3 9 Forced output mode In output mode CCxS bits 00 in the TIMx_CCMRx register each output compare signal OCxREF and then OCx OCxN can be forced to active or inac...

Page 484: ...t if the corresponding interrupt mask is set CCXIE bit in the TIMx_DIER register Sends a DMA request if the corresponding enable bit is set CCxDE bit in the TIMx_DIER register CCDS bit in the TIMx_CR2 register for the DMA request selection The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register In output compare mode the update eve...

Page 485: ...ster As the preload registers are transferred to the shadow registers only when an update event occurs before starting the counter you have to initialize all the registers by setting the UG bit in the TIMx_EGR register OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register It can be programmed as active high or active low OCx output is enabled by a combination of the CC...

Page 486: ...gned PWM waveforms ARR 8 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high Refer to the Downcounting mode on page 464 In PWM mode 1 the reference signal OCxRef is low as long as TIMx_CNT TIMx_CCRx else it becomes high If the compare value in TIMx_CCRx is greater than the auto reload value in TIMx_ARR then OCxREF is held at 1 0 PWM is not possible in this m...

Page 487: ... is the PWM mode 1 The flag is set when the counter counts down corresponding to the center aligned mode 1 selected for CMS 01 in TIMx_CR1 register Figure 167 Center aligned PWM waveforms ARR 8 Hints on using center aligned mode When starting in center aligned mode the current up down configuration is used It means that the counter counts up or down depending on the value written in the DIR bit RX...

Page 488: ...d the phase shift are determined by a pair of TIMx_CCRx register One register controls the PWM during up counting the second during down counting so that PWM is adjusted every half PWM cycle OC1REFC or OC2REFC is controlled by TIMx_CCR1 and TIMx_CCR2 OC3REFC or OC4REFC is controlled by TIMx_CCR3 and TIMx_CCR4 Asymmetric PWM mode can be selected independently on two channel one OCx output per pair ...

Page 489: ...n be selected independently on two channels one OCx output per pair of CCR registers by writing 1100 Combined PWM mode 1 or 1101 Combined PWM mode 2 in the OCxM bits in the TIMx_CCMRx register When a given channel is used as combined PWM channel its complementary channel must be configured in the opposite PWM mode for instance one in Combined PWM mode 1 and the other in Combined PWM mode 2 Note Th...

Page 490: ...he 3 bits GC5C 3 1 in the TIMx_CCR5 allow selection on which reference signal the OC5REF is combined The resulting signals OCxREFC are made of an AND logical combination of two reference PWMs If GC5C1 is set OC1REFC is controlled by TIMx_CCR1 and TIMx_CCR5 If GC5C2 is set OC2REFC is controlled by TIMx_CCR2 and TIMx_CCR5 If GC5C3 is set OC3REFC is controlled by TIMx_CCR3 and TIMx_CCR5 Combined 3 ph...

Page 491: ...outputs and their characteristics intrinsic delays of level shifters delays due to power switches You can select the polarity of the outputs main output OCx or complementary OCxN independently for each output This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register The complementary signals OCx and OCxN are activated by a combination of several control bits the CCxE and CCxNE b...

Page 492: ...eference rising edge The OCxN output signal is the opposite of the reference signal except for the rising edge which is delayed relative to the reference falling edge If the delay is greater than the width of the active output OCx or OCxN then the corresponding pulse is not generated The following figures show the relationships between the output signals of the dead time generator and the referenc...

Page 493: ...CxREF is high For example if CCxNP 0 then OCxN OCxRef On the other hand when both OCx and OCxN are enabled CCxE CCxNE 1 OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low 20 3 16 Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM1 timer The two break inputs are u...

Page 494: ...an be asynchronous a resynchronization circuit has been inserted between the actual signal acting on the outputs and the synchronous control bit accessed in the TIMx_BDTR register It results in some delays between the asynchronous and the synchronous signals In particular if you write MOE to 1 whereas it was low you must insert a delay dummy instruction before reading it correctly This is because ...

Page 495: ... the timer releases the output control taken over by the GPIO controller which forces a Hi Z state otherwise the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high The break status flag BIF and B2IF bits in the TIMx_SR register is set An interrupt is generated if the BIE bit in the TIMx_DIER register is set A DMA request can be sent if the BDE bit in the TIMx_DIE...

Page 496: ...break event on BKIN OSSI 1 GHOD GHOD GHOD GHOD GHOD GHOD GHOD GHOD 2 5 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 1 13 2 6 2 6 1 RU 2 6 2 6 1 06 9 5 02 ...

Page 497: ...CxN output behavior in case of active signals on BKIN and BKIN2 inputs In this case both outputs have active high polarities CCxP CCxNP 0 in TIMx_CCER register Figure 175 PWM output state following BKIN and BKIN2 pins assertion OSSI 1 Table 113 Behavior of timer outputs versus BRK BRK2 inputs BRK BRK2 Timer outputs state Typical use case OCxN output low side switches OCx output high side switches ...

Page 498: ...s the behavior of the OCxREF signal when the ETRF Input becomes High for both values of the enable bit OCxCE In this example the timer TIMx is programmed in PWM mode 06 9 1 2 2 VWDWH HDGWLPH FWLYH QDFWLYH LVDEOHG 2 VWDWH GHILQHG E WKH 3 2 FRQWUROOHU 2 VWDWH GHILQHG E WKH 3 2 FRQWUROOHU The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input OCxCE...

Page 499: ...cID025202 Rev 7 Figure 177 Clearing TIMx OCxREF Note In case of a PWM with a 100 duty cycle if CCRx ARR then OCxREF is enabled again at the next counter overflow 06 9 5 RXQWHU 17 75 2 5 2 µ 2 5 2 µ RFUHIBFOUBLQW EHFRPHV KLJK RFUHIBFOUBLQW VWLOO KLJK ...

Page 500: ...e TIMx_EGR register or by hardware on TRGI rising edge A flag is set when the COM event occurs COMIF bit in the TIMx_SR register which can generate an interrupt if the COMIE bit is set in the TIMx_DIER register or a DMA request if the COMDE bit is set in the TIMx_DIER register The Figure 178 describes the behavior of the OCx and OCxN outputs when a COM event occurs in 3 different examples of progr...

Page 501: ...is different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be In upcounting CNT CCRx ARR in particular 0 CCRx In downcounting CNT CCRx Figure 179 Example of one pulse mode For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2...

Page 502: ... bit which enables the counter Then the comparison between the counter and the compare value makes the output toggle But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get If you want to output a waveform with the minimum delay you can set the OCxFE bit in the TIMx_CCMRx register Then OCxRef and OCx are forced in response to the stimulus with...

Page 503: ...es as well as the direction signal Depending on the sequence the counter counts up or down the DIR bit in the TIMx_CR1 register is modified by hardware accordingly The DIR bit is calculated at each transition on any input TI1 or TI2 whatever the counter is counting on TI1 only TI2 only or both TI1 and TI2 Encoder interface mode acts simply as an external clock with direction selection This means t...

Page 504: ...e that the configuration is the following CC1S 01 TIMx_CCMR1 register TI1FP1 mapped on TI1 CC2S 01 TIMx_CCMR2 register TI1FP2 mapped on TI2 CC1P 0 and CC1NP 0 TIMx_CCER register TI1FP1 non inverted TI1FP1 TI1 CC2P 0 and CC2NP 0 TIMx_CCER register TI1FP2 non inverted TI1FP2 TI2 SMS 011 TIMx_SMCR register both inputs are active on both rising and falling edges CEN 1 TIMx_CR1 register Counter enabled...

Page 505: ...nto the timer counter register s bit 31 TIMxCNT 31 This allows both the counter value and a potential roll over condition signaled by the UIFCPY flag to be read in an atomic way It eases the calculation of angular speed by avoiding race conditions caused for instance by a processing shared between a background task counter reading and an interrupt update interrupt There is no latency between the U...

Page 506: ... setting the TI1S bit in the TIMx_CR2 register The slave mode controller is configured in reset mode the slave input is TI1F_ED Thus each time one of the 3 inputs toggles the counter restarts counting from 0 This creates a time base triggered by any change on the Hall inputs On the interfacing timer capture compare channel 1 is configured in capture mode capture signal is TRC See Figure 159 Captur...

Page 507: ... the CC1S bits in the TIMx_CCMR1 register to 01 You can also program the digital filter if needed Program the channel 2 in PWM 2 mode with the desired delay write the OC2M bits to 111 and the CC2S bits to 00 in the TIMx_CCMR1 register Select OC2REF as trigger output on TRGO write the MMS bits in the TIMx_CR2 register to 101 In the advanced control timer TIM1 the right ITR input must be selected as...

Page 508: ...508 1080 RM0365 Advanced control timers TIM1 549 Figure 184 Example of Hall sensor interface RXQWHU 17 75 2 2 5 5 2 2 1 20 ULWH 1 7 7 7 5 2 2 1 2 2 1 DQG 2 0 IRU QH W VWHS QWHUIDFLQJ WLPHU GYDQFHG FRQWURO WLPHUV 7 0 06 9 ...

Page 509: ...re it The CC1S bits select the input capture source only CC1S 01 in the TIMx_CCMR1 register Write CC1P 0 and CC1NP 0 in TIMx_CCER register to validate the polarity and detect rising edges only Configure the timer in reset mode by writing SMS 100 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register Start the counter by writing CEN 1 in the TIMx_CR1 register T...

Page 510: ..._CR1 register in gated mode the counter doesn t start if CEN 0 whatever is the trigger input level The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high The TIF flag in the TIMx_SR register is set both when the counter starts or stops The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization c...

Page 511: ...ombined reset trigger mode In this case a rising edge of the selected trigger input TRGI reinitializes the counter generates an update of the registers and starts the counter This mode is used for one pulse mode Slave mode external clock mode 2 trigger mode The external clock mode 2 can be used in addition to another slave mode except external clock mode 1 and encoder mode In this case the ETR sig...

Page 512: ...R register to validate the polarity and detect rising edge only 3 Configure the timer in trigger mode by writing SMS 110 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register A rising edge on TI1 enables the counter and sets the TIF flag The counter then counts on ETR rising edges The delay between the rising edge of the ETR signal and the actual reset of the...

Page 513: ...e TIMx timers have the capability to generate multiple DMA requests upon a single event The main purpose is to be able to re program part of the timer multiple times without software overhead but it can also be used to read several registers in a row at regular intervals The DMA controller destination is unique and must point to the virtual register TIMx_DMAR On a given timer event the timer launc...

Page 514: ... follows on the first update DMA request data1 is transferred to CCR2 data2 is transferred to CCR3 data3 is transferred to CCR4 and on the second update DMA request data4 is transferred to CCR2 data5 is transferred to CCR3 and data6 is transferred to CCR4 Note A null value can be written to the reserved registers 20 3 28 Debug mode When the microcontroller enters debug mode Cortex M4 F core halted...

Page 515: ...t 7 ARPE Auto reload preload enable 0 TIMx_ARR register is not buffered 1 TIMx_ARR register is buffered Bits 6 5 CMS 1 0 Center aligned mode selection 00 Edge aligned mode The counter counts up or down depending on the direction bit DIR 01 Center aligned mode 1 The counter counts up and down alternatively Output compare interrupt flags of channels configured in output CCxS 00 in TIMx_CCMRx registe...

Page 516: ...EV enabled The Update UEV event is generated by one of the following events Counter overflow underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values 1 UEV disabled The Update event is not generated shadow registers keep their value ARR PSC CCRx However the counter and the prescaler are reinitialized if the UG bit...

Page 517: ...oon as a capture or compare match occurs TRGO2 0100 Compare OC1REF signal is used as trigger output TRGO2 0101 Compare OC2REF signal is used as trigger output TRGO2 0110 Compare OC3REF signal is used as trigger output TRGO2 0111 Compare OC4REF signal is used as trigger output TRGO2 1000 Compare OC5REF signal is used as trigger output TRGO2 1001 Compare OC6REF signal is used as trigger output TRGO2...

Page 518: ...signal on TRGO is delayed compared to the actual reset 001 Enable the Counter Enable signal CNT_EN is used as trigger output TRGO It is useful to start several timers at the same time or to control a window in which a slave timer is enable The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode When the Counter Enable signal ...

Page 519: ...es Res Res Res Res Res Res Res Res Res Res SMS 3 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETP ECE ETPS 1 0 ETF 3 0 MSM TS 2 0 OCCS SMS 2 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 17 Reserved must be kept at reset value Bit 16 SMS 3 Slave mode selection bit 3 Refer to SMS description bits 2 0 Bit 15 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigge...

Page 520: ...PLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bit 7 MSM Master slave mode 0 No action 1 The effect of an event on the trigger input TRGI is delayed to allow a perfect synchronization between the current timer and its slaves through TRGO It is useful if we want to synchronize several timers on...

Page 521: ...es low Both start and stop of the counter are controlled 0110 Trigger Mode The counter starts at a rising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 0111 External Clock Mode 1 Rising edges of the selected trigger TRGI clock the counter 1000 Combined reset trigger mode Rising edge of the selected trigger input TRGI reinitializes the counter generates an...

Page 522: ...ompare 2 DMA request enable 0 CC2 DMA request disabled 1 CC2 DMA request enabled Bit 9 CC1DE Capture Compare 1 DMA request enable 0 CC1 DMA request disabled 1 CC1 DMA request enabled Bit 8 UDE Update DMA request enable 0 Update DMA request disabled 1 Update DMA request enabled Bit 7 BIE Break interrupt enable 0 Break interrupt disabled 1 Break interrupt enabled Bit 6 TIE Trigger interrupt enable 0...

Page 523: ...ote Channel 6 can only be configured as output Bit 16 CC5IF Compare 5 interrupt flag Refer to CC1IF description Note Channel 5 can only be configured as output Bits 15 13 Reserved must be kept at reset value Bit 12 CC4OF Capture Compare 4 overcapture flag Refer to CC1OF description Bit 11 CC3OF Capture Compare 3 overcapture flag Refer to CC1OF description Bit 10 CC2OF Capture Compare 2 overcapture...

Page 524: ...put This flag is set by hardware when the counter matches the compare value with some exception in center aligned mode refer to the CMS bits in the TIMx_CR1 register description It is cleared by software 0 No match 1 The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR the CC1IF bit goes high on t...

Page 525: ...ically cleared by hardware 0 No action 1 A break event is generated MOE bit is cleared and BIF flag is set Related interrupt or DMA transfer can occur if enabled Bit 6 TG Trigger generation This bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 The TIF flag is set in TIMx_SR register Related interrupt or DMA transfer can occur if enabled Bit...

Page 526: ...value of the counter is captured in TIMx_CCR1 register The CC1IF flag is set the corresponding interrupt or DMA request is sent if enabled The CC1OF flag is set if the CC1IF flag was already high Bit 0 UG Update generation This bit can be set by software it is automatically cleared by hardware 0 No action 1 Reinitialize the counter and generates an update of the registers Note that the prescaler c...

Page 527: ... is configured as output 01 CC2 channel is configured as input IC2 is mapped on TI2 10 CC2 channel is configured as input IC2 is mapped on TI1 11 CC2 channel is configured as input IC2 is mapped on TRC This mode is working only if an internal trigger input is selected through the TS bit TIMx_SMCR register Note CC2S bits are writable only when the channel is OFF CC2E 0 in TIMx_CCER Bit 7 OC1CE Outp...

Page 528: ...is inactive until a trigger event is detected on TRGI signal Then a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update 1001 Retrigerrable OPM mode 2 In up counting mode the channel is inactive until a trigger event is detected on TRGI signal Then a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update In...

Page 529: ...dently from the result of the comparison Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles OCFE acts only if the channel is configured in PWM1 or PWM2 mode Bits 1 0 CC1S Capture Compare 1 selection This bit field defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is configured as ...

Page 530: ...e prescaler acting on CC1 input IC1 The prescaler is reset as soon as CC1E 0 TIMx_CCER register 00 no prescaler capture is done each time an edge is detected on the capture input 01 capture is done once every 2 events 10 capture is done once every 4 events 11 capture is done once every 8 events Bits 1 0 CC1S Capture Compare 1 Selection This bit field defines the direction of the channel input outp...

Page 531: ...OC3PE Output compare 3 preload enable Bit 2 OC3FE Output compare 3 fast enable Bits 1 0 CC3S Capture Compare 3 selection This bit field defines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped on TI3 10 CC3 channel is configured as input IC3 is mapped on TI4 11 CC3 channel is configured as...

Page 532: ...Res Res Res CC6P CC6E Res Res CC5P CC5E rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC4NP Res CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 22 Reserved must be kept at reset value Bit 21 CC6P Capture Compare 6 output polarity Refer to CC1P description Bit 20 CC6E Capture Compare 6 output enable Refer to CC1E d...

Page 533: ...he polarity of TI1FP1 and TI2FP1 Refer to CC1P description Note This bit is not writable as soon as LOCK level 2 or 3 has been programmed LOCK bits in TIMx_BDTR register and CC1S 00 channel configured as output Note On channels having a complementary output this bit is preloaded If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit onl...

Page 534: ...s not inverted trigger operation in gated mode This configuration must not be used in encoder mode Note This bit is not writable as soon as LOCK level 2 or 3 has been programmed LOCK bits in TIMx_BDTR register Note On channels having a complementary output this bit is preloaded If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only ...

Page 535: ... not OCREF Polarity dead time 1 0 1 Off State output enabled with inactive state OCx CCxP OCxREF Polarity OCxN OCxREF x or CCxNP 1 1 0 OCxREF Polarity OCx OCxREF xor CCxP Off State output enabled with inactive state OCxN CCxNP 0 0 X X X Output disabled not driven by the timer anymore The output state is defined by the GPIO controller and can be High Low or Hi Z 1 0 0 0 1 Off State output enabled w...

Page 536: ... read at 0 Bits 30 16 Reserved must be kept at reset value Bits 15 0 CNT 15 0 Counter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded in the active prescaler register at each update event including when the cou...

Page 537: ... write to the TIMx_RCR register is not taken in account until the next repetition update event It means in PWM mode REP 1 corresponds to the number of PWM periods in edge aligned mode the number of half PWM period in center aligned mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1 15 0 rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r Bits 15 0 CCR1 15 0 Capture Compare...

Page 538: ... the counter TIMx_CNT and signaled on OC2 output If channel CC2 is configured as input CCR2 is the counter value transferred by the last input capture 2 event IC2 The TIMx_CCR2 register is read only and cannot be programmed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR3 15 0 rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r Bits 15 0 CCR3 15 0 Capture Compare value If cha...

Page 539: ...d in the TIMx_CCMR2 register bit OC4PE Else the preload value is copied in the active capture compare 4 register when an update event occurs The active capture compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output If channel CC4 is configured as input CCR4 is the counter value transferred by the last input capture 4 event IC4 The TIMx_CCR4 register ...

Page 540: ...DTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Note This bit cannot be modified when LOCK level 1 has been programmed LOCK bits in TIMx_BDTR register Bits 19 16 BKF 3 0 Break filter This bit field defines the frequency used to sample BRK input and t...

Page 541: ... 1 Break input BRK is active high Note This bit can not be modified as long as LOCK level 1 has been programmed LOCK bits in TIMx_BDTR register Note Any write operation to this bit takes a delay of 1 APB clock cycle to become effective Bit 12 BKE Break enable 0 Break inputs BRK and CCS clock failure event disabled 1 Break inputs BRK and CCS clock failure event enabled Note This bit cannot be modif...

Page 542: ...CK Level 1 CC Polarity bits CCxP CCxNP bits in TIMx_CCER register as long as the related channel is configured in output through the CCxS bits as well as OSSR and OSSI bits can no longer be written 11 LOCK Level 3 LOCK Level 2 CC Control bits OCxM and OCxPE bits in TIMx_CCMRx registers as long as the related channel is configured in output through the CCxS bits can no longer be written Note The LO...

Page 543: ...n this case the transfer is done to 7 registers starting from the following address TIMx_CR1 address DBA According to the configuration of the DMA Data Size several cases may occur If you configure the DMA Data Size in half words 16 bit data will be transferred to each of the 7 registers If you configure the DMA Data Size in bytes the data will also be transferred to 7 registers the first register...

Page 544: ...DBL configured in TIMx_DCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res TIM1_ETR_ADC1_ RMP rw rw Bits 31 4 Reserved must be kept at reset value Bits 1 0 TIM1_ETR_ADC1_RMP 1 0 TIM1_ETR_ADC1 remapping capability 00 TIM1_ETR is not connected ...

Page 545: ...Bits 14 12 OC6M Output compare 6 mode Bit 11 OC6PE Output compare 6 preload enable Bit 10 OC6FE Output compare 6 fast enable Bits 9 8 Reserved must be kept at reset value Bit 7 OC5CE Output compare 5 clear enable Bits 6 4 OC5M Output compare 5 mode Bit 3 OC5PE Output compare 5 preload enable Bit 2 OC5FE Output compare 5 fast enable Bits 1 0 Reserved must be kept at reset value 31 30 29 28 27 26 25...

Page 546: ... This bit can either have immediate effect or be preloaded and taken into account after an update event if preload feature is selected in TIMxCCMR1 Note it is also possible to apply this distortion on combined PWM signals Bits 28 16 Reserved must be kept at reset value Bits 15 0 CCR5 15 0 Capture Compare 5 value CCR5 is the value to be loaded in the actual capture compare 5 register preload value ...

Page 547: ... CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 TIMx_EGR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res B2G BG TG COM CC4G CC3G CC2G CC1G UG Reset value 0 0 0 0 0 0 0 0 0 0x18 TIMx_CCMR1 Output Compare mode Res Res Res Res Res Res Res OC2M 3 Res Res Res Res Res Res Res OC1M 3 OC2CE OC2M 2 0 OC2PE OC2FE CC2 S 1 0 OC1CE OC1M 2 0 OC1PE OC1F...

Page 548: ...eset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 TIMx_BDTR Res Res Res Res Res Res BK2P BK2E BK2F 3 0 BKF 3 0 MOE AOE BKP BKE OSSR OSSI LOC K 1 0 DT 7 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x48 TIMx_DCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DBL 4 0 Res Res Res DBA 4 0 Reset value 0 0 0 0 0 0 0 0 0 0 0x4C TIMx_DMAR DMAB 15 0 Reset val...

Page 549: ...es for the register boundary addresses 0x5C TIMx_CCR6 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CCR6 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 117 TIM1 register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 550: ...re available only on STM32F302xB C D E devices 21 2 TIM2 TIM3 TIM4 main features General purpose TIMx timer features include 16 bit TIM3 and TIM4 or 32 bit TIM2 up down up down auto reload counter 16 bit programmable prescaler used to divide also on the fly the counter clock frequency by any factor between 1 and 65535 Up to 4 independent channels for Input capture Output compare PWM generation Edg...

Page 551: ...7 0 IURP 5 75 06 9 25 QSXW ILOWHU HGJH GHWHFWRU DSWXUH RPSDUH UHJLVWHU 1RWHV 5HJ 3UHORDG UHJLVWHUV WUDQVIHUUHG WR DFWLYH UHJLVWHUV RQ 8 HYHQW DFFRUGLQJ WR FRQWURO ELW YHQW QWHUUXSW 0 RXWSXW XWR UHORDG UHJLVWHU DSWXUH RPSDUH UHJLVWHU 3UHVFDOHU 3UHVFDOHU QSXW ILOWHU HGJH GHWHFWRU 2XWSXW FRQWURO 8 8 2XWSXW FRQWURO 2 5 2 5 36 36 7 3 7 3 7 0 B 7 0 B 2 2 7 0 B 7 0 B QSXW ILOWHU HGJH GHWHFWRU DSWXUH RPSD...

Page 552: ...uto reload preload enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow or underflow when downcounting and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the update event is described in detail for each configuration The counter is clocked by the prescaler output CK_CNT which is enabled only wh...

Page 553: ...unter timing diagram with prescaler division change from 1 to 4 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU 06 9 06 9 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU ...

Page 554: ...e prescaler but the prescale rate does not change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sent This is to avoid generating both update and capture interrupts when clearing the counter on the capture event When an update event occurs all the r...

Page 555: ...gram internal clock divided by 2 Figure 194 Counter timing diagram internal clock divided by 4 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 ...

Page 556: ...N Figure 196 Counter timing diagram Update event when ARPE 0 TIMx_ARR not preloaded 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 1 XWR UHORDG SUHORDG UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B 55 ...

Page 557: ...lue whereas the counter of the prescaler restarts from 0 but the prescale rate doesn t change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sent This is to avoid generating both update and capture interrupts when clearing the counter on the capture...

Page 558: ...encies when TIMx_ARR 0x36 Figure 198 Counter timing diagram internal clock divided by 1 Figure 199 Counter timing diagram internal clock divided by 2 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ FQWBXGI 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 559: ...iagram internal clock divided by 4 Figure 201 Counter timing diagram internal clock divided by N 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 560: ...t is updated by hardware and gives the current direction of the counter The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register by software or by using the slave mode controller also generates an update event In this case the counter restarts counting from 0 as well as the counter of the prescaler The UEV update eve...

Page 561: ...updated with the preload value content of the TIMx_ARR register Note that if the update source is a counter overflow the auto reload is updated before the counter is reloaded so that the next period is the expected one the counter is loaded with the new value The following figures show some examples of the counter behavior for different clock frequencies Figure 203 Counter timing diagram internal ...

Page 562: ...nternal clock divided by 4 TIMx_ARR 0x36 1 Center aligned mode 2 or 3 is used with an UIF on overflow 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 1RWH HUH FHQWHUBDOLJQHG PRGH RU LV XSGDWHG ZLWK DQ 8 RQ RYHUIORZ ...

Page 563: ...ounter timing diagram Update event with ARPE 1 counter underflow 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU XQGHUIORZ 8SGDWH LQWHUUXSW IODJ 8 1 XWR UHORDG SUHORDG UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B 55 XWR UHORDG DFWLYH UHJLVWHU ...

Page 564: ...as prescaler for another timer on page 590 for more details Internal clock source CK_INT If the slave mode controller is disabled SMS 000 in the TIMx_SMCR register then the CEN DIR in the TIMx_CR1 register and UG bits in the TIMx_EGR register are actual control bits and can be changed only by software except UG which remains cleared automatically As soon as the CEN bit is written to 1 the prescale...

Page 565: ...example For example to configure the upcounter to count in response to a rising edge on the TI2 input use the following procedure For example to configure the upcounter to count in response to a rising edge on the TI2 input use the following procedure QWHUQDO FORFN RXQWHU FORFN B 17 B36 RXQWHU UHJLVWHU 1 17B 1 8 17B 1 7 06 9 WHUQDO FORFN PRGH QWHUQDO FORFN PRGH 75 B 17 B36 7 0 B60 5 606 75 7 B 7 3...

Page 566: ...y writing SMS 111 in the TIMx_SMCR register 5 Select TI2 as the input source by writing TS 110 in the TIMx_SMCR register 6 Enable the counter by writing CEN 1 in the TIMx_CR1 register When a rising edge occurs on TI2 the counter counts once and the TIF flag is set The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input Figur...

Page 567: ...ction on the ETR pin by writing ETP 0 in the TIMx_SMCR register 4 Enable external clock mode 2 by writing ECE 1 in the TIMx_SMCR register 5 Enable the counter by writing CEN 1 in the TIMx_CR1 register The counter counts once each 2 ETR rising edges The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal WHUQDO FORFN PR...

Page 568: ...iplexing and prescaler and an output stage with comparator and output control The following figure gives an overview of one Capture Compare channel The input stage samples the corresponding TIx input to generate a filtered signal TIxF Then an edge detector with polarity selection generates a signal TIxFPx which can be used as trigger input by the slave mode controller or as the capture command It ...

Page 569: ... VODYH PRGH FRQWUROOHU 7 3 6 7 3 75 IURP VODYH PRGH FRQWUROOHU 36 06 9 7 7 0 B 5 3 13 LOWHU GRZQFRXQWHU 7 0 B 05 GJH GHWHFWRU 7 B5LVLQJ 7 B DOOLQJ 7 0 B 05 7 0 B 5 7 B5LVLQJ IURP FKDQQHO 7 B DOOLQJ IURP FKDQQHO 7 I 76 DSWXUH FRPSDUH VKDGRZ UHJLVWHU RPSDUDWRU DSWXUH FRPSDUH SUHORDG UHJLVWHU RXQWHU 36 6 6 DSWXUH QSXW PRGH 6 5 5HDG 5 5HDG 5 UHDGBLQBSURJUHVV FDSWXUHBWUDQVIHU 6 6 6 5 ZULWH 5 ZULWH 5 ZU...

Page 570: ...oftware by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register CCxOF is cleared when you write it to 0 The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises To do this use the following procedure 1 Select the active input TIMx_CCR1 must be linked to the TI1 input so write the CC1S bits to 01 in the TIMx_CCMR1 register As soon as...

Page 571: ...nput capture occurs The TIMx_CCR1 register gets the value of the counter on the active transition CC1IF flag is set interrupt flag CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared An interrupt is generated depending on the CC1IE bit A DMA request is generated depending on the CC1DE bit In order to handle the overcapture it is recommended to read the ...

Page 572: ...in reset mode write the SMS bits to 100 in the TIMx_SMCR register 7 Enable the captures write the CC1E and CC2E bits to 1 in the TIMx_CCER register Figure 217 PWM input mode timing 1 The PWM input mode can be used only with the TIMx_CH1 TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller 21 3 7 Forced output mode In output mode CCxS bits 00 in th...

Page 573: ...ds a DMA request if the corresponding enable bit is set CCxDE bit in the TIMx_DIER register CCDS bit in the TIMx_CR2 register for the DMA request selection The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register In output compare mode the update event UEV has no effect on ocxref and OCx output The timing resolution is one count of ...

Page 574: ...ounter you have to initialize all the registers by setting the UG bit in the TIMx_EGR register OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register It can be programmed as active high or active low OCx output is enabled by the CCxE bit in the TIMx_CCER register Refer to the TIMx_CCERx register description for more details In PWM mode 1 or 2 TIMx_CNT and TIMx_CCRx are ...

Page 575: ...1 If the compare value is 0 then OCxREF is held at 0 Figure 219 shows some edge aligned PWM waveforms in an example where TIMx_ARR 8 Figure 219 Edge aligned PWM waveforms ARR 8 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high Refer to Downcounting mode on page 557 In PWM mode 1 the reference signal ocxref is low as long as TIMx_CNT TIMx_CCRx else it becom...

Page 576: ...Figure 220 shows some center aligned PWM waveforms in an example where TIMx_ARR 8 PWM mode is the PWM mode 1 The flag is set when the counter counts down corresponding to the center aligned mode 1 selected for CMS 01 in TIMx_CR1 register Figure 220 Center aligned PWM waveforms ARR 8 Hints on using center aligned mode When starting in center aligned mode the current up down configuration is used It...

Page 577: ...cycle and the phase shift are determined by a pair of TIMx_CCRx registers One register controls the PWM during up counting the second during down counting so that PWM is adjusted every half PWM cycle OC1REFC or OC2REFC is controlled by TIMx_CCR1 and TIMx_CCR2 OC3REFC or OC4REFC is controlled by TIMx_CCR3 and TIMx_CCR4 Asymmetric PWM mode can be selected independently on two channels one OCx output...

Page 578: ...elected independently on two channels one OCx output per pair of CCR registers by writing 1100 Combined PWM mode 1 or 1101 Combined PWM mode 2 in the OCxM bits in the TIMx_CCMRx register When a given channel is used as combined PWM channel its secondary channel must be configured in the opposite PWM mode for instance one in Combined PWM mode 1 and the other in Combined PWM mode 2 Note The OCxM 3 0...

Page 579: ... signal for a given channel can be reset by applying a high level on the ETRF input OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register OCxREF remains low until the next update event UEV occurs This function can be used only in the output compare and PWM modes It does not work in forced mode For example the OCxREF signal can be connected to the output of a comparator to be used for ...

Page 580: ...nput becomes high for both values of the OCxCE enable bit In this example the timer TIMx is programmed in PWM mode Figure 223 Clearing TIMx OCxREF Note In case of a PWM with a 100 duty cycle if CCRx ARR OCxREF is enabled again at the next counter overflow 06 9 5 RXQWHU 17 75 2 5 2 µ 2 5 2 µ RFUHIBFOUBLQW EHFRPHV KLJK RFUHIBFOUBLQW VWLOO KLJK ...

Page 581: ...ly if the compare value is different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be CNT CCRx ARR in particular 0 CCRx Figure 224 Example of one pulse mode For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin Let ...

Page 582: ...ter Then the comparison between the counter and the compare value makes the output toggle But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get If you want to output a waveform with the minimum delay you can set the OCxFE bit in the TIMx_CCMRx register Then OCxRef and OCx is forced in response to the stimulus without taking in account the co...

Page 583: ...sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal Depending on the sequence the counter counts up or down the DIR bit in the TIMx_CR1 register is modified by hardware accordingly The DIR bit is calculated at each transition on any input TI1 or TI2 whatever the counter is counting on TI1 only TI2 only or both TI1 and TI2 Encoder interf...

Page 584: ...Mx_CCMR1 register TI1FP1 mapped on TI1 CC2S 01 TIMx_CCMR2 register TI2FP2 mapped on TI2 CC1P and CC1NP 0 TIMx_CCER register TI1FP1 noninverted TI1FP1 TI1 CC2P and CC2NP 0 TIMx_CCER register TI2FP2 noninverted TI2FP2 TI2 SMS 011 TIMx_SMCR register both inputs are active on both rising and falling edges CEN 1 TIMx_CR1 register Counter is enabled Figure 226 Example of counter operation in encoder int...

Page 585: ...opy of the update interrupt flag UIF into bit 31 of the timer counter register s bit 31 TIMxCNT 31 This allows to atomically read both the counter value and a potential roll over condition signaled by the UIFCPY flag It eases the calculation of angular speed by avoiding race conditions caused for instance by a processing shared between a background task counter reading and an interrupt update inte...

Page 586: ... Write CC1P 0 and CC1NP 0 in TIMx_CCER register to validate the polarity and detect rising edges only 2 Configure the timer in reset mode by writing SMS 100 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register 3 Start the counter by writing CEN 1 in the TIMx_CR1 register The counter starts counting on the internal clock then behaves normally until TI1 rising...

Page 587: ...r is set both when the counter starts or stops The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input Figure 229 Control circuit in gated mode 1 The configuration CCxP CCxNP 1 detection of both rising and falling edges does not have any effect in gated mode because gated mode acts on a level and not on an edge Note The confi...

Page 588: ...ined reset trigger mode In this case a rising edge of the selected trigger input TRGI reinitializes the counter generates an update of the registers and starts the counter This mode is used for one pulse mode Slave mode External Clock mode 2 trigger mode The external clock mode 2 can be used in addition to another slave mode except external clock mode 1 and encoder mode In this case the ETR signal...

Page 589: ...igger mode by writing SMS 110 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register A rising edge on TI1 enables the counter and sets the TIF flag The counter then counts on ETR rising edges The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input Figure 231 Control circuit i...

Page 590: ... TIMx_CR1 register Note If OCx is selected on TIM3 as the trigger output MMS 1xx its rising edge is used to clock the counter of TIM2 Using one timer to enable another timer In this example we control the enable of TIM2 with the output compare 1 of Timer 3 Refer to Figure 232 for connections TIM2 counts on the divided internal clock only when OC1REF of TIM3 is high Both counter clock frequencies a...

Page 591: ... ratio is the same for both timers TIM2 stops when TIM3 is disabled by writing 0 to the CEN bit in the TIM3_CR1 register 1 Configure TIM3 master mode to send its Output Compare 1 Reference OC1REF signal as trigger output MMS 100 in the TIM3_CR2 register 2 Configure the TIM3 OC1REF waveform TIM3_CCMR1 register 3 Configure TIM2 to get the input trigger from TIM3 TS 010 in the TIM2_SMCR register 4 Co...

Page 592: ...unts until we write 0 to the CEN bit in the TIM2_CR1 register Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT fCK_CNT fCK_INT 3 1 Configure TIM3 master mode to send its Update Event UEV as trigger output MMS 010 in the TIM3_CR2 register 2 Configure the TIM3 period TIM3_ARR registers 3 Configure TIM2 to get the input trigger from TIM3 TS 010 in the TIM2_SMCR regi...

Page 593: ...r output MMS 001 in the TIM3_CR2 register 2 Configure TIM3 slave mode to get the input trigger from TI1 TS 100 in the TIM3_SMCR register 3 Configure TIM3 in trigger mode SMS 110 in the TIM3_SMCR register 4 Configure the TIM3 in Master Slave mode by writing MSM 1 TIM3_SMCR register 5 Configure TIM2 to get the input trigger from TIM3 TS 000 in the TIM2_SMCR register 6 Configure TIM2 in trigger mode ...

Page 594: ...s a sequence of DMA requests burst Each write into the TIMx_DMAR register is actually redirected to one of the timer registers The DBL 4 0 bits in the TIMx_DCR register set the DMA burst length The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address i e the number of transfers either in half words or in bytes The DBA 4 0 bits in the TIMx_DCR registers d...

Page 595: ...pdated once If every CCRx register is to be updated twice for example the number of data to transfer should be 6 Let s take the example of a buffer in the RAM containing data1 data2 data3 data4 data5 and data6 The data is transferred to the CCRx registers as follows on the first update DMA request data1 is transferred to CCR2 data2 is transferred to CCR3 data3 is transferred to CCR4 and on the sec...

Page 596: ...T 11 Reserved Bit 7 ARPE Auto reload preload enable 0 TIMx_ARR register is not buffered 1 TIMx_ARR register is buffered Bits 6 5 CMS Center aligned mode selection 00 Edge aligned mode The counter counts up or down depending on the direction bit DIR 01 Center aligned mode 1 The counter counts up and down alternatively Output compare interrupt flags of channels configured in output CCxS 00 in TIMx_C...

Page 597: ...rflow underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values 1 UEV disabled The Update event is not generated shadow registers keep their value ARR PSC CCRx However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller Bit 0 CEN Cou...

Page 598: ...y the trigger input there is a delay on TRGO except if the master slave mode is selected see the MSM bit description in TIMx_SMCR register 010 Update The update event is selected as trigger output TRGO For instance a master timer can then be used as a prescaler for a slave timer 011 Compare Pulse The trigger output send a positive pulse when the CC1IF flag is to be set even if it was already high ...

Page 599: ...l clock enable This bit enables External clock mode 2 0 External clock mode 2 disabled 1 External clock mode 2 enabled The counter is clocked by any active edge on the ETRF signal 1 Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF SMS 111 and TS 111 2 It is possible to simultaneously use external clock mode 2 with the following slave modes rese...

Page 600: ... fSAMPLING fCK_INT N 4 0011 fSAMPLING fCK_INT N 8 0100 fSAMPLING fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bit 7 MSM Master Slave mode 0 No...

Page 601: ... level 0010 Encoder mode 2 Counter counts up down on TI2FP2 edge depending on TI1FP1 level 0011 Encoder mode 3 Counter counts up down on both TI1FP1 and TI2FP2 edges depending on the level of the other input 0100 Reset Mode Rising edge of the selected trigger input TRGI reinitializes the counter and generates an update of the registers 0101 Gated Mode The counter clock is enabled when the trigger ...

Page 602: ...Bit 12 CC4DE Capture Compare 4 DMA request enable 0 CC4 DMA request disabled 1 CC4 DMA request enabled Bit 11 CC3DE Capture Compare 3 DMA request enable 0 CC3 DMA request disabled 1 CC3 DMA request enabled Bit 10 CC2DE Capture Compare 2 DMA request enable 0 CC2 DMA request disabled 1 CC2 DMA request enabled Bit 9 CC1DE Capture Compare 1 DMA request enable 0 CC1 DMA request disabled 1 CC1 DMA reque...

Page 603: ...o CC1OF description Bit 10 CC2OF Capture compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF Capture Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode It is cleared by software by writing it to 0 0 No overcapture has been detected 1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag ...

Page 604: ...cted polarity Bit 0 UIF Update interrupt flag This bit is set by hardware on an update event It is cleared by software 0 No update occurred 1 Update interrupt pending This bit is set by hardware when the registers are updated At overflow or underflow for TIM2 to TIM4 and if UDIS 0 in the TIMx_CR1 register When CNT is reinitialized by software using the UG bit in TIMx_EGR register if URS 0 and UDIS...

Page 605: ...terrupt or DMA request is sent if enabled If channel CC1 is configured as input The current value of the counter is captured in TIMx_CCR1 register The CC1IF flag is set the corresponding interrupt or DMA request is sent if enabled The CC1OF flag is set if the CC1IF flag was already high Bit 0 UG Update generation This bit can be set by software it is automatically cleared by hardware 0 No action 1...

Page 606: ...the used input 00 CC2 channel is configured as output 01 CC2 channel is configured as input IC2 is mapped on TI2 10 CC2 channel is configured as input IC2 is mapped on TI1 11 CC2 channel is configured as input IC2 is mapped on TRC This mode is working only if an internal trigger input is selected through the TS bit TIMx_SMCR register Note CC2S bits are writable only when the channel is OFF CC2E 0 ...

Page 607: ...formed as in PWM mode 1 and the channels becomes inactive again at the next update In down counting mode the channel is inactive until a trigger event is detected on TRGI signal Then a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update 1001 Retriggerable OPM mode 2 In up counting mode the channel is inactive until a trigger event is detected on TRGI...

Page 608: ...evel independently from the result of the comparison Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles OCFE acts only if the channel is configured in PWM1 or PWM2 mode Bits 1 0 CC1S Capture Compare 1 selection This bit field defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is co...

Page 609: ...field defines the ratio of the prescaler acting on CC1 input IC1 The prescaler is reset as soon as CC1E 0 TIMx_CCER register 00 no prescaler capture is done each time an edge is detected on the capture input 01 capture is done once every 2 events 10 capture is done once every 4 events 11 capture is done once every 8 events Bits 1 0 CC1S Capture Compare 1 selection This bit field defines the direct...

Page 610: ... to OC1M description bits 6 4 in TIMx_CCMR1 register Bit 3 OC3PE Output compare 3 preload enable Bit 2 OC3FE Output compare 3 fast enable Bits 1 0 CC3S Capture Compare 3 selection This bit field defines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped on TI3 10 CC3 channel is configured as...

Page 611: ... Res CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 CC4NP Capture Compare 4 output Polarity Refer to CC1NP description Bit 14 Reserved must be kept at reset value Bit 13 CC4P Capture Compare 4 output Polarity Refer to CC1P description Bit 12 CC4E Capture Compare 4 output enable refer to CC1E description Bit 11 CC3NP Capture Compare 3 output Polarity Refer to CC1NP description Bit 10 Reserved...

Page 612: ...is inverted trigger in gated mode encoder mode 10 reserved do not use this configuration 11 noninverted both edges Circuit is sensitive to both TIxFP1 rising and falling edges capture trigger in reset external clock or trigger mode TIxFP1 is not inverted trigger in gated mode This configuration must not be used for encoder mode Bit 0 CC1E Capture Compare 1 output enable CC1 channel configured as o...

Page 613: ...rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded in the active prescaler register at each update event including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ARR 31 16 depending o...

Page 614: ...red to the counter TIMx_CNT and signaled on OC1 output If channel CC1is configured as input CCR1 is the counter value transferred by the last input capture 1 event IC1 The TIMx_CCR1 register is read only and cannot be programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR2 31 16 depending on timers rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r 15 14 13 12 ...

Page 615: ..._CNT and signalled on OC3 output If channel CC3is configured as input CCR3 is the counter value transferred by the last input capture 3 event IC3 The TIMx_CCR3 register is read only and cannot be programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR4 31 16 depending on timers rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 616: ...e address This 5 bit vector defines the base address for DMA transfers when read write access are done through the TIMx_DMAR address DBA is defined as an offset starting from the address of the TIMx_CR1 register Example 00000 TIMx_CR1 00001 TIMx_CR2 00010 TIMx_SMCR Example Let us consider the following transfer DBL 7 transfers DBA TIMx_CR1 In this case the transfer is done to from 7 registers star...

Page 617: ...s Res CC4OF CC3OF CC2OF CC1OF Res Res TIF Res CC4IF CC3IF CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0 0 0 0 0x14 TIMx_EGR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TG Res CC4G CC3G CC2G CC1G UG Reset value 0 0 0 0 0 0 0x18 TIMx_CCMR1 Output Compare mode Res Res Res Res Res Res Res OC2M 3 Res Res Res Res Res Res Res OC1M 3 OC2CE OC2M 2 0 OC2PE...

Page 618: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x38 TIMx_CCR2 CCR2 31 16 TIM2 only reserved on the other timers CCR2 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3C TIMx_CCR3 CCR3 31 16 TIM2 only reserved on the other timers CCR3 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x40 TIMx_CCR4 CCR4 31 16 TIM2 only reserved on the other tim...

Page 619: ... synchronization TIM15 22 2 TIM15 main features TIM15 includes the following features 16 bit auto reload upcounter 16 bit programmable prescaler used to divide also on the fly the counter clock frequency by any factor between 1 and 65535 Up to 2 independent channels for Input capture Output compare PWM generation edge mode One pulse mode output Complementary outputs with programmable dead time for...

Page 620: ...nnel for Input capture Output compare PWM generation edge aligned mode One pulse mode output Complementary outputs with programmable dead time Repetition counter to update the timer registers only after a given number of cycles of the counter Break input to put the timer s output signals in the reset state or a known state Interrupt DMA generation on the following events Update counter overflow Tr...

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Page 622: ... signal Cortex M4 F LOCKUP Hardfault output COMP output QWHUQDO FORFN B 17 RXQWHU QDEOH 1 7 0 B 7 0 B 1 7 5 3RODULW VHOHFWLRQ QSXW ILOWHU HGJH VHOHFWRU QWHUQDO EUHDN HYHQW VRXUFHV XWR UHORDG UHJLVWHU 17 FRXQWHU DSWXUH FRPSDUH UHJLVWHU 7 3 5 3 UHJLVWHU 5HSHWLWLRQ FRXQWHU 7 UHJLVWHUV 7 2XWSXW FRQWURO B36 B 17 36 6WRS FOHDU RU XS GRZQ 2 5 8 8 8 2 2 1 7 0 B 7 0 B 1 8 1RWHV 5HJ 3UHORDG UHJLVWHUV WUDQVI...

Page 623: ... preload enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the update event is described in detailed for each configuration The counter is clocked by the prescaler output CK_CNT which is enabled only when the counter enable bit CEN in TIMx_C...

Page 624: ...1 Counter timing diagram with prescaler division change from 1 to 4 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU 06 9 06 9 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU ...

Page 625: ...eload registers Then no update event occurs until the UDIS bit has been written to 0 However the counter restarts from 0 as well as the counter of the prescaler but the prescale rate does not change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sen...

Page 626: ... diagram internal clock divided by 1 Figure 243 Counter timing diagram internal clock divided by 2 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 627: ...g diagram internal clock divided by 4 Figure 245 Counter timing diagram internal clock divided by N 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 ...

Page 628: ...agram update event when ARPE 1 TIMx_ARR preloaded 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 1 XWR UHORDG SUHORDG UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B 55 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 1 XWR UHORDG SUHORDG UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B 55 XWR UHORDG VKDGRZ UHJLVWHU ...

Page 629: ... prescaler register but also TIMx_CCRx capture compare registers in compare mode every N counter overflows where N is the value in the TIMx_RCR repetition counter register The repetition counter is decremented at each counter overflow The repetition counter is an auto reload type the repetition rate is maintained as defined by the TIMx_RCR register value refer to Figure 248 When the update event i...

Page 630: ...ther timer for example you can configure TIM1 to act as a prescaler for TIM15 Refer to Using one timer as prescaler for another timer on page 590 for more details Internal clock source CK_INT If the slave mode controller is disabled SMS 000 then the CEN in the TIMx_CR1 register and UG bits in the TIMx_EGR register are actual control bits and can be changed GJH DOLJQHG PRGH 8 9 8SGDWH YHQW SUHORDG ...

Page 631: ...ler Figure 249 Control circuit in normal mode internal clock divided by 1 External clock source mode 1 This mode is selected when SMS 111 in the TIMx_SMCR register The counter can count at each rising or falling edge on a selected input Figure 250 TI2 external clock connection example QWHUQDO FORFN RXQWHU FORFN B 17 B36 RXQWHU UHJLVWHU 1 17B 1 8 17B 1 7 06 9 WHUQDO FORFN PRGH QWHUQDO FORFN PRGH 75...

Page 632: ...triggering so you don t need to configure it When a rising edge occurs on TI2 the counter counts once and the TIF flag is set The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input Figure 251 Control circuit in external clock mode 1 22 4 5 Capture compare channels Each Capture Compare channel is built around a capture compa...

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Page 634: ...egister which is copied into the preload register In compare mode the content of the preload register is copied into the shadow register which is compared to the counter 06 9 2XWSXW PRGH FRQWUROOHU 17 5 17 5 7 0 B 05 2 0 2 5 2 HDG WLPH JHQHUDWRU 2 B 7 2 1B 7 7 7 0 B 75 µ µ 7 0 B 5 1 3 7 0 B 5 13 7 0 B 5 2 2XWSXW HQDEOH FLUFXLW 2 1 7 0 B 5 1 266 7 0 B 75 02 2665 2XWSXW VHOHFWRU 2 5 2 5 7R WKH PDVWH...

Page 635: ...must program a filter duration longer than these 5 clock cycles We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected sampled at fDTS frequency Then write IC1F bits to 0011 in the TIMx_CCMR1 register 3 Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register rising edge in this case 4 Program the i...

Page 636: ...e polarity for TI1FP1 used both for capture in TIMx_CCR1 and counter clear write the CC1P and CC1NP bits to 0 active on rising edge 3 Select the active input for TIMx_CCR2 write the CC2S bits to 10 in the TIMx_CCMR1 register TI1 selected 4 Select the active polarity for TI1FP2 used for capture in TIMx_CCR2 write the CC2P and CC2NP bits to 1 active on falling edge 5 Select the valid trigger input w...

Page 637: ...utput compare mode This function is used to control an output waveform or indicating when a period of time has elapsed When a match is found between the capture compare register and the counter the output compare function Assigns the corresponding output pin to a programmable value defined by the output compare mode OCxM bits in the TIMx_CCMRx register and the output polarity CCxP bit in the TIMx_...

Page 638: ...ot enabled OCxPE 0 else TIMx_CCRx shadow register is updated only at the next update event UEV An example is given in Figure 256 Figure 257 Output compare mode toggle on OC1 22 4 10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register The PWM mode can...

Page 639: ...NT TIMx_CCRx depending on the direction of the counter The TIM15 TIM16 TIM17 are capable of upcounting only Refer to Upcounting mode on page 625 In the following example we consider PWM mode 1 The reference PWM signal OCxREF is high as long as TIMx_CNT TIMx_CCRx else it becomes low If the compare value in TIMx_CCRx is greater than the auto reload value in TIMx_ARR then OCxREF is held at 1 If the c...

Page 640: ...er When a given channel is used as a combined PWM channel its complementary channel must be configured in the opposite PWM mode for instance one in Combined PWM mode 1 and the other in Combined PWM mode 2 Note The OCxM 3 0 bit field is split into two parts for compatibility reasons the most significant bit is not contiguous with the 3 least significant ones Figure 259 represents an example of sign...

Page 641: ... complementary OCx and OCxN channels with break feature TIM15 on page 667 for more details In particular the dead time is activated when switching to the idle state MOE falling down to 0 Dead time insertion is enabled by setting both CCxE and CCxNE bits and the MOE bit if the break circuit is present There is one 10 bit dead time generator for each channel From a reference waveform OCxREF it gener...

Page 642: ...irected to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register This allows you to send a specific waveform such as PWM or static active level on one output while the complementary remains at its inactive level Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead time Note When onl...

Page 643: ...t from a comparator A PVD output SRAM parity error signal Cortex M4 LOCKUP Hardfault output When exiting from reset the break circuit is disabled and the MOE bit is low The break function is enabled by setting the BKE bit in the TIMx_BDTR register The break input polarity can be selected by configuring the BKP bit in the same register BKE and BKP can be modified at the same time When the BKE and B...

Page 644: ... or CCxNE bits is high The break status flag BIF bit in the TIMx_SR register is set An interrupt can be generated if the BIE bit in the TIMx_DIER register is set A DMA request can be sent if the BDE bit in the TIMx_DIER register is set If the AOE bit in the TIMx_BDTR register is set the MOE bit is automatically set again at the next update event UEV This can be used to perform a regulation for ins...

Page 645: ...ponse to a break GHOD GHOD GHOD GHOD GHOD GHOD GHOD GHOD 2 5 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 QRW LPSOHPHQWHG 3 2 6 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 2 6 1 13 2 6 1 2 2 1 3 1 13 2 6 2 6 1 RU 2 6 2 6 1 06 9 5 02 ...

Page 646: ...ly if the compare value is different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be CNT CCRx ARR in particular 0 CCRx Figure 264 Example of one pulse mode For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin Let ...

Page 647: ...the next update event when the counter rolls over from the auto reload value back to 0 Particular case OCx fast enable In One pulse mode the edge detection on TIx input set the CEN bit which enables the counter Then the comparison between the counter and the compare value makes the output toggle But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we ...

Page 648: ...f channel 1 to be connected to the output of a XOR gate combining the two input pins TIMx_CH1 and TIMx_CH2 The XOR output can be used with all the timer input functions such as trigger or input capture It is useful for measuring the interval between the edges on two input signals as shown in Figure 265 Figure 265 Measuring time interval between edges on 2 signals 06 9 7 7 7 25 7 RXQWHU ...

Page 649: ...ng so you don t need to configure it The CC1S bits select the input capture source only CC1S 01 in the TIMx_CCMR1 register Write CC1P 0 and CC1NP 0 in the TIMx_CCER register to validate the polarity and detect rising edges only 2 Configure the timer in reset mode by writing SMS 100 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register 3 Start the counter by w...

Page 650: ... TIMx_CCER register to validate the polarity and detect low level only 2 Configure the timer in gated mode by writing SMS 101 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register 3 Enable the counter by writing CEN 1 in the TIMx_CR1 register in gated mode the counter doesn t start if CEN 0 whatever is the trigger input level The counter starts counting on th...

Page 651: ... starts counting on the internal clock and the TIF flag is set The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input Figure 268 Control circuit in trigger mode 22 4 18 Slave mode Combined reset trigger mode TIM15 only In this case a rising edge of the selected trigger input TRGI reinitializes the counter generates an updat...

Page 652: ...dress is the DMAR register address DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into the CCRx registers Number of data to transfer 3 See note below Circular mode disabled 2 Configure the DCR register by configuring the DBA and DBL bit fields as follows DBL 3 transfers DBA 0xE 3 Enable the TIMx update DMA request set the UDE bit in ...

Page 653: ... are received from the master timer 22 4 21 Debug mode When the microcontroller enters debug mode Cortex M4 F core halted the TIMx counter either continues to work normally or stops depending on DBG_TIMx_STOP configuration bit in DBG module For more details refer to Section 33 14 2 Debug support for timers watchdog bxCAN and I2C For safety purposes when the counter is stopped DBG_TIMx_STOP 1 the o...

Page 654: ..._CNT register bit 31 1 Remapping enabled UIF status bit is copied to TIMx_CNT register bit 31 Bit 10 Reserved must be kept at reset value Bits 9 8 CKD 1 0 Clock division This bitfield indicates the division ratio between the timer clock CK_INT frequency and the dead time and sampling clock tDTS used by the dead time generators and the digital filters TIx 00 tDTS tCK_INT 01 tDTS 2 tCK_INT 10 tDTS 4...

Page 655: ...ed if the UG bit is set or if a hardware reset is received from the slave mode controller Bit 0 CEN Counter enable 0 Counter disabled 1 Counter enabled Note External clock and gated mode can work only if the CEN bit has been previously set by software However trigger mode can set the CEN bit automatically by hardware 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res OIS2 OIS1N OIS1 TI1S MM...

Page 656: ...egister 010 Update The update event is selected as trigger output TRGO For instance a master timer can then be used as a prescaler for a slave timer 011 Compare Pulse The trigger output send a positive pulse when the CC1IF flag is to be set even if it was already high as soon as a capture or a compare match occurred TRGO 100 Compare OC1REF signal is used as trigger output TRGO 101 Compare OC2REF s...

Page 657: ...ect of an event on the trigger input TRGI is delayed to allow a perfect synchronization between the current timer and its slaves through TRGO It is useful if we want to synchronize several timers on a single external event Bits 6 4 TS 2 0 Trigger selection This bit field selects the trigger input to be used to synchronize the counter 000 Internal Trigger 0 ITR0 001 Internal Trigger 1 ITR1 010 Inte...

Page 658: ...nal Clock Mode 1 Rising edges of the selected trigger TRGI clock the counter 1000 Combined reset trigger mode Rising edge of the selected trigger input TRGI reinitializes the counter generates an update of the registers and starts the counter Other codes reserved Note The gated mode must not be used if TI1F_ED is selected as the trigger input TS 100 Indeed TI1F_ED outputs 1 pulse for each transiti...

Page 659: ... Reserved must be kept at reset value Bit 2 CC2IE Capture Compare 2 interrupt enable 0 CC2 interrupt disabled 1 CC2 interrupt enabled Bit 1 CC1IE Capture Compare 1 interrupt enable 0 CC1 interrupt disabled 1 CC1 interrupt enabled Bit 0 UIE Update interrupt enable 0 Update interrupt disabled 1 Update interrupt enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res CC2OF CC1OF Res BIF TIF...

Page 660: ...pture Compare 1 interrupt flag If channel CC1 is configured as output This flag is set by hardware when the counter matches the compare value It is cleared by software 0 No match 1 The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR the CC1IF bit goes high on the counter overflow If channel CC1 i...

Page 661: ...cleared by hardware 0 No action 1 When the CCPC bit is set it is possible to update the CCxE CCxNE and OCxM bits Note This bit acts only on channels that have a complementary output Bits 4 3 Reserved must be kept at reset value Bit 2 CC2G Capture Compare 2 generation Refer to CC1G description Bit 1 CC1G Capture Compare 1 generation This bit is set by software in order to generate an event it is au...

Page 662: ...S 1 0 IC2F 3 0 IC2PSC 1 0 IC1F 3 0 IC1PSC 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 25 Reserved always read as 0 Bit 24 OC2M 3 Output Compare 2 mode bit 3 Bits 23 17 Reserved always read as 0 Bit 16 OC1M 3 Output Compare 1 mode bit 3 refer to OC1M description on bits 6 4 Bit 15 Reserved always read as 0 Bits 14 12 OC2M 2 0 Output Compare 2 mode Bit 11 OC2PE Output Compare 2 prelo...

Page 663: ...REF is forced high 0110 PWM mode 1 Channel 1 is active as long as TIMx_CNT TIMx_CCR1 else inactive 0111 PWM mode 2 Channel 1 is inactive as long as TIMx_CNT TIMx_CCR1 else active 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Combined PWM mode 1 OC1REF has the same behavior as in PWM mode 1 OC1REFC is the logical OR between OC1REF and OC2REF 1101 Combined PWM mode 2 OC1REF has the sa...

Page 664: ...e level independently of the result of the comparison Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles OCFE acts only if the channel is configured in PWM1 or PWM2 mode Bits 1 0 CC1S Capture Compare 1 selection This bit field defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is c...

Page 665: ...ines the ratio of the prescaler acting on CC1 input IC1 The prescaler is reset as soon as CC1E 0 TIMx_CCER register 00 no prescaler capture is done each time an edge is detected on the capture input 01 capture is done once every 2 events 10 capture is done once every 4 events 11 capture is done once every 8 events Bits 1 0 CC1S Capture Compare 1 Selection This bit field defines the direction of th...

Page 666: ...t pin depending on MOE OSSI OSSR OIS1 OIS1N and CC1E bits Bit 1 CC1P Capture Compare 1 output polarity CC1 channel configured as output 0 OC1 active high 1 OC1 active low CC1 channel configured as input The CC1NP CC1P bits select the polarity of TI1FP1 and TI2FP1 for trigger or capture operations 00 non inverted rising edge The circuit is sensitive to TIxFP1 rising edge capture or trigger operatio...

Page 667: ...utput state 1 X X 0 0 Output Disabled not driven by the timer Hi Z OCx 0 OCxN 0 OCxN_EN 0 0 0 1 Output Disabled not driven by the timer Hi Z OCx 0 OCxREF Polarity OCxN OCxREF XOR CCxNP 0 1 0 OCxREF Polarity OCx OCxREF XOR CCxP Output Disabled not driven by the timer Hi Z OCxN 0 X 1 1 OCREF Polarity dead time Complementary to OCREF not OCREF Polarity dead time 1 0 1 Off State output enabled with in...

Page 668: ... must be kept at reset value Bits 15 0 CNT 15 0 Counter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded in the active prescaler register at each update event including when the counter is cleared through UG bit...

Page 669: ...counting from REP value As REP_CNT is reloaded with REP value only at the repetition update event U_RC any write to the TIMx_RCR register is not taken in account until the next repetition update event It means in PWM mode REP 1 corresponds to the number of PWM periods in edge aligned mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 CCR1...

Page 670: ... OC2 output If channel CC2 is configured as input CCR2 is the counter value transferred by the last input capture 2 event IC2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOE AOE BKP BKE OSSR OSSI LOCK 1 0 DTG 7 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept ...

Page 671: ...y the timer Note This bit can not be modified as soon as the LOCK level 2 has been programmed LOCK bits in TIMx_BDTR register Bit 10 OSSI Off state selection for Idle mode This bit is used when MOE 0 on channels configured as outputs See OC OCN enable description for more details Section 22 5 8 TIM15 capture compare enable register TIM15_CCER on page 665 0 When inactive OC OCN outputs are disabled...

Page 672: ...s by 2 µs steps Note This bit field can not be modified as long as LOCK level 1 2 or 3 has been programmed LOCK bits in TIMx_BDTR register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res DBL 4 0 Res Res Res DBA 4 0 rw rw rw rw rw rw rw rw rw rw Bits 15 13 Reserved must be kept at reset value Bits 12 8 DBL 4 0 DMA burst length This 5 bit field defines the length of DMA transfers the timer recogni...

Page 673: ...es Res Res Res OIS2 OIS1N OIS1 TI1S MMS 2 0 CCDS CCUS Res CCPC Reset value 0 0 0 0 0 0 0 0 0 0 0x08 TIM15_SMCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res SMS 3 Res Res Res Res Res Res Res Res MSM TS 2 0 Res SMS 2 0 Reset value 0 0 0 0 0 0 0 0 0x0C TIM15_DIER Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TDE COMDE Res Res CC2DE CC1DE UDE BIE TIE COMIE Res Res ...

Page 674: ... Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res REP 7 0 Reset value 0 0 0 0 0 0 0 0 0x34 TIM15_CCR1 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CCR1 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x38 TIM15_CCR2 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CCR2 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 TIM15_BDTR Res Res Res...

Page 675: ...cates the division ratio between the timer clock CK_INT frequency and the dead time and sampling clock tDTS used by the dead time generators and the digital filters TIx 00 tDTS tCK_INT 01 tDTS 2 tCK_INT 10 tDTS 4 tCK_INT 11 Reserved do not program this value Bit 7 ARPE Auto reload preload enable 0 TIMx_ARR register is not buffered 1 TIMx_ARR register is buffered Bits 6 4 Reserved must be kept at r...

Page 676: ... Res Res Res Res OIS1N OIS1 Res Res Res Res CCDS CCUS Res CCPC rw rw rw rw rw Bits 15 10 Reserved must be kept at reset value Bit 9 OIS1N Output Idle state 1 OC1N output 0 OC1N 0 after a dead time when MOE 0 1 OC1N 1 after a dead time when MOE 0 Note This bit can not be modified as long as LOCK level 1 2 or 3 has been programmed LOCK bits in TIMx_BKR register Bit 8 OIS1 Output Idle state 1 OC1 out...

Page 677: ...be kept at reset value Bit 13 COMDE COM DMA request enable 0 COM DMA request disabled 1 COM DMA request enabled Bits 12 10 Reserved must be kept at reset value Bit 9 CC1DE Capture Compare 1 DMA request enable 0 CC1 DMA request disabled 1 CC1 DMA request enabled Bit 8 UDE Update DMA request enable 0 Update DMA request disabled 1 Update DMA request enabled Bit 7 BIE Break interrupt enable 0 Break in...

Page 678: ...reak event occurred 1 An active level has been detected on the break input Bit 6 Reserved must be kept at reset value Bit 5 COMIF COM interrupt flag This flag is set by hardware on a COM event once the capture compare control bits CCxE CCxNE OCxM have been updated It is cleared by software 0 No COM event occurred 1 COM interrupt pending Bits 4 2 Reserved must be kept at reset value Bit 1 CC1IF Cap...

Page 679: ...his bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 A break event is generated MOE bit is cleared and BIF flag is set Related interrupt or DMA transfer can occur if enabled Bit 6 Reserved must be kept at reset value Bit 5 COMG Capture Compare control update generation This bit can be set by software it is automatically cleared by hardware ...

Page 680: ...input stage and for the output stage Output compare mode Bit 0 UG Update generation This bit can be set by software it is automatically cleared by hardware 0 No action 1 Reinitialize the counter and generates an update of the registers Note that the prescaler counter is cleared too anyway the prescaler ratio is not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Re...

Page 681: ... anytime the new value is taken in account immediately 1 Preload register on TIMx_CCR1 enabled Read Write operations access the preload register TIMx_CCR1 preload value is loaded in the active register at each update event Note 1 These bits can not be modified as long as LOCK level 3 has been programmed LOCK bits in TIMx_BDTR register and CC1S 00 the channel is configured in output 2 The PWM mode ...

Page 682: ...PLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bits 3 2 IC1PSC Input capture 1 prescaler This bit field defines the ratio of the prescaler acting on CC1 input IC1 The prescaler is reset as soon as CC1E 0 TIMx_CCER register 00 no prescaler capture is done each time an edge is detected on the capture input 01 capture is done once every 2 events 10 capture is done once every ...

Page 683: ...operations 00 Non inverted rising edge The circuit is sensitive to TIxFP1 rising edge capture or trigger operations in reset external clock or trigger mode TIxFP1 is not inverted trigger operation in gated mode 01 Inverted falling edge The circuit is sensitive to TIxFP1 falling edge capture or trigger operations in reset external clock or trigger mode TIxFP1 is inverted trigger operation in gated ...

Page 684: ...time Complementary to OCREF not OCREF Polarity dead time 1 0 1 Off State output enabled with inactive state OCx CCxP OCxREF Polarity OCxN OCxREF XOR CCxNP 1 1 0 OCxREF Polarity OCx OCxREF XOR CCxP OCx_EN 1 Off State output enabled with inactive state OCxN CCxNP OCxN_EN 1 0 0 X X X Output disabled not driven by the timer anymore The output state is defined by the GPIO controller and can be High Low...

Page 685: ...5 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded in the active prescaler register at each update event including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode 15 14 13 12 11 10 9 8 7...

Page 686: ...starts counting from REP value As REP_CNT is reloaded with REP value only at the repetition update event U_RC any write to the TIMx_RCR register is not taken in account until the next repetition update event It means in PWM mode REP 1 corresponds to the number of PWM periods in edge aligned mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15...

Page 687: ...e state depending on the OSSI bit 1 OC and OCN outputs are enabled if their respective enable bits are set CCxE CCxNE in TIMx_CCER register See OC OCN enable description for more details Section 22 5 8 TIM15 capture compare enable register TIM15_CCER on page 665 Bit 14 AOE Automatic output enable 0 MOE can be set only by software 1 MOE can be set by software or automatically at the next update eve...

Page 688: ...ed LOCK bits in TIMx_BDTR register Bits 9 8 LOCK 1 0 Lock configuration These bits offer a write protection against software errors 00 LOCK OFF No bit is write protected 01 LOCK Level 1 DTG bits in TIMx_BDTR register OISx and OISxN bits in TIMx_CR2 register and BKE BKP AOE bits in TIMx_BDTR register can no longer be written 10 LOCK Level 2 LOCK Level 1 CC Polarity bits CCxP CCxNP bits in TIMx_CCER...

Page 689: ...t be kept at reset value Bits 4 0 DBA 4 0 DMA base address This 5 bit field defines the base address for DMA transfers when read write access are done through the TIMx_DMAR address DBA is defined as an offset starting from the address of the TIMx_CR1 register Example 00000 TIMx_CR1 00001 TIMx_CR2 00010 TIMx_SMCR Example Let us consider the following transfer DBL 7 transfers and DBA TIMx_CR1 In thi...

Page 690: ...Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res TI1RMP rw rw Bits 31 2 Reserved must be kept at reset value Bits1 0 TI1_RMP Timer 16 input 1 connection This bit is set and cleared by software 00 TIM16 TI1 is connected to GPIO 01 TIM16 TI1 is connected to RTC_clock 10 TIM16 TI1 is connected to HSE 32 11 TI...

Page 691: ...1OF Res BIF Res COMIF Res Res Res CC1IF UIF Reset value 0 0 0 0 0 0x14 TIMx_EGR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res BG Res COMG Res Res Res CC1G UG Reset value 0 0 0 0 0x18 TIMx_CCMR1 Output Compare mode Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res OC1M 3 Res Res Res Res Res Res Res Res OC1CE OC1M 2 0 OC1PE OC1FE CC1 S 1 0 ...

Page 692: ...s Res MOE AOE BKP BKE OSSR OSSI LOC K 1 0 DT 7 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x48 TIMx_DCR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DBL 4 0 Res Res Res DBA 4 0 Reset value 0 0 0 0 0 0 0 0 0 0 0x4C TIMx_DMAR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DMAB 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x50 TIM16_OR Res Res Re...

Page 693: ...dependent and do not share any resources 23 2 TIM6 main features Basic timer TIM6 features include 16 bit auto reload upcounter 16 bit programmable prescaler used to divide also on the fly the counter clock frequency by any factor between 1 and 65535 Synchronization circuit to trigger the DAC Interrupt DMA generation on the update event counter overflow Figure 269 Basic timer block diagram 06 9 QW...

Page 694: ... the auto reload preload enable bit ARPE in the TIMx_CR1 register The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the update event is described in detail for each configuration The counter is clocked by the prescaler output CK_CNT which is enabled only when the counter ...

Page 695: ...ng diagram with prescaler division change from 1 to 4 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU 06 9 06 9 B36 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 3UHVFDOHU FRQWURO UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B36 3UHVFDOHU EXIIHU 3UHVFDOHU FRXQWHU ...

Page 696: ...rescaler counter both restart from 0 but the prescale rate does not change In addition if the URS update request selection bit in the TIMx_CR1 register is set setting the UG bit generates an update event UEV but the UIF flag is not set so no interrupt or DMA request is sent When an update event occurs all the registers are updated and the update flag UIF bit in the TIMx_SR register is set dependin...

Page 697: ...nal clock divided by 2 Figure 274 Counter timing diagram internal clock divided by 4 06 9 B36 17B 1 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 17B 1 ...

Page 698: ...76 Counter timing diagram update event when ARPE 0 TIMx_ARR not preloaded 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 06 9 B36 7LPHUFORFN B 17 RXQWHU UHJLVWHU 8SGDWH HYHQW 8 9 RXQWHU RYHUIORZ 8SGDWH LQWHUUXSW IODJ 8 1 XWR UHORDG SUHORDG UHJLVWHU ULWH D QHZ YDOXH LQ 7 0 B 55 ...

Page 699: ...sk counter reading and an interrupt Update Interrupt There is no latency between the assertions of the UIF and UIFCPY flags 23 3 4 Clock source The counter clock is provided by the Internal clock CK_INT source The CEN in the TIMx_CR1 register and UG bits in the TIMx_EGR register are actual control bits and can be changed only by software except for UG that remains cleared automatically As soon as ...

Page 700: ...ist of abbreviations used in register descriptions The peripheral registers can be accessed by half words 16 bit or words 32 bit 23 4 1 TIM6 control register 1 TIMx_CR1 Address offset 0x00 Reset value 0x0000 QWHUQDO FORFN RXQWHU FORFN B 17 B36 RXQWHU UHJLVWHU 1 17B 1 8 17B 1 7 06 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res UIF RE MAP Res Res Res ARPE Res Res Res OPM URS UDIS CEN rw rw ...

Page 701: ...ate interrupt or DMA request if enabled Bit 1 UDIS Update disable This bit is set and cleared by software to enable disable UEV event generation 0 UEV enabled The Update UEV event is generated by one of the following events Counter overflow underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values 1 UEV disabled Th...

Page 702: ... control a window in which a slave timer is enabled The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode When the Counter Enable signal is controlled by the trigger input there is a delay on TRGO except if the master slave mode is selected see the MSM bit description in the TIMx_SMCR register 010 Update The update event is...

Page 703: ...flow or underflow regarding the repetition counter value and if UDIS 0 in the TIMx_CR1 register When CNT is reinitialized by software using the UG bit in the TIMx_EGR register if URS 0 and UDIS 0 in the TIMx_CR1 register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res UG w Bits 15 1 Reserved must be kept at reset value Bit 0 UG Update generation Th...

Page 704: ...w rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded into the active prescaler register at each update event including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 705: ...s Reset value 0 0 0 0x08 Reserved 0x0C TIMx_DIER Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res UDE Res Res Res Res Res Res Res UIE Reset value 0 0 0x10 TIMx_SR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res UIF Reset value 0 0x14 TIMx_EGR Res Res Res Res Res Res Res Res Res Re...

Page 706: ...lemented easily through a basic input capture mode Figure 279 IR internal hardware connections with TIM16 and TIM17 All standard IR pulse modulation modes can be obtained by programming the two timer output compare channels TIM17 is used to generate the high frequency carrier signal while TIM16 generates the modulation envelope The infrared function is output on the IR_OUT pin The activation of th...

Page 707: ...which require the watchdog to react within an accurate timing window 25 2 WWDG main features Programmable free running downcounter Conditional reset Reset if watchdog activated when the downcounter value becomes less than 0x40 Reset if watchdog activated if the downcounter is reloaded outside the window see Figure 281 Early wakeup interrupt EWI triggered if enabled and the watchdog activated when ...

Page 708: ...greater than 0x3F Figure 281 describes the window watchdog process Note The T6 bit can be used to generate a software reset the WDGA bit is set and the T6 bit is cleared 25 3 3 Advanced watchdog interrupt feature The Early Wakeup Interrupt EWI can be used if specific safety operations or data logging must be performed before the actual reset is generated The EWI interrupt is enabled by setting the...

Page 709: ... timeout Warning When writing to the WWDG_CR register always write 1 in the T6 bit to avoid generating an immediate reset Figure 281 Window watchdog timing diagram The formula to calculate the timeout value is given by where tWWDG WWDG timeout tPCLK APB1 clock period measured in ms 4096 value corresponding to internal divider As an example lets assume APB1 frequency is equal to 48 MHz WDGTB 1 0 is...

Page 710: ...words 32 bit 25 4 1 Control register WWDG_CR Address offset 0x00 Reset value 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res WDGA T 6 0 rs rw Bits 31 8 Reserved must be kept at reset value Bit 7 WDGA Activation bit This bit is set by software and only cl...

Page 711: ... Bits 8 7 WDGTB 1 0 Timer base The time base of the prescaler can be modified as follows 00 CK Counter Clock PCLK div 4096 div 1 01 CK Counter Clock PCLK div 4096 div 2 10 CK Counter Clock PCLK div 4096 div 4 11 CK Counter Clock PCLK div 4096 div 8 Bits 6 0 W 6 0 7 bit window value These bits contain the window value to be compared to the downcounter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 712: ...26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 WWDG_ CR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res WDGA T 6 0 Reset value 0 1 1 1 1 1 1 1 0x04 WWDG_ CFR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res EWI WDGTB1 WDGTB0 W 6 0 Reset value 0 0 0 1 1 1 1 1 1 1 0x08 WWDG_ SR Res Res...

Page 713: ...have lower timing accuracy constraints For further information on the window watchdog refer to Section 25 on page 707 26 2 IWDG main features Free running downcounter Clocked from an independent RC oscillator can operate in Standby and Stop modes Conditional Reset Reset if watchdog activated when the downcounter value becomes lower than 0x000 Reset if watchdog activated if the downcounter is reloa...

Page 714: ...unter to the IWDG_RLR value and ease the cycle number calculation to generate the next reload Configuring the IWDG when the window option is enabled 1 Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register 2 Enable register access by writing 0x0000 5555 in the IWDG_KR register 3 Write the IWDG prescaler by programming IWDG_PR from 0 to 7 4 Write the reload register IWDG_RLR 5 Wait for the ...

Page 715: ...on Write access to the IWDG_PR IWDG_RLR and IWDG_WINR registers is protected To modify them you must first write the code 0x0000 5555 in the IWDG_KR register A write access to this register with a different value will break the sequence and register access will be protected again This implies that it is the case of the reload operation writing 0x0000 AAAA A status register is available to indicate...

Page 716: ...Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w w w w w w w w w w w w w w w w Bits 31 16 Reserved must be kept at reset value Bits 15 0 KEY 15 0 Key value write only read 0x0000 These bits must be written by software at regular intervals with the key value 0xAAAA otherwise the watchdog generates a reset when the counter reaches 0 Writing the key value 0...

Page 717: ...are write access protected see Section 26 3 5 Register access protection They are written by software to select the prescaler divider feeding the counter clock PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider 000 divider 4 001 divider 8 010 divider 16 011 divider 32 100 divider 64 101 divider 128 110 divider 256 111 divider 256 Note Reading this register returns...

Page 718: ... access protection They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register The watchdog counter counts down from this value The timeout period is a function of this value and the clock prescaler Refer to the datasheet for the timeout information The RVU bit in the IWDG_SR register must be reset in order to ...

Page 719: ... PVU r r r Bits 31 3 Reserved must be kept at reset value Bit 2 WVU Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing It is reset by hardware when the reload value update operation is completed in the VDD voltage domain takes up to 5 RC 40 kHz cycles Window value can be updated only when WVU bit is reset This bit is generated...

Page 720: ...er window value These bits are write access protected see Section 26 3 5 These bits contain the high limit of the window value to be compared to the downcounter To prevent a reset the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value Note Reading t...

Page 721: ... Res Res Res Res KEY 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 IWDG_PR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res PR 2 0 Reset value 0 0 0 0x08 IWDG_RLR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res RL 11 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0x0C IWDG_SR Res Res Res Res Res Res R...

Page 722: ...d year expressed in binary coded decimal format BCD The sub seconds value is also available in binary format Compensations for 28 29 leap year 30 and 31 day months are performed automatically Daylight saving time compensation can also be performed Additional 32 bit registers contain the programmable alarm subseconds seconds minutes hours day and date A digital calibration feature is available to c...

Page 723: ... Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt Reference clock detection a more precise second source clock 50 or 60 Hz can be used to enhance the calendar precision Accurate synchronization with an external clock using the subsecond shift feature Digital calibration circuit periodic counter correction 0 95 ppm accuracy obtained in a calibration windo...

Page 724: ...DOHU GHIDXOW 5 57 B35 5 7 03 7LPH VWDPS UHJLVWHUV 76 2XWSXW FRQWURO 57 B287 57 B 5 FDOLEUDWLRQ 57 B7 03 6PRRWK FNBVSUH GHIDXOW 57 B5 1 57 B7 03 57 B76 V QFKURQRXV ELW SUHVFDOHU GHIDXOW 57 B35 5 DOHQGDU 6KDGRZ UHJLVWHUV 57 B75 57 B 5 ODUP 57 B 50 5 57 B 50 665 FNBDSUH GHIDXOW 57 B DFNXS UHJLVWHUV DQG 57 WDPSHU FRQWURO UHJLVWHUV 6KDGRZ UHJLVWHU 57 B665 ODUP 57 B 50 5 57 B 50 665 5 8 6 3UHVFDOHU ELW ...

Page 725: ...ction RTC_TAMP3 tamper3 event detection RTC_REFIN 50 or 60 Hz reference clock input 27 3 2 GPIOs controlled by the RTC RTC_OUT RTC_TS and RTC_TAMP1 are mapped on the same pin PC13 The selection of the RTC_ALARM output is performed through the RTC_TAFCR register as follows the PC13VALUE bit is used to select whether the RTC_ALARM output is configured in push pull or open drain mode When PC13 is not...

Page 726: ...care Output PP forced 0 0 0 0 1 PC13 output data value Wakeup pin or Standard GPIO 0 0 0 0 0 Don t care 1 OD open drain PP push pull Table 131 LSE pin PC14 configuration 1 Pin configuration and function LSEON bit in RCC_BDCR register LSEBYP bit in RCC_BDCR register PC14MODE bit PC14VALUE bit LSE oscillator 1 0 Don t care Don t care LSE bypass 1 1 Don t care Don t care Output PP forced 0 Don t care...

Page 727: ...nimum division factor is 1 and the maximum division factor is 222 This corresponds to a maximum input frequency of around 4 MHz fck_apre is given by the following formula The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter When it reaches 0 RTC_SSR is reloaded with the content of PREDIV_S fck_spre is given by the following formula The ck_spre clock can be used either to up...

Page 728: ...m interrupt is enabled through the ALRAIE bit in the RTC_CR register Caution If the seconds field is selected MSK1 bit reset in RTC_ALRMAR the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior Alarm A and Alarm B if enabled by bits OSEL 1 0 in RTC_CR register can be routed to the RTC_ALARM output RTC_ALARM output polarity can be config...

Page 729: ...registers are write protected Writing to the RTC registers is enabled by writing a key into the Write Protection register RTC_WPR The following steps are required to unlock the write protection on all the RTC registers except for RTC_TAFCR RTC_BKPxR and RTC_ISR 13 8 1 Write 0xCA into the RTC_WPR register 2 Write 0x53 into the RTC_WPR register Writing a wrong key reactivates the write protection Th...

Page 730: ...larm A again Note Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization Programming the wakeup timer The following sequence is required to configure or change the wakeup timer auto reload value WUT 15 0 in RTC_WUTR 1 Clear WUTE in RTC_CR to disable the wakeup timer 2 Poll WUTWF until it is set in RTC_ISR to make sure the access to ...

Page 731: ... After synchronization refer to Section 27 3 10 RTC synchronization the software must wait until RSF is set before reading the RTC_SSR RTC_TR and RTC_DR registers When the BYPSHAD control bit is set in the RTC_CR register bypass shadow registers Reading the calendar registers gives the values from the calendar counters directly thus eliminating the need to wait for the RSF bit to be set This is es...

Page 732: ...ith PREDIV_S set to 0x7FFF However increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler output at 1 Hz In this way the frequency of the asynchronous prescaler output increases which may increase the RTC dynamic consumption The RTC can be finely adjusted using the RTC shift control register RTC_SHIFTR Writing to RTC_SHIFTR can shift either delay o...

Page 733: ...sing a large 7 ck_apre period detection window centered on the ck_spre edge When the RTC_REFIN detection is enabled PREDIV_A and PREDIV_S must be set to their default values PREDIV_A 0x007F PREVID_S 0x00FF Note RTC_REFIN clock detection is not available in Standby mode 27 3 12 RTC smooth digital calibration The RTC frequency can be digitally calibrated with a resolution of about 0 954 ppm with a r...

Page 734: ...les which is equivalent to adding 256 clock cycles every 32 seconds As a result between 255 and 256 clock pulses corresponding to a calibration range from 243 3 to 244 1 ppm can effectively be added during each 32 second cycle using only the CALM bits With a nominal RTCCLK frequency of 32768 Hz when PREDIV_A equals 1 division factor of 2 PREDIV_S should be set to 16379 rather than 16383 4 less The...

Page 735: ...value to RTC_CALR if necessary RECALPF is then automatically set to 1 3 Within three ck_apre cycles after the write operation to RTC_CALR the new calibration settings take effect 27 3 13 Time stamp function Time stamp is enabled by setting the TSE bit of RTC_CR register to 1 The calendar is saved in the time stamp registers RTC_TSSSR RTC_TSTR RTC_TSDR when a time stamp event is detected on the RTC...

Page 736: ... detection input is associated with a flag TAMPxF in the RTC_ISR register The TAMPxF flag is asserted after the tamper event on the pin with the latency provided below 3 ck_apre cycles when TAMPFLT differs from 0x0 Level detection with filtering 3 ck_apre cycles when TAMPTS 1 Timestamp on tamper event No latency when TAMPFLT 0x0 Edge detection and TAMPTS 0 A new tamper occurring on the same pin du...

Page 737: ...ing on RTC_TAMPx inputs Level detection with filtering is performed by setting TAMPFLT to a non zero value A tamper detection event is generated when either 2 4 or 8 depending on TAMPFLT consecutive samples are observed at the level designated by the TAMPxTRG bits The RTC_TAMPx inputs are precharged through the I O internal pull up resistance before its state is sampled unless disabled by setting ...

Page 738: ... RTC_ALARM output is enabled it has priority over RTC_CALIB COE bit is don t care and must be kept cleared When the RTC_CALIB or RTC_ALARM output is selected the RTC_OUT pin is automatically configured in output alternate function 27 4 RTC low power modes 27 5 RTC interrupts All RTC interrupts are connected to the NVIC controller Refer to Section 13 2 Extended interrupts and events controller EXTI...

Page 739: ... RTC to detect the RTC Wakeup timer event 27 6 RTC registers Refer to Section 2 1 on page 42 of the reference manual for a list of abbreviations used in register descriptions The peripheral registers can be accessed by words 32 bit 27 6 1 RTC time register RTC_TR The RTC_TR is the calendar time shadow register This register must be written in initialization mode only Refer to Calendar initializati...

Page 740: ...18 17 16 Res Res Res Res Res Res Res Res Res PM HT 1 0 HU 3 0 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res MNT 2 0 MNU 3 0 Res ST 2 0 SU 3 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 23 Reserved must be kept at reset value Bit 22 PM AM PM notation 0 AM or 24 hour format 1 PM Bits 21 20 HT 1 0 Hour tens in BCD format Bits 19 16 HU 3 0 Hour units in BCD format Bit 15 Reserv...

Page 741: ...s in BCD format Bits 19 16 YU 3 0 Year units in BCD format Bits 15 13 WDU 2 0 Week day units 000 forbidden 001 Monday 111 Sunday Bit 12 MT Month tens in BCD format Bits 11 8 MU Month units in BCD format Bits 7 6 Reserved must be kept at reset value Bits 5 4 DT 1 0 Date tens in BCD format Bits 3 0 DU 3 0 Date units in BCD format ...

Page 742: ...ut polarity This bit is used to configure the polarity of RTC_ALARM output 0 The pin is high when ALRAF ALRBF WUTF is asserted depending on OSEL 1 0 1 The pin is low when ALRAF ALRBF WUTF is asserted depending on OSEL 1 0 Bit 19 COSEL Calibration output selection When COE 1 this bit selects which signal is output on RTC_CALIB 0 Calibration output is 512 Hz with default prescaler setting 1 Calibrat...

Page 743: ... Alarm A interrupt disabled 1 Alarm A interrupt enabled Bit 11 TSE timestamp enable 0 timestamp disable 1 timestamp enable Bit 10 WUTE Wakeup timer enable 0 Wakeup timer disabled 1 Wakeup timer enabled Bit 9 ALRBE Alarm B enable 0 Alarm B disabled 1 Alarm B enabled Bit 8 ALRAE Alarm A enable 0 Alarm A disabled 1 Alarm A enabled Bit 7 Reserved must be kept at reset value Bit 6 FMT Hour format 0 24 ...

Page 744: ...register write protection on page 729 Caution TSE must be reset when TSEDGE is changed to avoid spuriously setting of TSF Bit 4 REFCKON RTC_REFIN reference clock detection enable 50 or 60 Hz 0 RTC_REFIN detection disabled 1 RTC_REFIN detection enabled Note PREDIV_S must be 0x00FF Bit 3 TSEDGE Time stamp event active edge 0 RTC_TS input rising edge generates a time stamp event 1 RTC_TS input fallin...

Page 745: ...he fly Bit 15 TAMP3F RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input It is cleared by software writing 0 Bit 14 TAMP2F RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input It is cleared by software writing 0 Bit 13 TAMP1F RTC_TAMP1 detection flag This flag is set...

Page 746: ...sters update is allowed Bit 5 RSF Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers RTC_SSRx RTC_TRx and RTC_DRx This bit is cleared by hardware in initialization mode while a shift operation is pending SHPF 1 or when in bypass shadow register mode BYPSHAD 1 This bit can also be cleared by software It is cleared either ...

Page 747: ... is cleared and WUTWF is set 0 Wakeup timer configuration update not allowed 1 Wakeup timer configuration update allowed Bit 1 ALRBWF Alarm B write flag This bit is set by hardware when Alarm B values can be changed after the ALRBE bit has been set to 0 in RTC_CR It is cleared by hardware in initialization mode 0 Alarm B update not allowed 1 Alarm B update allowed Bit 0 ALRAWF Alarm A write flag T...

Page 748: ...eset value 0x007F 00FF System reset not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res PREDIV_A 6 0 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res PREDIV_S 14 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 23 Reserved must be kept at reset value Bits 22 16 PREDIV_A 6 0 Asynchronous prescaler factor This is the asynchronous divis...

Page 749: ...es Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WUT 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 0 WUT 15 0 Wakeup auto reload value bits When the wakeup timer is enabled WUTE set to 1 the WUTF flag is set every WUT 15 0 1 ck_wut cycles The ck_wut period is selected through WUCKSEL 2 0 bits of the RTC_CR register When WUCKSEL 2 1 the...

Page 750: ...he date day match 1 Date day don t care in Alarm A comparison Bit 30 WDSEL Week day selection 0 DU 3 0 represents the date units 1 DU 3 0 represents the week day DT 1 0 is don t care Bits 29 28 DT 1 0 Date tens in BCD format Bits 27 24 DU 3 0 Date units or day in BCD format Bit 23 MSK3 Alarm A hours mask 0 Alarm A set if the hours match 1 Hours don t care in Alarm A comparison Bit 22 PM AM PM nota...

Page 751: ...e and day match 1 Date and day don t care in Alarm B comparison Bit 30 WDSEL Week day selection 0 DU 3 0 represents the date units 1 DU 3 0 represents the week day DT 1 0 is don t care Bits 29 28 DT 1 0 Date tens in BCD format Bits 27 24 DU 3 0 Date units or day in BCD format Bit 23 MSK3 Alarm B hours mask 0 Alarm B set if the hours match 1 Hours don t care in Alarm B comparison Bit 22 PM AM PM no...

Page 752: ...KEY Write protection key This byte is written by software Reading this byte always returns 0x00 Refer to RTC register write protection for a description of how to unlock RTC register write protection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SS 15 0 r r r r r r r r r r r r r r r r Bits31 16 ...

Page 753: ...d to be used with SUBFS see description below in order to effectively add a fraction of a second to the clock in an atomic operation Bits 30 15 Reserved must be kept at reset value Bits 14 0 SUBFS Subtract a fraction of a second These bits are write only and is always read as zero Writing to this bit has no effect when a shift operation is pending when SHPF 1 in RTC_ISR The value which is written ...

Page 754: ... PM HT 1 0 HU 3 0 r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res MNT 2 0 MNU 3 0 Res ST 2 0 SU 3 0 r r r r r r r r r r r r r r Bits 31 23 Reserved must be kept at reset value Bit 22 PM AM PM notation 0 AM or 24 hour format 1 PM Bits 21 20 HT 1 0 Hour tens in BCD format Bits 19 16 HU 3 0 Hour units in BCD format Bit 15 Reserved must be kept at reset value Bits 14 12 MNT 2 0 Minute tens in ...

Page 755: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDU 1 0 MT MU 3 0 Res Res DT 1 0 DU 3 0 r r r r r r r r r r r r r r Bits 31 16 Reserved must be kept at reset value Bits 15 13 WDU 1 0 Week day units Bit 12 MT Month tens in BCD format Bits 11 8 MU 3 0 Month units in BCD format Bits 7 6 Reserved must be ...

Page 756: ...offset 0x38 Backup domain reset value 0x0000 0000 System reset not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SS 15 0 r r r r r r r r r r r r r r r r Bits 31 16 Reserved must be kept at reset value Bits 15 0 SS Sub second value SS 15 0 is the value of the synchronous prescaler counte...

Page 757: ... 32768 Hz the number of RTCCLK pulses added during a 32 second window is calculated as follows 512 CALP CALM Refer to Section 27 3 12 RTC smooth digital calibration Bit 14 CALW8 Use an 8 second calibration cycle period When CALW8 is set to 1 the 8 second calibration cycle period is selected Note CALM 1 0 are stuck at 00 when CALW8 1 Refer to Section 27 3 12 RTC smooth digital calibration Bit 13 CA...

Page 758: ... PC15MODE 1 PC15VALUE configures the PC15 output data Bit 21 PC14MODE PC14 mode 0 PC14 is controlled by the GPIO configuration registers Consequently PC14 is floating in Standby mode 1 PC14 is forced to push pull output if LSE is disabled Bit 20 PC14VALUE PC14 value If the LSE is disabled and PC14MODE 1 PC14VALUE configures the PC14 output data Bit 19 PC13MODE PC13 mode 0 PC13 is controlled by the...

Page 759: ...TCCLK 16384 2 Hz when RTCCLK 32768 Hz 0x2 RTCCLK 8192 4 Hz when RTCCLK 32768 Hz 0x3 RTCCLK 4096 8 Hz when RTCCLK 32768 Hz 0x4 RTCCLK 2048 16 Hz when RTCCLK 32768 Hz 0x5 RTCCLK 1024 32 Hz when RTCCLK 32768 Hz 0x6 RTCCLK 512 64 Hz when RTCCLK 32768 Hz 0x7 RTCCLK 256 128 Hz when RTCCLK 32768 Hz Bit 7 TAMPTS Activate timestamp on tamper detection event 0 Tamper detection event does not cause a timesta...

Page 760: ...nable 0 Tamper interrupt disabled 1 Tamper interrupt enabled Bit 1 TAMP1TRG Active level for RTC_TAMP1 input If TAMPFLT 00 0 RTC_TAMP1 input staying low triggers a tamper detection event 1 RTC_TAMP1 input staying high triggers a tamper detection event if TAMPFLT 00 0 RTC_TAMP1 input rising edge triggers a tamper detection event 1 RTC_TAMP1 input falling edge triggers a tamper detection event Bit 0...

Page 761: ...onds for Alarm A The alarm is set when the seconds unit is incremented assuming that the rest of the fields match 1 SS 14 1 are don t care in Alarm A comparison Only SS 0 is compared 2 SS 14 2 are don t care in Alarm A comparison Only SS 1 0 are compared 3 SS 14 3 are don t care in Alarm A comparison Only SS 2 0 are compared 12 SS 14 12 are don t care in Alarm A comparison SS 11 0 are compared 13 ...

Page 762: ...or Alarm B The alarm is set when the seconds unit is incremented assuming that the rest of the fields match 0x1 SS 14 1 are don t care in Alarm B comparison Only SS 0 is compared 0x2 SS 14 2 are don t care in Alarm B comparison Only SS 1 0 are compared 0x3 SS 14 3 are don t care in Alarm B comparison Only SS 2 0 are compared 0xC SS 14 12 are don t care in Alarm B comparison SS 11 0 are compared 0x...

Page 763: ... 3 0 Res MNT 2 0 MNU 3 0 Res ST 2 0 SU 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 RTC_DR Res Res Res Res Res Res Res Res YT 3 0 YU 3 0 WDU 2 0 MT MU 3 0 Res Res DT 1 0 DU 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0x08 RTC_CR Res Res Res Res Res Res Res Res COE OSE L 1 0 POL COSEL BKP SUB1H ADD1H TSIE WUTIE ALRBIE ALRAIE TSE WUTE ALRBE ALRAE Res FMT BYPSHAD REF...

Page 764: ...0 0 0 0 0 0 0 0x38 RTC_TSSSR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res SS 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3C RTC_ CALR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CALP CALW8 CALW16 Res Res Res Res CALM 8 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x40 RTC_TAFCR Res Res Res Res Res Res Res Res PC15MODE PC15MODE PC14VALUE PC14MODE PC13VALUE PC1...

Page 765: ... also SMBus system management bus and PMBus power management bus compatible DMA can be used to reduce CPU overload 28 2 I2C main features I2C bus specification rev03 compatibility Slave and master modes Multimaster capability Standard mode up to 100 kHz Fast mode up to 400 kHz Fast mode Plus up to 1 MHz 7 bit and 10 bit addressing mode Multiple 7 bit slave addresses 2 addresses 1 with configurable...

Page 766: ...set of features implemented in I2C1 I2C3 and I2C3 I2C2 I2C3 and I2C4 I2C3 28 4 I2C functional description In addition to receiving and transmitting data this interface converts it from serial to parallel format and vice versa The interrupts are enabled or disabled by software The interface is connected to the I2C bus by a data pin SDA and by a clock pin SCL It can be connected with a standard up t...

Page 767: ...selected for either of the following two clock sources HSI high speed internal oscillator default value SYSCLK system clock Refer to Section 9 Reset and clock control RCC for more details 06 9 6 6 6 83 1 5 B 6 IURP UHVHW DQG FORFN FRQWUROOHU DNHXS RQ DGGUHVV PDWFK 60 86 3 JHQHUDWLRQ FKHFN 6KLIW UHJLVWHU DWD FRQWURO 60 XV 7LPHRXW FKHFN ORFN FRQWURO 0DVWHU FORFN JHQHUDWLRQ 6ODYH FORFN VWUHWFKLQJ 60 ...

Page 768: ...receiver Master transmitter Master receiver By default it operates in slave mode The interface automatically switches from slave to master when it generates a START condition and from master to slave if an arbitration loss or a STOP generation occurs allowing multimaster capability Communication flow In Master mode the I2C interface initiates a data transfer and generates the clock signal A serial...

Page 769: ...I2C interface RM0365 769 1080 DocID025202 Rev 7 Figure 285 I2 C bus protocol Acknowledge can be enabled or disabled by software The I2C interface addresses can be selected by software 06 9 6 6 6WDUW FRQGLWLRQ 6WRS FRQGLWLRQ 06 ...

Page 770: ...spikes with a pulse width up to 50 ns in Fast mode and Fast mode Plus The user can disable this analog filter by setting the ANFOFF bit and or select a digital filter by configuring the DNF 3 0 bit in the I2C_CR1 register When the digital filter is enabled the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x I2CCLK periods This allows to suppress...

Page 771: ...egister The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 286 Setup and hold timings 06Y 9 W6 1 6 IDOOLQJ HGJH LQWHUQDO GHWHFWLRQ 6 6 VWUHWFKHG ORZ E WKH 6 RXWSXW GHOD 6 6 d K d D W 7 6 6 VWUHWFKHG ORZ E WKH 6 6 d dhW d D W68 67 DWD KROG WLPH LQ FDVH RI WUDQVPLVVLRQ WKH GDWD LV VHQW RQ 6 RXWSXW DIWHU WKH 6 GHOD LI LW LV DOUHDG DYDLODEOH LQ ...

Page 772: ...s not stretch the LOW period tLOW of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock The SDA rising edge is usually the worst case so in this case the previous equation becomes SDADEL tVD DAT max tr max 260 ns DNF 4 x tI2CCLK PRESC 1 x tI2CCLK Note This condition can be violated when NOSTRETCH 0 because the device stretches SCL l...

Page 773: ...ected a delay is inserted before releasing the SCL output This delay is tSCLL SCLL 1 x tPRESC where tPRESC PRESC 1 x tI2CCLK tSCLL impacts the SCL low time tLOW When the SCL rising edge is internally detected a delay is inserted before forcing the SCL output to low level This delay is tSCLH SCLH 1 x tPRESC where tPRESC PRESC 1 x tI2CCLK tSCLH impacts the SCL high time tHIGH Refer to I2C master ini...

Page 774: ... not impacted Here is the list of impacted register bits 1 I2C_CR2 register START STOP NACK 2 I2C_ISR register BUSY TXE TXIS RXNE ADDR NACKF TCR TC STOPF BERR ARLO OVR and in addition when the SMBus feature is supported 1 I2C_CR2 register PECBYTE 2 I2C_ISR register PECERR TIMEOUT ALERT PE must be kept low during at least 3 APB clock cycles in order to perform the software reset This is ensured by ...

Page 775: ...hen the complete data byte is received the shift register is copied into I2C_RXDR register if it is empty RXNE 0 If RXNE 1 meaning that the previous received data byte has not yet been read the SCL line is stretched low until I2C_RXDR is read The stretch is inserted between the 8th and 9th SCL pulse before the Acknowledge pulse Figure 288 Data reception XX 3HIFT REGISTER DATA DATA XX DATA 28 PULSE...

Page 776: ...e byte counter is always used in master mode By default it is disabled in slave mode but it can be enabled by software by setting the SBC Slave Byte Control bit in the I2C_CR2 register The number of bytes to be transferred is programmed in the NBYTES 7 0 bit field in the I2C_CR2 register If the number of bytes to be transferred NBYTES is greater than 255 or if a receiver wants to control the ackno...

Page 777: ...ng mode by setting the OA1MODE bit in the I2C_OAR1 register OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register If additional slave addresses are required the 2nd slave address OA2 can be configured Up to 7 OA2 LSB can be masked by configuring the OA2MSK 2 0 bits in the I2C_OAR2 register Therefore for OA2MSK configured from 1 to 6 only OA2 7 2 OA2 7 3 OA2 7 4 OA2 7 5 OA2 7 6 or OA2 7 ...

Page 778: ... This stretch is released when I2C_RXDR is read When TCR 1 in Slave Byte Control mode reload mode SBC 1 and RELOAD 1 meaning that the last data byte has been transferred This stretch is released when then TCR is cleared by writing a non zero value in the NBYTES 7 0 field After SCL falling edge detection the I2C stretches SCL low during SDADEL SCLDEL 1 x PRESC 1 1 x tI2CCLK Slave without clock stre...

Page 779: ... set stretching the SCL signal low between the 8th and 9th SCL pulses The user can read the data from the I2C_RXDR register and then decide to acknowledge it or not by configuring the ACK bit in the I2C_CR2 register The SCL stretch is released by programming NBYTES to a non zero value the acknowledge or not acknowledge is sent and next byte can be received NBYTES can be loaded with a value greater...

Page 780: ...e TXIS bit is not set when a NACK is received When a STOP is received and the STOPIE bit is set in the I2C_CR1 register the STOPF flag is set in the I2C_ISR register and an interrupt is generated In most applications the SBC bit is usually programmed to 0 In this case If TXE 0 when the slave address is received ADDR 1 the user can choose either to send the content of the I2C_TXDR register as the f...

Page 781: ...sent the I2C_TXDR register can be flushed by setting the TXE bit in order to program a new data byte The STOPF bit must be cleared only after these actions in order to guarantee that they are executed before the first data transmission starts following the address acknowledge If STOPF is still set when the first data transmission starts an underrun error will be generated the OVR flag is set If a ...

Page 782: ...ated circuit I2C interface 834 Figure 292 Transfer sequence flowchart for I2C slave transmitter NOSTRETCH 1 D ϭϵϴϱϮsϮ 6ODYH LQLWLDOL DWLRQ 6ODYH WUDQVPLVVLRQ 2SWLRQDO 6HW B 65 7 DQG B 65 7 6 ULWH B7 5 7 7 B 65 6723 1R HV B 65 7 6 HV 1R 6HW B 5 6723 ...

Page 783: ...Q UHFHSWLRQ 6 VWUHWFK 9 9 9 9 DPSOH VODYH WUDQVPLWWHU E WHV 12675 7 9 ZU GDWD 9 7 6 65 ZU GDWD 9 7 6 65 ZU GDWD 9 7 6 65 ZU GDWD QRW VHQW 9 6723 65 RSWLRQDO VHW 7 DQG 7 6 VHW 6723 7 6 7 6 7 OHJHQG WUDQVPLVVLRQ UHFHSWLRQ 6 VWUHWFK 9 9 9 7 6 9 6723 9 DPSOH VODYH WUDQVPLWWHU E WHV ZLWKRXW VW GDWD IOXVK 12675 7 9 5 65 FKHFN 2 DQG 5 VHW 5 9 7 6 65 ZU GDWD 9 7 6 65 ZU GDWD 9 7 6 65 ZU GDWD QRW VHQW 5 7 ...

Page 784: ...XIE is set in I2C_CR1 RXNE is cleared when I2C_RXDR is read When a STOP is received and STOPIE is set in I2C_CR1 STOPF is set in I2C_ISR and an interrupt is generated Figure 294 Transfer sequence flowchart for slave receiver with NOSTRETCH 0 D ϭϵϴϱϱsϮ 6ODYH LQLWLDOL DWLRQ 6ODYH UHFHSWLRQ 5HDG 2 DQG 5 LQ B 65 6HW B 5 5 ULWH B5 5 5 7 B 65 5 1R HV B 65 5 1 HV 1R 6 VWUHWFKHG ...

Page 785: ...G B5 5 5 7 B 65 6723 1R HV B 65 5 1 HV 1R 6HW B 5 6723 06 9 9 5 65 FKHFN 2 DQG 5 VHW 5 9 5 1 65 UG GDWD 9 5 1 65 UG GDWD 9 5 1 65 UG GDWD 5 5 1 5 1 5 1 OHJHQG WUDQVPLVVLRQ UHFHSWLRQ 6 VWUHWFK 9 9 9 9 5 1 65 UG GDWD 9 5 1 65 UG GDWD 9 5 1 65 UG GDWD 9 6723 65 VHW 6723 5 1 OHJHQG WUDQVPLVVLRQ UHFHSWLRQ 6 VWUHWFK 5 1 9 DPSOH VODYH UHFHLYHU E WHV 12675 7 4 GGUHVV GDWD GDWD GDWD 1 DPSOH VODYH UHFHLYHU ...

Page 786: ...zation to the I2CxCLK clock The I2C releases SCL to high level once the SCLL counter reaches the value programmed in the SCLL 7 0 bits in the I2C_TIMINGR register The I2C detects its own SCL high level after a tSYNC2 delay depending on the SCL rising edge SCL input noise filters analog digital and SCL synchronization to I2CxCLK clock The I2C ties SCL to low level once the SCLH counter is reached r...

Page 787: ...O GHWHFWHG 6 FRXQWHU VWDUWV 6 6 6 PDVWHU FORFN JHQHUDWLRQ 6 UHOHDVHG 6 ORZ OHYHO GHWHFWHG 6 FRXQWHU VWDUWV 6 GULYHQ ORZ 6 W6 1 6 PDVWHU FORFN V QFKURQL DWLRQ 6 6 GULYHQ ORZ E DQRWKHU GHYLFH 6 ORZ OHYHO GHWHFWHG 6 FRXQWHU VWDUWV 6 UHOHDVHG 6 6 6 KLJK OHYHO GHWHFWHG 6 FRXQWHU VWDUWV 6 KLJK OHYHO GHWHFWHG 6 FRXQWHU VWDUWV 6 ORZ OHYHO GHWHFWHG 6 FRXQWHU VWDUWV 6 6 GULYHQ ORZ E DQRWKHU GHYLFH 6 6 KLJK ...

Page 788: ...h 0xFF The user must then set the START bit in I2C_CR2 register Changing all the above bits is not allowed when START bit is set Then the master automatically sends the START condition followed by the slave address as soon as it detects that the bus is free BUSY 0 and after a delay of tBUF In case of an arbitration loss the master automatically switches back to slave mode and can acknowledge its o...

Page 789: ... mode and the START bit is cleared when the ADDRCF bit is set Note The same procedure is applied for a Repeated Start condition In this case BUSY 1 Figure 298 Master initialization flowchart Initialization of a master receiver addressing a 10 bit address slave If the slave address is in 10 bit format the user can choose to send the complete read sequence by clearing the HEAD10R bit in the I2C_CR2 ...

Page 790: ...AD bit in the I2C_CR2 register In this case when NBYTES data have been transferred the TCR flag is set and the SCL line is stretched low until NBYTES 7 0 is written to a non zero value The TXIS flag is not set when a NACK is received When RELOAD 0 and NBYTES data have been transferred In automatic end mode AUTOEND 1 a STOP is automatically sent In software end mode AUTOEND 0 the TC flag is set and...

Page 791: ...nce flowchart for I2C master transmitter for N 255 bytes D ϭϵϴϲϬsϮ 0DVWHU LQLWLDOL DWLRQ 0DVWHU WUDQVPLVVLRQ ULWH B7 5 B 65 7 6 1R HV B 65 1 HV 1R 1 7 6 1 872 1 IRU 5 67 57 IRU 6723 RQILJXUH VODYH DGGUHVV 6HW B 5 67 57 QG 1 7 6 WUDQVPLWWHG B 65 7 HV QG 1R HV 1R 6HW B 5 67 57 ZLWK VODYH DGGHVV 1 7 6 ...

Page 792: ...C master transmitter for N 255 bytes 06 9 0DVWHU LQLWLDOL DWLRQ 0DVWHU WUDQVPLVVLRQ ULWH B7 5 B 65 7 6 1R HV B 65 1 HV 1R 1 7 6 1 1 5 2 RQILJXUH VODYH DGGUHVV 6HW B 5 67 57 QG 1 7 6 WUDQVPLWWHG B 65 7 HV QG 1R HV 1R 6HW B 5 67 57 ZLWK VODYH DGGHVV 1 7 6 B 65 7 5 HV 1 1 7 6 1 1 5 2 872 1 IRU 5 67 57 IRU 6723 6 1 7 6 1 1 5 2 ...

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Page 794: ...itten to a non zero value When RELOAD 0 and NBYTES 7 0 data have been transferred In automatic end mode AUTOEND 1 a NACK and a STOP are automatically sent after the last received byte In software end mode AUTOEND 0 a NACK is automatically sent after the last received byte the TC flag is set and the SCL line is stretched low in order to allow software actions A RESTART condition can be requested by...

Page 795: ...ransfer sequence flowchart for I2C master receiver for N 255 bytes D ϭϵϴϲϯsϮ 0DVWHU LQLWLDOL DWLRQ 0DVWHU UHFHSWLRQ 5HDG B5 5 B 65 5 1 1R HV 1 7 6 1 872 1 IRU 5 67 57 IRU 6723 RQILJXUH VODYH DGGUHVV 6HW B 5 67 57 1 7 6 UHFHLYHG B 65 7 HV QG 1R HV 1R 6HW B 5 67 57 ZLWK VODYH DGGHVV 1 7 6 ...

Page 796: ...t for I2C master receiver for N 255 bytes D ϭϵϴϲϰsϮ 0DVWHU LQLWLDOL DWLRQ 0DVWHU UHFHSWLRQ 5HDG B5 5 B 65 5 1 1R HV 1 7 6 1 1 5 2 RQILJXUH VODYH DGGUHVV 6HW B 5 67 57 1 7 6 UHFHLYHG B 65 7 HV QG 1R HV 1R 6HW B 5 67 57 ZLWK VODYH DGGHVV 1 7 6 B 65 7 5 HV 1 1 7 6 1 1 5 2 872 1 IRU 5 67 57 IRU 6723 6 1 7 6 1 1 5 2 1R ...

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Page 798: ... SCLDEL 0x4 0x4 0x3 0x1 tSCLDEL 5x250 ns 1250 ns 5x250 ns 1250 ns 4x125 ns 500 ns 2x125 ns 250 ns 1 SCL period tSCL is greater than tSCLL tSCLH due to SCL internal detection delay Values provided for tSCL are examples only 2 tSYNC1 tSYNC2 minimum value is 4 x tI2CCLK 500 ns Example with tSYNC1 tSYNC2 1000 ns 3 tSYNC1 tSYNC2 minimum value is 4 x tI2CCLK 500 ns Example with tSYNC1 tSYNC2 750 ns 4 tS...

Page 799: ...vided for tSCL are examples only 2 tSYNC1 tSYNC2 minimum value is 4 x tI2CCLK 250 ns Example with tSYNC1 tSYNC2 1000 ns 3 tSYNC1 tSYNC2 minimum value is 4 x tI2CCLK 250 ns Example with tSYNC1 tSYNC2 750 ns 4 tSYNC1 tSYNC2 minimum value is 4 x tI2CCLK 250 ns Example with tSYNC1 tSYNC2 500 ns Table 143 Examples of timings settings for fI2CCLK 48 MHz Parameter Standard mode Sm Fast mode Fm Fast mode ...

Page 800: ...CR1 register The ARP commands should be implemented by the user software Arbitration is also performed in slave mode for ARP support For more details of the SMBus Address Resolution Protocol refer to SMBus specification version 2 0 http smbus org Received Command and Data acknowledge control A SMBus receiver must be able to NACK each received command or data In order to allow the ACK control in sl...

Page 801: ...lated PEC Timeouts This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification version 2 0 Table 144 SMBus timeout specifications Symbol Parameter Limits Unit Min Max tTIMEOUT Detect clock low timeout 25 35 ms tLOW SEXT 1 1 tLOW SEXT is the cumulative time a given slave device is allowed to extend the clock cycles in one message from the initi...

Page 802: ...to ensure that a transfer is not currently in progress The peripheral supports a hardware bus idle detection 28 4 11 SMBus initialization This section is relevant only when SMBus feature is supported Please refer to Section 28 3 I2C implementation In addition to I2C initialization some other specific initialization must be done in order to perform SMBus communication Received Command and Data Ackn...

Page 803: ...n the I2C is enabled Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2C_TIMEOUTR register The timers must be programmed in such a way that they detect a timeout before the maximum time given in the SMBus specification version 2 0 tTIMEOUT check In order to enable the tTIMEOUT check the 12 bit TIMEOUTA 11 0 bits must be programmed with the timer re...

Page 804: ...he TIMOUTEN bit in the I2C_TIMEOUTR register If both the SCL and SDA lines remain high for a time greater than TIMEOUTA 1 x 4 x tI2CCLK the TIMEOUT flag is set in the I2C_ISR register Refer to Table 148 Examples of TIMEOUTA settings for various I2CCLK frequencies max tIDLE 50 µs Caution Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set 28 4 12 SMBus I2C_TIMEOUT...

Page 805: ...the PEC transmission at the end of the programmed number of data bytes When the PECBYTE bit is set the number of bytes programmed in NBYTES 7 0 includes the PEC transmission In that case the total number of TXIS interrupts will be NBYTES 1 and the content of the I2C_PECR register is automatically transmitted if the master requests an extra byte after the NBYTES 1 data transfer Caution The PECBYTE ...

Page 806: ... SMBus slave transmitter SBC 1 D ϭϵϴϲϳsϮ 6ODYH LQLWLDOL DWLRQ 60 XV VODYH WUDQVPLVVLRQ ULWH B7 5 7 7 B 65 7 6 1R HV B 65 5 HV 1R 5HDG 2 DQG 5 LQ B 65 B 5 1 7 6 1 3 7 6HW B 5 5 6 VWUHWFKHG 06 9 DPSOH 60 XV VODYH WUDQVPLWWHU E WHV 3 9 5 65 FKHFN 2 SURJUDP 1 7 6 VHW 3 7 VHW 5 9 7 6 65 ZU GDWD 9 7 6 65 ZU GDWD 5 OHJHQG WUDQVPLVVLRQ UHFHSWLRQ 6 VWUHWFK 9 9 7 6 7 6 9 1 7 6 6 GGUHVV GDWD GDWD 3 1 3 ...

Page 807: ...red with the internal I2C_PECR register content A NACK is automatically generated if the comparison does not match and an ACK is automatically generated if the comparison matches whatever the ACK bit value Once the PEC byte is received it is copied into the I2C_RXDR register like any other data and the RXNE flag is set In the case of a PEC mismatch the PECERR flag is set and an interrupt is genera...

Page 808: ...hart for SMBus slave receiver N Bytes PEC D ϭϵϴϲϴsϮ 6ODYH LQLWLDOL DWLRQ 60 XV VODYH UHFHSWLRQ 5HDG B5 5 5 7 B 65 5 1 B 65 7 5 1R HV B 65 5 HV 1R 5HDG 2 DQG 5 LQ B 65 B 5 1 7 6 5 2 3 7 6HW B 5 5 6 VWUHWFKHG 5HDG B5 5 5 7 3URJUDP B 5 1 B 5 1 7 6 1 1 1 5HDG B5 5 5 7 3URJUDP 5 2 1 DQG 1 7 6 B 65 5 1 1R QG 1R HV HV ...

Page 809: ...will be NBYTES 1 So if the PECBYTE bit is set when NBYTES 0x1 the content of the I2C_PECR register is automatically transmitted If the SMBus master wants to send a STOP condition after the PEC automatic end mode should be selected AUTOEND 1 In this case the STOP condition automatically follows the PEC transmission 06 9 DPSOH 60 XV VODYH UHFHLYHU E WHV 3 GGUHVV 6 9 5 65 FKHFN 2 DQG 5 SURJUDP 1 7 6 ...

Page 810: ...fect when the RELOAD bit is set Figure 312 Bus transfer diagrams for SMBus master transmitter 06 9 DPSOH 60 XV PDVWHU WUDQVPLWWHU E WHV 3 DXWRPDWLF HQG PRGH 6723 GGUHVV 6 1 7 SURJUDP 6ODYH DGGUHVV SURJUDP 1 7 6 872 1 VHW 3 7 VHW 67 57 9 7 6 65 ZU GDWD 9 7 6 65 ZU GDWD GDWD 7 6 7 6 GDWD 1 7 6 OHJHQG WUDQVPLVVLRQ UHFHSWLRQ 6 VWUHWFK 9 1 7 DPSOH 60 XV PDVWHU WUDQVPLWWHU E WHV 3 VRIWZDUH HQG PRGH 5 67...

Page 811: ...CK response is given to the PEC byte followed by a STOP condition When the SMBus master receiver wants to receive the PEC byte followed by a RESTART condition at the end of the transfer software mode must be selected AUTOEND 0 The PECBYTE bit must be set and the slave address must be programmed before setting the START bit In this case after NBYTES 1 data have been received the next received byte ...

Page 812: ... 9 5 1 65 UG GDWD 9 5 1 65 UG GDWD 9 5 1 65 UG 3 GDWD 5 1 5 1 GDWD 1 7 6 1 OHJHQG WUDQVPLVVLRQ UHFHSWLRQ 6 VWUHWFK 9 9 1 7 DPSOH 60 XV PDVWHU UHFHLYHU E WHV 3 VRIWZDUH HQG PRGH 5 67 57 GGUHVV 6 1 7 SURJUDP 6ODYH DGGUHVV SURJUDP 1 7 6 872 1 VHW 3 7 VHW 67 57 9 5 1 65 UG GDWD 9 5 1 65 UG GDWD 9 5 1 65 UHDG 3 9 7 65 SURJUDP 6ODYH DGGUHVV SURJUDP 1 7 6 1 VHW 67 57 GDWD 5 1 5 1 GDWD 1 7 6 5HVWDUW OHJHQ...

Page 813: ...sfer as a master or as an addressed slave after the ADDR flag is set This can be managed by clearing SLEEPDEEP bit in the ADDR interrupt routine and setting it again only after the STOPF flag is set Caution The digital filter is not compatible with the wakeup from Stop mode feature If the DNF bit is not equal to 0 setting the WUPEN bit has no effect Caution This feature is available only when the ...

Page 814: ... 0xFF if not When a new byte should be sent and the I2C_TXDR register has not been written yet 0xFF is sent When an overrun or underrun error is detected the OVR flag is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register Packet Error Checking Error PECERR This section is relevant only when the SMBus feature is supported Please refer to Section...

Page 815: ...initialization the slave address direction number of bytes and START bit are programmed by software the transmitted slave address cannot be transferred with DMA When all data are transferred using DMA the DMA must be initialized before setting the START bit The end of transfer is managed with the NBYTES counter Refer to Master transmitter on page 790 In slave mode With NOSTRETCH 0 when all data ar...

Page 816: ...o work normally or stops depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module 28 5 I2C low power modes 28 6 I2C interrupts The table below gives the list of I2C interrupt requests Table 149 low power modes Mode Description Sleep No effect I2C interrupts cause the device to exit the Sleep mode Stop The contents of I2C registers are kept Standby The I2C peripheral is powered ...

Page 817: ...figure the I2C to generate interrupts The I2C wakeup event is connected to the EXTI controller refer to Section 13 2 Extended interrupts and events controller EXTI Figure 314 I2C interrupt mapping diagram Bus error BERR Write BERRCF 1 ERRIE Arbitration loss ARLO Write ARLOCF 1 Overrun Underrun OVR Write OVRCF 1 PEC error PECERR Write PECERRCF 1 Timeout tLOW error TIMEOUT Write TIMEOUTCF 1 SMBus Al...

Page 818: ...w rw Bits 31 24 Reserved must be kept at reset value Bit 23 PECEN PEC enable 0 PEC calculation disabled 1 PEC calculation enabled Note If the SMBus feature is not supported this bit is reserved and forced by hardware to 0 Please refer to Section 28 3 I2C implementation Bit 22 ALERTEN SMBus alert enable Device mode SMBHEN 0 0 Releases SMBA pin high and Alert Response Address Header disabled 0001100...

Page 819: ...abled Note This bit can only be programmed when the I2C is disabled PE 0 Bit 16 SBC Slave byte control This bit is used to enable hardware byte control in slave mode 0 Slave byte control disabled 1 Slave byte control enabled Bit 15 RXDMAEN DMA reception requests enable 0 DMA mode disabled for reception 1 DMA mode enabled for reception Bit 14 TXDMAEN DMA transmission requests enable 0 DMA mode disa...

Page 820: ...upt enable 0 Stop detection STOPF interrupt disabled 1 Stop detection STOPF interrupt enabled Bit 4 NACKIE Not acknowledge received Interrupt enable 0 Not acknowledge NACKF received interrupts disabled 1 Not acknowledge NACKF received interrupts enabled Bit 3 ADDRIE Address match Interrupt enable slave only 0 Address match ADDR interrupts disabled 1 Address match ADDR interrupts enabled Bit 2 RXIE...

Page 821: ...equested Note Writing 0 to this bit has no effect This bit has no effect when RELOAD is set This bit has no effect is slave mode when SBC 0 If the SMBus feature is not supported this bit is reserved and forced by hardware to 0 Please refer to Section 28 3 I2C implementation Bit 25 AUTOEND Automatic end mode master mode This bit is set and cleared by software 0 software end mode TC flag is set when...

Page 822: ...ing 1 to the ADDRCF bit in the I2C_ICR register 0 No Start generation 1 Restart Start generation If the I2C is already in master mode with AUTOEND 0 setting this bit generates a Repeated Start condition when RELOAD 0 after the end of the NBYTES transfer Otherwise setting this bit will generate a START condition once the bus is free Note Writing 0 to this bit has no effect The START bit can be set ...

Page 823: ...lave address bit 7 1 master mode In 7 bit addressing mode ADD10 0 These bits should be written with the 7 bit slave address to be sent In 10 bit addressing mode ADD10 1 These bits should be written with bits 7 1 of the slave address to be sent Note Changing these bits when the START bit is set is not allowed Bit 0 SADD0 Slave address bit 0 master mode In 7 bit addressing mode ADD10 0 This bit is d...

Page 824: ...rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bit 15 OA1EN Own Address 1 enable 0 Own address 1 disabled The received slave address OA1 is NACKed 1 Own address 1 enabled The received slave address OA1 is ACKed Bits 14 11 Reserved must be kept at reset value Bit 10 OA1MODE Own Address 1 10 bit mode 0 Own address 1 is a 7 bit address 1 Own address 1 is a 10 bit address Note This bit ca...

Page 825: ...dress 2 enabled The received slave address OA2 is ACKed Bits 14 11 Reserved must be kept at reset value Bits 10 8 OA2MSK 2 0 Own Address 2 masks 000 No mask 001 OA2 1 is masked and don t care Only OA2 7 2 are compared 010 OA2 2 1 are masked and don t care Only OA2 7 3 are compared 011 OA2 3 1 are masked and don t care Only OA2 7 4 are compared 100 OA2 4 1 are masked and don t care Only OA2 7 5 are...

Page 826: ...CLK Bits 27 24 Reserved must be kept at reset value Bits 23 20 SCLDEL 3 0 Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge In master mode and in slave mode with NOSTRETCH 0 the SCL line is stretched low during tSCLDEL tSCLDEL SCLDEL 1 x tPRESC Note tSCLDEL is used to generate tSU DAT timing Bits 19 16 SDADEL 3 0 Data hold time This field is used t...

Page 827: ...IMEOUT 1 Bits 30 28 Reserved must be kept at reset value Bits 27 16 TIMEOUTB 11 0 Bus timeout B This field is used to configure the cumulative clock extension timeout In master mode the master cumulative clock low extend time tLOW MEXT is detected In slave mode the slave cumulative clock low extend time tLOW SEXT is detected tLOW EXT TIMEOUTB 1 x 2048 x tI2CCLK Note These bits can be written only ...

Page 828: ...ceiver mode 1 Read transfer slave enters transmitter mode Bit 15 BUSY Bus busy This flag indicates that a communication is in progress on the bus It is set by hardware when a START condition is detected It is cleared by hardware when a Stop condition is detected or when PE 0 Bit 14 Reserved must be kept at reset value Bit 13 ALERT SMBus alert This flag is set by hardware when SMBHEN 1 SMBus host c...

Page 829: ...CR Transfer Complete Reload This flag is set by hardware when RELOAD 1 and NBYTES data have been transferred It is cleared by software when NBYTES is written to a non zero value Note This bit is cleared by hardware when PE 0 This flag is only for master mode or for slave mode when the SBC bit is set Bit 6 TC Transfer Complete master mode This flag is set by hardware when RELOAD 0 AUTOEND 0 and NBY...

Page 830: ...bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR Note This bit is set by hardware when PE 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res ALERT CF TIM OUTCF PECCF OVRCF ARLO CF BERR CF Res Res STOP CF NACK CF ADDR CF Res Res Res w w w w w w w w w ...

Page 831: ...p detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register Bit 4 NACKCF Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register Bit 3 ADDRCF Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register Writing 1 to this bit also clears the START bit in the I2C_CR2 register Bits 2 0 Reserved must be k...

Page 832: ...es Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res RXDATA 7 0 r Bits 31 8 Reserved must be kept at reset value Bits 7 0 RXDATA 7 0 8 bit receive data Data byte received from the I2 C bus 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res T...

Page 833: ... Res Res Res Res Res Res Res Res Res OA2EN Res Res Res Res OA2MS K 2 0 OA2 7 1 Res Reset value 0 0 0 0 0 0 0 0 0 0 0 0x10 I2C_TIMINGR PRESC 3 0 Res Res Res Res SCLDEL 3 0 SDADEL 3 0 SCLH 7 0 SCLL 7 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 I2C_ TIMEOUTR TEXTEN Res Res Res TIMEOUTB 11 0 TIMOUTEN Res TIDLE TIMEOUTA 11 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 834: ...er boundary addresses 0x28 I2C_TXDR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res TXDATA 7 0 Reset value 0 0 0 0 0 0 0 0 Table 151 I2C register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 835: ...guration 29 2 USART main features Full duplex asynchronous communications NRZ standard format mark space Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance A common programmable transmit and receive baud rate of up to 9 Mbit s when the clock frequency is 72 MHz and oversampling is by 8 Dual clock domain allowing USART functionality and wakeup from Sto...

Page 836: ...dle line detection or address mark detection 29 3 USART extended features LIN master synchronous break send capability and LIN slave break detection capability 13 bit break generation and 10 11 bit break detection when USART is hardware configured for LIN IrDA SIR encoder decoder supporting 3 16 bit duration for normal mode Smartcard mode Supports the T 0 and T 1 asynchronous protocols for smartca...

Page 837: ... LIN mode X X X X X X X Dual clock domain and wakeup from Stop mode X X X X X X X Receiver timeout interrupt X X X X X X X Modbus communication X X X X X X X Auto baud rate detection X 4 modes X 4 modes X 4 modes Driver Enable X X X X USART data length 8 and 9 bits 7 8 and 9 bits 7 8 and 9 bits 1 X supported 2 CK output is disabled when UE bit 0 3 With the following limitation for STM32F302xB C If...

Page 838: ...or A status register USART_ISR Receive and transmit data registers USART_RDR USART_TDR A baud rate register USART_BRR A guard time register USART_GTPR in case of Smartcard mode Refer to Section 29 8 USART registers on page 879 for the definitions of each bit The following pin is required to interface in synchronous mode and Smartcard mode CK Clock output This pin outputs the transmitter data clock...

Page 839: ... 7UDQVPLW GDWD UHJLVWHU 7 5 3 7 35 7 5HFHLYH GDWD UHJLVWHU 5 5 7UDQVPLW VKLW UHJLVWHU 86 57B 5 UHJLVWHU 86 57B 5 UHJLVWHU 576 76 DUGZDUH IORZ FRQWUROOHU U 6 5 1 EORFN 7UDQVPLW FRQWURO 86 57B 5 UHJLVWHU DNHXS XQLW 86 57B 5 UHJLVWHU 86 57B 735 UHJLVWHU 7 36 FRQWURO 86 57B 5 UHJLVWHU 5HFHLYHU FRQWURO 5HFHLYHU FORFN 86 57B 65 UHJLVWHU 86 57 LQWHUUXSW FRQWURO 86 57B 55 UHJLVWHU 7UDQVPLWWHU UDWH FRQWURO...

Page 840: ...bit mode is supported only on some USARTs By default the signal TX or RX is in low state during the start bit It is in high state during the stop bit These values can be inverted separately for each signal through polarity configuration control An Idle character is interpreted as an entire frame of 1 s the number of 1 s includes the number of stop bits A Break character is interpreted on receiving...

Page 841: ...W UHDN IUDPH DWD IUDPH ORFN 6WDUW ELW 6WRS ELW 6WDUW ELW 6WRS ELW LW LW LW LW LW LW LW LW 6WDUW ELW 6WRS ELW 1H W 6WDUW ELW GOH IUDPH ELW ZRUG OHQJWK 0 6WRS ELW 3RVVLEOH 3DULW ELW UHDN IUDPH DWD IUDPH ORFN 6WDUW ELW 6WRS ELW 6WDUW ELW 6WRS ELW LW LW LW LW LW LW LW 6WDUW ELW 6WRS ELW 1H W 6WDUW ELW GOH IUDPH ELW ZRUG OHQJWK 0 6WRS ELW 3RVVLEOH 3DULW ELW UHDN IUDPH DWD IUDPH ORFN ELW FRQWUROV ODVW G...

Page 842: ...d by USART 0 5 1 1 5 and 2 stop bits Note The TE bit must be set before writing the data to be transmitted to the USART_TDR The TE bit should not be reset during transmission of data Resetting the TE bit during the transmission will corrupt the data on the TX pin as the baud rate counters will get frozen The current data being transmitted will be lost An idle frame will be sent after the TE bit is...

Page 843: ...RT is disabled or enters the Halt mode to avoid corrupting the last transmission Single byte communication Clearing the TXE bit is always performed by a write to the transmit data register The TXE bit is set by hardware and it indicates The data has been moved from the USART_TDR register to the shift register and the data transmission has started The USART_TDR register is empty The next data can b...

Page 844: ...it is set by the write operation and it is reset by hardware when the break character is completed during the stop bits after the break character The USART inserts a logic 1 signal STOP for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start bit of the next frame In the case the application needs to send the break character following all previously insert...

Page 845: ... on the 3rd 5th and 7th bits finds the 3 bits at 0 and second sampling on the 8th 9th and 10th bits also finds the 3 bits at 0 The start bit is validated RXNE flag set interrupt generated if RXNEIE 1 but the NF noise flag is set if a for both samplings 2 out of the 3 sampled bits are at 0 sampling on the 3rd 5th and 7th bits and sampling on the 8th 9th and 10th bits or b for one of the samplings s...

Page 846: ... bit When a character is received The RXNE bit is set to indicate that the content of the shift register is transferred to the RDR In other words data has been received and can be read as well as its associated error flags An interrupt is generated if the RXNEIE bit is set The error flags can be set if a frame error noise or an overrun error has been detected during reception PE flag can also be s...

Page 847: ...RDR at the same time as the new and lost data is received Selecting the clock source and the proper oversampling method The choice of the clock source is done through the Clock Control system see Section Reset and clock control RCC The clock source must be chosen before enabling the USART by setting the UE bit The choice of the clock source must be done according to two criteria Possible use of th...

Page 848: ...equal the NF bit is set A single sample in the center of the received bit Depending on the application select the three samples majority vote method ONEBIT 0 when operating in a noisy environment and reject the data when a noise is detected refer to Figure 153 because this indicates that a glitch occurred during the sampling select the single sample method ONEBIT 1 when the line is noise free to i...

Page 849: ... oversampling by 16 Figure 321 Data sampling when oversampling by 8 Table 153 Noise detection from sampled data Sampled value NE status Received bit value 000 0 0 001 1 0 010 1 0 011 1 1 100 1 0 101 1 1 110 1 1 111 0 1 06Y 9 VDPSOHG YDOXHV 2QH ELW WLPH 6DPSOH FORFN 5 OLQH 06Y 9 VDPSOHG YDOXHV 2QH ELW WLPH 6DPSOH FORFN 5 OLQH ...

Page 850: ... frame can be detected when 0 5 stop bit is selected 1 stop bit Sampling for 1 stop Bit is done on the 8th 9th and 10th samples 1 5 stop bits Smartcard mode When transmitting in Smartcard mode the device must check that the data is correctly sent Thus the receiver block must be enabled RE 1 in the USART_CR1 register and the stop bit is checked to test if the smartcard has detected a parity error I...

Page 851: ...s coded on the USART_BRR register When OVER8 0 BRR USARTDIV When OVER8 1 BRR 2 0 USARTDIV 3 0 shifted 1 bit to the right BRR 3 must be kept cleared BRR 15 4 USARTDIV 15 4 Note The baud counters are updated to the new value in the baud registers after a write operation to USART_BRR Hence the baud rate register value should not be changed during communication In case of oversampling by 16 or 8 USART...

Page 852: ... 0 2 4 KBps 0xEA60 0 2 9 6 KBps 9 6 KBps 0x1D4C 0 9 6 KBps 0x3A94 0 3 19 2 KBps 19 2 KBps 0xEA6 0 19 2 KBps 0x1D46 0 4 38 4 KBps 38 4 KBps 0x753 0 38 4 KBps 0xEA3 0 5 57 6 KBps 57 6 KBps 0x4E2 0 57 6 KBps 0x9C2 0 6 115 2 KBps 115 2 KBps 0x271 0 115 2 KBps 0x4E1 0 7 230 4 KBps 230 03KBps 0x139 0 16 230 4 KBps 0x270 0 8 460 8 KBps 461 54KBps 0x9C 0 16 460 06KBps 0x134 0 16 9 921 6 KBps 923 08KBps 0x...

Page 853: ...on when the wakeup from Stop mode is used when M 1 0 01 when M 1 0 00 when M 1 0 10 tWUUSART is the time between detection of the wakeup event and the instant when clock requested by the peripheral and regulator are ready The USART receiver can receive data correctly at up to the maximum tolerated deviation specified in Table 155 and Table 155 depending on the following choices 9 10 or 11 bit char...

Page 854: ...field in the USART_CR2 register In these auto baud rate modes the baud rate is measured several times during the synchronization data reception and each measurement is compared to the previous one These modes are Mode 0 Any character starting with a bit at 1 In this case the USART measures the duration of the Start bit falling edge to rising edge Mode 1 Any character starting with a 10xx bit patte...

Page 855: ... end of the operation At any later time the auto baud rate detection may be relaunched by resetting the ABRF flag by writing a 0 Note If the USART is disabled UE 0 during an auto baud rate operation the BRR value may be corrupted 29 5 7 Multiprocessor communication using USART In multiprocessor communication the following bits are to be kept cleared LINEN bit in the USART_CR2 register HDSEL IREN a...

Page 856: ...ne IDLE frame not only after the reception of one character frame 4 bit 7 bit address mark detection WAKE 1 In this mode bytes are recognized as addresses if their MSB is a 1 otherwise they are considered as data In an address byte the address of the targeted receiver is put in the 4 or 7 LSBs The choice of 7 or 4 bit address detection is done using the ADDM7 bit This 4 bit 7 bit word is compared ...

Page 857: ...dle line for more than 2 character times This function is implemented through the programmable timeout function The timeout function and interrupt must be activated through the RTOEN bit in the USART_CR2 register and the RTOIE in the USART_CR1 register The value corresponding to a timeout of 2 character times for example 22 x bit duration must be programmed in the RTO register when the receive lin...

Page 858: ...d the parity bit As an example if data 00110101 and 4 bits set then the parity bit will be 1 if odd parity is selected PS bit in USART_CR1 1 Parity checking in reception If the parity check fails the PE flag is set in the USART_ISR register and an interrupt is generated if PEIE is set in the USART_CR1 register The PE flag is cleared by software writing 1 to the PECF in the USART_ICR register Parit...

Page 859: ...tart signal The method for detecting start bits is the same when searching break characters or data After a start bit has been detected the circuit samples the next bits exactly like for the data on the 8th 9th and 10th samples If 10 when the LBDL 0 in USART_CR2 or 11 when LBDL 1 in USART_CR2 consecutive bits are detected as 0 and are followed by a delimiter character the LBDF flag is set in USART...

Page 860: ... HQRXJK EUHDN GLVFDUGHG LV QRW VHW 5 OLQH DSWXUH VWUREH UHDN VWDWH PDFKLQH 5HDG VDPSOHV GOH LW LW LW LW LW LW LW LW LW LW GOH DVH EUHDN VLJQDO MXVW ORQJ HQRXJK EUHDN GHWHFWHG LV VHW 5 OLQH DSWXUH VWUREH UHDN VWDWH PDFKLQH 5HDG VDPSOHV UHDN IUDPH UHDN IUDPH HOLPLWHU LV LPPHGLDWH GOH LW LW LW LW LW LW LW LW LW LW LW GOH DVH EUHDN VLJQDO ORQJ HQRXJK EUHDN GHWHFWHG LV VHW 5 OLQH DSWXUH VWUREH UHDN VWD...

Page 861: ...d data bit address mark The CPOL bit in the USART_CR2 register is used to select the clock polarity and the CPHA bit in the USART_CR2 register is used to select the phase of the external clock see Figure 326 Figure 327 and Figure 328 During the Idle state preamble and send break the external CK clock is not activated In synchronous mode the USART transmitter works exactly like in asynchronous mode...

Page 862: ...thout transmitting data The LBCL CPOL and CPHA bits have to be selected when the USART is disabled UE 0 to ensure that the clock pulses function correctly Figure 326 USART example of synchronous transmission Figure 327 USART data clock timing diagram M bits 00 06Y 9 86 57 6 QFKURQRXV GHYLFH H J VODYH 63 5 7 DWD RXW DWD LQ ORFN 06Y 9 06 06 6 6 6WDUW 6WDUW 6WRS GOH RU SUHFHGLQJ WUDQVPLVVLRQ GOH RU Q...

Page 863: ...Smartcard mode Refer to Section 29 5 13 USART Smartcard mode for more details 06Y 9 06 06 6 6 6WDUW 6WDUW 6WRS GOH RU SUHFHGLQJ WUDQVPLVVLRQ GOH RU QH W WUDQVPLVVLRQ ELW FRQWUROV ODVW GDWD SXOVH DSWXUH VWUREH DWD RQ 5 IURP VODYH DWD RQ 7 IURP PDVWHU ORFN 32 3 ORFN 32 3 ORFN 32 3 ORFN 32 3 6WRS 0 ELWV GDWD ELWV 06Y 9 DWD RQ 5 IURP VODYH FDSWXUH VWUREH RQ ULVLQJ HGJH LQ WKLV H DPSOH 9DOLG 7 ELW W6 7...

Page 864: ...ed by software by the use of a centralized arbiter for instance In particular the transmission is never blocked by hardware and continues as soon as data is written in the data register while the TE bit is set 29 5 13 USART Smartcard mode This section is relevant only when Smartcard mode is supported Please refer to Section 29 4 USART implementation on page 837 Smartcard mode is selected by settin...

Page 865: ...he USART_RQR register Smartcard auto retry in transmission a delay of 2 5 baud periods is inserted between the NACK detection by the USART and the start bit of the repeated character The TC bit is set immediately at the end of reception of the last repeated character no guard time If the software wants to repeat it again it must insure the minimum 2 baud periods required by the standard If a parit...

Page 866: ...nsmitter According to the ISO protocol the duration of the received NACK can be 1 or 2 baud clock periods On the receiver side if a parity error is detected and a NACK is transmitted the receiver does not detect the NACK as a start bit Note A break character is not significant in Smartcard mode A 0x00 data with a framing error is treated as data and not as a break No Idle frame is transmitted when...

Page 867: ...nd stop bit in case of STOP 10 1 bit duration after the beginning of the STOP bit in case STOP 11 From the beginning of the STOP bit in case STOP 01 As in the Smartcard protocol definition the BWT CWT values are defined from the beginning start bit of the last character The RTO register must be programmed to BWT 11 or CWT 11 respectively taking into account the length of the last character itself ...

Page 868: ... LHHL HHH LLH sets up the direct convention state H encodes value 1 and moment 2 conveys the least significant bit LSB first when decoded by direct convention the conveyed byte is equal to 3B Character parity is correct when there is an even number of bits set to 1 in the nine moments 2 to 10 As the USART does not know which convention is used by the card it needs to be able to recognize either pa...

Page 869: ...am is transmitted to an external output driver and infrared LED USART supports only bit rates up to 115 2 Kbps for the SIR ENDEC In normal mode the transmitted pulse width is specified as 3 16 of a bit period The SIR receive decoder demodulates the return to zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the USART The decoder input is normally high mar...

Page 870: ...he pulse width is not maintained at 3 16 of the bit period Instead the width of the pulse is 3 times the low power baud rate which can be a minimum of 1 42 MHz Generally this value is 1 8432 MHz 1 42 MHz PSC 2 12 MHz A low power mode programmable divisor divides the system clock to achieve this value Receiver Receiving in low power mode is similar to receiving in normal mode For glitch detection t...

Page 871: ...T transmission use the following procedure x denotes the channel number 1 Write the USART_TDR register address in the DMA control register to configure it as the destination of the transfer The data is moved to this address from memory after each TXE event 2 Write the memory address in the DMA control register to configure it as the source of the transfer The data is loaded into the USART_TDR regi...

Page 872: ...the memory after each RXNE event 2 Write the memory address in the DMA control register to configure it as the destination of the transfer The data is loaded from USART_RDR to this memory area after each RXNE event 3 Configure the total number of bytes to be transferred to the DMA control register 4 Configure the channel priority in the DMA control register 5 Configure interrupt generation after h...

Page 873: ...ables an interrupt after the current byte if any of these errors occur 29 5 16 RS232 hardware flow control and RS485 driver enable using USART It is possible to control the serial data flow between 2 devices by using the CTS input and the RTS output The Figure 336 shows how to connect 2 devices in this mode Figure 336 Hardware flow control between 2 USARTs 7 OLQH UDPH 6HW E KDUGZDUH FOHDUHG E 0 UH...

Page 874: ...32 CTS flow control If the CTS flow control is enabled CTSE 1 then the transmitter checks the CTS input before transmitting the next frame If CTS is asserted tied low then the next data is transmitted assuming that data is to be transmitted in other words if TXE 0 else the transmission does not occur when CTS is de asserted during a transmission the current transmission is completed before the tra...

Page 875: ...it in the USART_CR3 control register In USART the DEAT and DEDT are expressed in sample time units 1 8 or 1 16 bit duration depending on the oversampling rate 29 5 17 Wakeup from Stop mode using USART The USART is able to wake up the MCU from Stopmode when the UESM bit is set and the USART clock is set to HSI or LSE refer to Section Reset and clock control RCC USART source clock is HSI If during s...

Page 876: ...exit from Stop mode The wakeup from Stop mode feature is not available for all modes For example it doesn t work in SPI mode because the SPI operates in master mode only Using Mute mode with Stop mode If the USART is put into Mute mode before entering Stop mode Wakeup from Mute mode on idle detection must not be used because idle detection cannot work in Stop mode If the wakeup from Mute mode on a...

Page 877: ... the device to exit Sleep mode Stop The USART is able to wake up the MCU from Stop mode when the UESM bit is set and the USART clock is set to HSI or LSE The MCU wakeup from Stop mode can be done using either a standard RXNE or a WUF interrupt Standby The USART is powered down and must be reinitialized when the device has exited from Standby mode Table 159 USART interrupt requests Interrupt event ...

Page 878: ... empty or Framing error in Smartcard mode interrupt During reception Idle Line detection Overrun error Receive data register not empty Parity error LIN break detection Noise Flag Framing Error Character match etc These events generate an interrupt if the corresponding Enable Control Bit is set Figure 339 USART interrupt mapping diagram 1 The WUF interrupt is active only in Stop mode 06Y 9 7 7 7 7 ...

Page 879: ...detection are not supported Bit 27 EOBIE End of Block interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 A USART interrupt is generated when the EOBF flag is set in the USART_ISR register Note If the USART does not support Smartcard mode this bit is reserved and forced by hardware to 0 Please refer to Section 29 4 USART implementation on page 837 Bit 26 RTOIE Recei...

Page 880: ...t the USART can switch between the active and mute modes as defined by the WAKE bit It is set and cleared by software 0 Receiver in active mode permanently 1 Receiver can switch between mute mode and active mode Bit 12 M0 Word length This bit with bit 28 M1 determines the word length It is set or cleared by software See Bit 28 M1 description This bit can only be written when the USART is disabled ...

Page 881: ... and cleared by software 0 Interrupt is inhibited 1 A USART interrupt is generated whenever ORE 1 or RXNE 1 in the USART_ISR register Bit 4 IDLEIE IDLE interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 A USART interrupt is generated whenever IDLE 1 in the USART_ISR register Bit 3 TE Transmitter enable This bit enables the transmitter It is set and cleared by softw...

Page 882: ...mode If the USART does not support the wakeup from Stop feature this bit is reserved and forced by hardware to 0 Please refer to Section 29 4 USART implementation on page 837 Bit 0 UE USART enable When this bit is cleared the USART prescalers and outputs are stopped immediately and current operations are discarded The configuration of the USART is kept but all the status flags in the USART_ISR are...

Page 883: ...le no reception for the duration programmed in the RTOR receiver timeout register Note If the USART does not support the Receiver timeout feature this bit is reserved and forced by hardware to 0 Please refer to Section 29 4 USART implementation on page 837 Bits 22 21 ABRMOD 1 0 Auto baud rate mode These bits are set and cleared by software 00 Measurement of the start bit is used to detect the baud...

Page 884: ... 0 Bit 15 SWAP Swap TX RX pins This bit is set and cleared by software 0 TX RX pins are used as defined in standard pinout 1 The TX and RX pins functions are swapped This allows to work in the case of a cross wired connection to another USART This bit field can only be written when the USART is disabled UE 0 Bit 14 LINEN LIN mode enable This bit is set and cleared by software 0 LIN mode disabled 1...

Page 885: ... The first clock transition is the first data capture edge 1 The second clock transition is the first data capture edge This bit can only be written when the USART is disabled UE 0 Note If synchronous mode is not supported this bit is reserved and forced by hardware to 0 Please refer to Section 29 4 USART implementation on page 837 Bit 8 LBCL Last bit clock pulse This bit is used to select whether...

Page 886: ...n only be written when the USART is disabled UE 0 Note In 7 bit and 9 bit data modes the address detection is done on 6 bit and 8 bit address ADD 5 0 and ADD 7 0 respectively Bits 3 0 Reserved must be kept at reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res WUFIE WUS SCARCNT2 0 Res rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEP DEM DDRE O...

Page 887: ...efer to Section 29 4 USART implementation on page 837 Bit16 Reserved must be kept at reset value Bit 15 DEP Driver enable polarity selection 0 DE signal is active high 1 DE signal is active low This bit can only be written when the USART is disabled UE 0 Note If the Driver Enable feature is not supported this bit is reserved and must be kept cleared Please refer to Section 29 4 USART implementatio...

Page 888: ...SART implementation on page 837 Bit 9 CTSE CTS enable 0 CTS hardware flow control disabled 1 CTS mode enabled data is only transmitted when the CTS input is asserted tied to 0 If the CTS input is de asserted while data is being transmitted then the transmission is completed before stopping If data is written into the data register while CTS is de asserted the transmission is postponed until CTS is...

Page 889: ...plex mode 0 Half duplex mode is not selected 1 Half duplex mode is selected This bit can only be written when the USART is disabled UE 0 Bit 2 IRLP IrDA low power This bit is used for selecting between normal and low power IrDA modes 0 Normal mode 1 Low power mode This bit can only be written when the USART is disabled UE 0 Note If IrDA mode is not supported this bit is reserved and forced by hard...

Page 890: ...0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved must be kept at reset value Bits 15 4 BRR 15 4 BRR 15 4 USARTDIV 15 4 Bits 3 0 BRR 3 0 When OVER8 0 BRR 3 0 USARTDIV 3 0 When OVER8 1 BRR 2 0 USARTDIV 3 0 shifted 1 bit to...

Page 891: ...s divided by the value given in the register 8 significant bits 00000000 Reserved do not program this value 00000001 divides the source clock by 1 00000010 divides the source clock by 2 In Smartcard mode PSC 4 0 Prescaler value Used for programming the prescaler for dividing the USART source clock to provide the Smartcard clock The value given in the register 5 significant bits is multiplied by 2 ...

Page 892: ...ed also in other modes In this case the Block length counter is reset when RE 0 receiver disabled and or when the EOBCF bit is written to 1 Note This value can be programmed after the start of the block reception using the data from the LEN character in the Prologue Field It must be programmed only once per received block Bits 23 0 RTO 23 0 Receiver timeout value This bit field gives the Receiver ...

Page 893: ...sets the RWU flag Bit 1 SBKRQ Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line as soon as the transmit machine is available Note In the case the application needs to send the break character following all previously inserted data including the ones not yet transmitted the software should wait for the TXE flag assertion before setting the SBKRQ bit...

Page 894: ...d and forced by hardware to 0 Bit 19 RWU Receiver wakeup from Mute mode This bit indicates if the USART is in mute mode It is cleared set by hardware when a wakeup mute sequence is recognized The mute mode control sequence address or IDLE is selected by the WAKE bit in the USART_CR1 register When wakeup on IDLE mode is selected this bit can only be set by software writing 1 to the MMRQ bit in the ...

Page 895: ...rated if the EOBIE 1 in the USART_CR2 register It is cleared by software writing 1 to the EOBCF in the USART_ICR register 0 End of Block not reached 1 End of Block number of characters reached Note If Smartcard mode is not supported this bit is reserved and forced by hardware to 0 Please refer to Section 29 4 USART implementation on page 837 Bit 11 RTOF Receiver timeout This bit is set by hardware...

Page 896: ... to the USART_TDR register The TXE flag can also be cleared by writing 1 to the TXFRQ in the USART_RQR register in order to discard the data only in Smartcard T 0 mode in case of transmission failure An interrupt is generated if the TXEIE bit 1 in the USART_CR1 register 0 data is not transferred to the shift register 1 data is transferred to the shift register Note This bit is used during single b...

Page 897: ...et in the USART_CR3 register Bit 2 NF START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame It is cleared by software writing 1 to the NFCF bit in the USART_ICR register 0 No noise is detected 1 Noise is detected Note This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt An interrup...

Page 898: ...ot support Smartcard mode this bit is reserved and forced by hardware to 0 Please refer to Section 29 4 USART implementation on page 837 Bit 11 RTOCF Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register Note If the USART does not support the Receiver timeout feature this bit is reserved and forced by hardware to 0 Please refer to Section 29 4 USART imple...

Page 899: ...ing 1 to this bit clears the PE flag in the USART_ISR register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res RDR 8 0 r r r r r r r r r Bits 31 9 Reserved must be kept at reset value Bits 8 0 RDR 8 0 Receive data value Contains the received data character The RDR regis...

Page 900: ...0 OVER8 CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE UESM UE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 USART_CR2 ADD 7 4 ADD 3 0 RTOEN ABRMOD1 ABRMOD0 ABREN MSBFIRST DATAINV TXINV RXINV SWAP LINEN STOP 1 0 CLKEN CPOL CPHA LBCL Res LBDIE LBDL ADDM7 Res Res Res Res Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 USART_CR3 Res Res...

Page 901: ... Res Res Res Res Res Res WUCF Res Res CMCF Res Res Res Res EOBCF RTOCF Res CTSCF LBDCF Res TCCF Res IDLECF ORECF NCF FECF PECF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x24 USART_RDR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res RDR 8 0 Reset value X X X X X X X X X 0x28 USART_TDR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res R...

Page 902: ...rent audio standards including the Philips I2 S standard the MSB and LSB justified standards and the PCM standard 30 2 SPI main features Master or slave operation Full duplex synchronous transfers on three lines Half duplex synchronous transfer on two lines with bidirectional data line Simplex synchronous transfers on two lines with unidirectional data line 4 bit to 16 bit data size selection Mult...

Page 903: ... reception with one data register for both channel sides Supported I2S protocols I2S Philips standard MSB justified standard left justified LSB justified standard right justified PCM standard with short and long frame synchronization on 16 bit channel frame or 16 bit data frame extended to 32 bit channel frame Data direction is always MSB first DMA capability for transmission and reception 16 bit ...

Page 904: ...t The main elements of SPI and their interactions are shown in the following block diagram Figure 340 Figure 340 SPI block diagram Table 162 STM32F302xB C D E SPI implementation SPI Features 1 SPI1 SPI2 SPI3 SPI4 2 Hardware CRC calculation X X X X Rx Tx FIFO X X X X NSS pulse mode X X X X I2S mode X X TI mode X X X X 1 X supported 2 SPI4 is only in STM32F302xD E 6KLIW UHJLVWHU ULWH 5HDG GGUHVV DQG...

Page 905: ...I allows the MCU to communicate using different configurations depending on the device targeted and the application requirements These configurations use 2 or 3 wires with software NSS management or 3 or 4 wires with hardware NSS management Communication is always initiated by the master Full duplex communication By default the SPI is configured for full duplex communication In this configuration ...

Page 906: ...ary till next node changes its direction settings correspondingly too It is suggested to insert a serial resistance between MISO and MOSI pins at this mode to protect the outputs and limit the current blowing between them at this situation Simplex communications The SPI can communicate in simplex mode by setting the SPI in transmit only or in receive only using the RXONLY bit in the SPIx_CR2 regis...

Page 907: ... in standard transmit only mode e g OVF flag 3 In this configuration both the MISO pins can be used as GPIOs Note Any simplex communication can be alternatively replaced by a variant of the half duplex communication with a constant setting of the transaction direction bidirectional mode is enabled while BDIO bit is not changed 30 5 3 Standard multi slave communication In a configuration with two o...

Page 908: ... which detects a potential conflict between two nodes trying to master the bus at the same time For this detection NSS pin is used configured at hardware input mode The connection of more than two SPI nodes working at this mode is impossible as only one node can apply its output on a common data line at time When nodes are non active both stay at slave mode by default Once one node wants to overta...

Page 909: ...ent SSM 1 in this configuration slave select information is driven internally by the SSI bit value in register SPIx_CR1 The external NSS pin is free for other application uses Hardware NSS management SSM 0 in this case there are two possible configurations The configuration used depends on the NSS output configuration SSOE bit in register SPIx_CR1 NSS output enable SSM 0 SSOE 1 this configuration ...

Page 910: ... being transferred This bit affects both master and slave modes If CPOL is reset the SCK pin has a low level idle state If CPOL is set the SCK pin has a high level idle state If the CPHA bit is set the second edge on the SCK pin captures the first data bit transacted falling edge if the CPOL bit is reset rising edge if the CPOL bit is set Data are latched on each occurrence of this clock transitio...

Page 911: ... SPI shift register can be set up to shift out MSB first or LSB first depending on the value of the LSBFIRST bit The data frame size is chosen by using the DS bits It can be set from 4 bit up to 16 bit length and the setting applies for both transmission and reception Whatever the selected data frame size read access to the FIFO must be aligned with the FRXTH level When the SPIx_DR register is acc...

Page 912: ...MODE can t be set at the same time d Configure the LSBFIRST bit to define the frame format Note 2 e Configure the CRCL and CRCEN bits if CRC is needed while SCK clock signal is at idle state f Configure SSM and SSI Notes 2 3 g Configure the MSTR bit in multimaster NSS configuration avoid conflict state on NSS if master is configured to prevent MODF error 3 Write to SPI_CR2 register a Configure the...

Page 913: ...FO called TXFIFO and RXFIFO These FIFOs are used in all SPI modes except for receiver only mode slave or master with CRC calculation enabled see Section 30 5 14 CRC calculation The handling of FIFOs depends on the data exchange mode duplex simplex data frame format number of bits in the frame access size performed on the FIFO data registers 8 bit or 16 bit and whether or not data packing is used w...

Page 914: ...dle data flow and its content at anytime When necessary the master must slow down the communication and provide either a slower clock or separate frames or data sessions with sufficient delays Be aware there is no underflow error signal for master or slave in SPI mode and data from the slave is always transacted and processed by the master even if the slave could not prepare it correctly in time I...

Page 915: ...necessary to identify the end of ongoing transactions for example When NSS signal is managed by software and master has to provide proper end of NSS pulse for slave or When transactions streams from DMA or FIFO are completed while the last data frame or CRC frame transaction is still ongoing in the peripheral bus The correct disable procedure is except when receive only mode is used 1 Wait until F...

Page 916: ...hen the TXE or RXNE enable bit in the SPIx_CR2 register is set Separate requests must be issued to the Tx and Rx buffers In transmission a DMA request is issued each time TXE is set to 1 The DMA then writes to the SPIx_DR register In reception a DMA request is issued each time RXNE is set to 1 The DMA then reads the SPIx_DR register See Figure 350 through Figure 353 When the SPI is used only to tr...

Page 917: ...by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register if DMA Tx and or DMA Rx are used Packing with DMA If the transfers are managed by DMA TXDMAEN and RXDMAEN set in the SPIx_CR2 register packing mode is enabled disabled automatically depending on the PSIZE value configured for SPI TX and the SPI RX DMA channel If the DMA channel PSIZE value is equal to 16 bit and SPI data size is less...

Page 918: ...ll the data to be sent can fit into TxFIFO the DMA Tx TCIF flag can be raised even before communication on the SPI bus starts This flag always rises before the SPI transaction is completed 6 The CRC value for a package is calculated continuously frame by frame in the SPIx_TxCRCR and SPIx_RxCRCR registers The CRC information is processed after the entire data package has completed either automatica...

Page 919: ... 8 bit If DMA is used Number of Tx frames transacted by DMA is set to 3 Number of Rx frames transacted by DMA is set to 3 See also Communication diagrams on page 918 for details about common assumptions and notes 7 5 166 6 6 026 06 06 06 7 7 63 7 7 9 7 7 6 5 6 5 6 5 1 5 5 5 5 9 0 7 7 0 5 7 QDEOH 7 5 0 RU LQWHUUXSWV 0 RU VRIWZDUH FRQWURO DW 7 HYHQWV 0 RU VRIWZDUH FRQWURO DW 5 HYHQWV 7 0 62 06Y 9 ...

Page 920: ...e 8 bit If DMA is used Number of Tx frames transacted by DMA is set to 3 Number of Rx frames transacted by DMA is set to 3 See also Communication diagrams on page 918 for details about common assumptions and notes 7 5 166 6 6 0 62 06 06 06 7 7 63 7 7 9 7 7 6 5 6 5 6 5 1 5 5 5 5 9 0 7 7 0 5 7 QDEOH 7 5 0 RU LQWHUUXSWV 0 RU VRIWZDUH FRQWURO DW 7 HYHQWV 0 RU VRIWZDUH FRQWURO DW 5 HYHQWV 7 026 06Y 9 ...

Page 921: ...ize 16 bit CRC enabled If DMA is used Number of Tx frames transacted by DMA is set to 2 Number of Rx frames transacted by DMA is set to 3 See also Communication diagrams on page 918 for details about common assumptions and notes 7 5 166 6 6 026 06 06 06 7 5 63 7 7 9 7 7 6 5 6 5 6 5 1 5 5 5 5 9 0 7 7 0 5 7 QDEOH 7 5 0 RU LQWHUUXSWV 0 RU VRIWZDUH FRQWURO DW 7 HYHQWV 0 RU VRIWZDUH FRQWURO DW 5 HYHQWV...

Page 922: ...access FRXTH 0 If DMA is used Number of Tx frames to be transacted by DMA is set to 3 Number of Rx frames to be transacted by DMA is set to 3 PSIZE for both Tx and Rx DMA channel is set to 16 bit LDMA_TX 1 and LDMA_RX 1 See also Communication diagrams on page 918 for details about common assumptions and notes 166 6 6 026 63 7 7 9 7 7 5 1 5 5 5 5 9 0 7 7 0 5 7 QDEOH 7 5 0 RU LQWHUUXSWV 0 RU VRIWZDU...

Page 923: ...usy flag BSY The BSY flag is set and cleared by hardware writing to this flag has no effect When BSY is set it indicates that a data transfer is in progress on the SPI the SPI bus is busy The BSY flag can be used in certain modes to detect the end of a transfer so that the software can disable the SPI or its peripheral clock before entering a low power mode which does not provide a clock for the p...

Page 924: ...et The SPE bit is cleared This blocks all output from the device and disables the SPI interface The MSTR bit is cleared thus forcing the device into slave mode Use the following software sequence to clear the MODF bit 1 Make a read or write access to the SPIx_SR register while the MODF bit is set 2 Then write to the SPIx_CR1 register To avoid any multiple slave conflicts in a system comprising sev...

Page 925: ... 0 In this case the sampling edge is the rising edge of SCK and NSS assertion and deassertion refer to this sampling edge 30 5 13 TI mode TI protocol in master mode The SPI interface is compatible with the TI protocol The FRF bit of the SPIx_CR2 register can be used to configure the SPI to be compliant with this protocol The clock polarity and phase are forced to conform to the TI protocol require...

Page 926: ...calculation independently of the frame data length which can be fixed to 8 bit or 16 bit For all the other data frame lengths no CRC is available CRC principle CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the SPI is enabled SPE 1 The CRC value is calculated using an odd programmable polynomial on each bit The calculation is processed on the sampling clock edg...

Page 927: ... DMA When SPI communication is enabled with CRC communication and DMA mode the transmission and reception of the CRC at the end of communication is automatic with the exception of reading CRC data in receive only mode The CRCNEXT bit does not have to be handled by the software The counter for the SPI transmission DMA channel has to be set to the number of data frames to transmit excluding the CRC ...

Page 928: ...mally see more details at the product errata sheet At TI mode despite the fact that clock phase and clock polarity setting is fixed and independent on SPIx_CR1 register the corresponding setting CPOL 0 CPHA 1 has to be kept at the SPIx_CR1 register anyway if CRC is applied In addition the CRC calculation has to be reset between sessions by SPI disable sequence with re enable the CRCEN bit describe...

Page 929: ...I can function as an audio I2 S interface when the I2 S capability is enabled by setting the I2SMOD bit in the SPIx_I2SCFGR register This interface mainly uses the same pins flags and interrupts as the SPI 7 EXIIHU 6KLIW UHJLVWHU ELW RPPXQLFDWLRQ 5 EXIIHU ELW 026 6 0DVWHU FRQWURO ORJLF 63 EDXG UDWH JHQHUDWRU 602 6 ILUVW 6 LUVW 63 5 5 5 0675 32 3 LGL PRGH LGL 2 5 1 5 1H W 5 RQO 660 66 GGUHVV DQG GD...

Page 930: ...I2 S uses its own clock generator to produce the communication clock when it is set in master mode This clock generator is also the source of the master clock output Two additional registers are available in I2 S mode One is linked to the clock generator configuration SPIx_I2SPR and the other one is a generic I2 S configuration register SPIx_I2SCFGR audio standard slave master mode data format pac...

Page 931: ...nnel right CHSIDE has no meaning for the PCM protocol Four data and packet frames are available Data may be sent with a format of 16 bit data packed in a 16 bit frame 16 bit data packed in a 32 bit frame 24 bit data packed in a 32 bit frame 32 bit data packed in a 32 bit frame When using 16 bit data extended on 32 bit packet the first 16 bits MSB are the significant bits the 16 bit LSB is forced t...

Page 932: ...ard waveforms 24 bit frame This mode needs two write or read operations to from the SPIx_DR register In transmission mode If 0x8EAA33 has to be sent 24 bit Figure 360 Transmitting 0x8EAA33 In reception mode If data 0x8EAA33 is received 06 9 6 6 DQ EH ELW RU ELW 06 06 6 KDQQHO OHIW KDQQHO ULJKW WUDQVPLVVLRQ UHFHSWLRQ 06 9 6 6 7UDQVPLVVLRQ 5HFHSWLRQ ELW GDWD 06 6 KDQQHO OHIW ELW KDQQHO ULJKW ELW UHP...

Page 933: ...SPIx_DR the TXE flag is set and its interrupt if allowed is generated to load the SPIx_DR register with the new value to send This takes place even if 0x0000 have not yet been sent because it is done by hardware For reception the RXNE flag is set and its interrupt if allowed is generated when the first 16 MSB half word is received In this way more time is provided between two write or read operati...

Page 934: ...t extended to 32 bit packet frame LSB justified standard This standard is similar to the MSB justified standard no difference for the 16 bit and 32 bit full accuracy frame formats The sampling of the input and output signals is the same as for the I2S Philips standard 06 9 6 6 7UDQVPLVVLRQ 5HFHSWLRQ RU ELW GDWD 06 6 KDQQHO OHIW KDQQHO ULJKW 06 06 9 6 6 7UDQVPLVVLRQ 5HFHSWLRQ ELW GDWD 06 6 KDQQHO O...

Page 935: ...shown below Figure 369 Operations required to transmit 0x3478AE In reception mode If data 0x3478AE are received two successive read operations from the SPIx_DR register are required on each RXNE event 06 9 6 6 7UDQVPLVVLRQ 5HFHSWLRQ RU ELW GDWD 06 6 KDQQHO OHIW KDQQHO ULJKW 06 06 9 6 6 7UDQVPLVVLRQ 5HFHSWLRQ ELW GDWD IRUFHG 06 6 KDQQHO OHIW ELW KDQQHO ULJKW ELW UHPDLQLQJ LUVW ZULWH WR DWD UHJLVWHU...

Page 936: ...e of 16 bit data frame extended to 32 bit channel frame In transmission mode when a TXE event occurs the application has to write the data to be transmitted in this case 0x76A3 The 0x000 field is transmitted first extension on 32 bit The TXE flag is set again as soon as the effective data 0x76A3 is sent on SD In reception mode RXNE is asserted as soon as the significant half word is received and n...

Page 937: ...ssertion time is fixed to 13 bits in master mode For short frame synchronization the WS synchronization signal is only one cycle long Figure 374 PCM standard waveforms 16 bit extended to 32 bit packet frame Note For both modes master and slave and for both synchronizations short and long the number of bits between two consecutive pieces of data and so two synchronization signals needs to be specif...

Page 938: ...e This means that the I2SE bit must be set to 1 when WS 1 for I2S Philips standard or when WS 0 for other standards 06Y 9 GXP QRW VLJQLILFDQW GDWD 6 2 6 2 2 32 HIW VDPSOH 5LJKW VDPSOH 6 6 2 2 32 6 2 HIW VDPSOH 5LJKW VDPSOH 6 2 6 2 6DPSOH 6DPSOH 0DVWHU 6 3KLOLSV 6WDQGDUG 0DVWHU 6 06 RU 6 MXVWLILHG 0DVWHU 3 0 VKRUW IUDPH 6 6 2 32 2 32 2 32 2 32 GXP GXP GXP 6 6 2 6 2 6DPSOH 6DPSOH 0DVWHU 3 0 ORQJ IUD...

Page 939: ...rogram the linear divider in order to communicate with the desired audio frequency Figure 377 I2S clock generator architecture 1 Where x can be 2 or 3 Figure 377 presents the communication clock architecture By default the I2Sx clock is always the system clock To achieve high quality audio performance the I2SxCLK clock source can be an external clock mapped to the I2S_CKIN pin Refer to Section 9 4...

Page 940: ...ct signal WS Master clock MCK may be output or not controlled by the MCKOE bit in the SPIx_I2SPR register Table 164 Audio frequency precision using standard 8 MHz HSE 1 SYSCLK MHz I2S_DIV I2S_ODD MCLK Target fS Hz Real fS KHz Error 16 bit 32 bit 16 bit 32 bit 16 bit 32 bit 16 bit 32 bit 72 11 6 1 0 No 96000 97826 09 93750 1 90 2 34 72 23 11 1 1 No 48000 47872 34 48913 04 0 27 1 90 72 25 13 1 0 No ...

Page 941: ...t channel data When data are transferred from the Tx buffer to the shift register TXE is set and data corresponding to the right channel have to be written into the Tx buffer The CHSIDE flag indicates which channel is to be transmitted It has a meaning when the TXE flag is set because the CHSIDE flag is updated when TXE goes high A full frame has to be considered as a left channel data transmissio...

Page 942: ...gth DATLEN 00 and CHLEN 1 using the LSB justified mode I2SSTD 10 a Wait for the second to last RXNE 1 n 1 b Then wait 17 I2 S clock cycles using a software loop c Disable the I2 S I2SE 0 16 bit data length extended on 32 bit channel length DATLEN 00 and CHLEN 1 in MSB justified I2 S or PCM modes I2SSTD 00 I2SSTD 01 or I2SSTD 11 respectively a Wait for the last RXNE b Then wait 1 I2 S clock cycle u...

Page 943: ...be transmitted Compared to the master transmission mode in slave mode CHSIDE is sensitive to the WS signal coming from the external master This means that the slave needs to be ready to transmit the first data before the clock is generated by the master WS assertion corresponds to left channel transmitted first Note The I2SE has to be written at least two PCLK cycles before the first clock of the ...

Page 944: ...un is generated and the OVR flag is set If the bit ERRIE is set in the SPIx_CR2 register an interrupt is generated to indicate the error To switch off the I2S in reception mode I2SE has to be cleared immediately after receiving the last RXNE 1 Note The external master components should have the capability of sending receiving data in 16 bit or 32 bit packets via an audio channel 30 7 8 I2 S status...

Page 945: ...nabling it with configuration if it needs changing This flag has no meaning in the PCM standard for both Short and Long frame modes When the OVR or UDR flag in the SPIx_SR is set and the ERRIE bit in SPIx_CR2 is also set an interrupt is generated This interrupt can be cleared by reading the SPIx_SR status register once the interrupt source has been cleared 30 7 9 I2 S error flags There are three e...

Page 946: ...synchronization between master and slave devices may be due to noisy environment on the CK communication clock or on the WS frame synchronization line An error interrupt can be generated if the ERRIE bit is set The desynchronization flag FRE is cleared by software when the status register is read 30 7 10 DMA features In I2 S mode the DMA works in exactly the same way as it does in SPI mode There i...

Page 947: ... Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode 0 Output disabled receive only mode 1 Output enabled transmit only mode Note In master mode the MOSI pin is used and in slave mode the MISO pin is used This bit is not used in I2 S mode Bit 13 CRCEN Hardware CRC calculation enable 0 CRC calculation disabled 1 CRC cal...

Page 948: ...ot used in I2 S mode and SPI TI mode Bit 8 SSI Internal slave select This bit has an effect only when the SSM bit is set The value of this bit is forced onto the NSS pin and the I O value of the NSS pin is ignored Note This bit is not used in I2 S mode and SPI TI mode Bit 7 LSBFIRST Frame format 0 data is transmitted received with the MSB first 1 data is transmitted received with the LSB first Not...

Page 949: ...the total number of data to transmit by DMA is odd or even It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used data length 8 bit and write access to SPIx_DR is 16 bit wide It has to be written when the SPI is disabled SPE 0 in the SPIx_CR1 register 0 Number of data to transfer is even 1 Number of data to transfer is odd Note Refer to Procedure fo...

Page 950: ... enable 0 RXNE interrupt masked 1 RXNE interrupt not masked Used to generate an interrupt request when the RXNE flag is set Bit 5 ERRIE Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs CRCERR OVR MODF in SPI mode FRE at TI mode 0 Error interrupt is masked 1 Error interrupt is enabled Bit 4 FRF Frame format 0 SPI Motorola mode 1 SPI TI mode Note...

Page 951: ...when the SPI interface is enabled The SPI interface cannot work in a multimaster environment Note This bit is not used in SPI TI mode Bit 1 TXDMAEN Tx buffer DMA enable When this bit is set a DMA request is generated whenever the TXE flag is set 0 Tx buffer DMA disabled 1 Tx buffer DMA enabled Bit 0 RXDMAEN Rx buffer DMA enable When this bit is set a DMA request is generated whenever the RXNE flag...

Page 952: ...ation is enabled Bit 8 FRE Frame format error This flag is used for SPI in TI slave mode and I2S slave mode Refer to Section 30 5 11 SPI error flags and Section 30 7 9 I2S error flags This flag is set by hardware and reset when SPIx_SR is read by software 0 No frame format error 1 A frame format error occurred Bit 7 BSY Busy flag 0 SPI or I2S not busy 1 SPI or I2S is busy in communication or Tx bu...

Page 953: ...ceived 1 Channel Right has to be transmitted or has been received Note This bit is not used in SPI mode It has no significance in PCM mode Bit 1 TXE Transmit buffer empty 0 Tx buffer not empty 1 Tx buffer empty Bit 0 RXNE Receive buffer not empty 0 Rx buffer empty 1 Rx buffer not empty 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 DR 15 0 D...

Page 954: ...Note The polynomial value should be odd only No even value is supported Bits 15 0 CRCPOLY 15 0 CRC polynomial register This register contains the polynomial for the CRC calculation The CRC polynomial 0007h is the reset value of this register Another polynomial can be configured as required ...

Page 955: ...selected CRCL bit in the SPIx_CR1 register is set CRC calculation is done based on any CRC16 standard Note A read to this register when the BSY Flag is set could return an incorrect value These bits are not used in I2 S mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TxCRC 15 0 r r r r r r r r r r r r r r r r Bits 15 0 TxCRC 15 0 Tx CRC register When CRC calculation is enabled the TxCRC 7 0 bits contai...

Page 956: ...is not used in SPI mode Bits 9 8 I2SCFG I2S configuration mode 00 Slave transmit 01 Slave receive 10 Master transmit 11 Master receive Note These bits should be configured when the I2S is disabled They are not used in SPI mode Bit 7 PCMSYNC PCM frame synchronization 0 Short frame synchronization 1 Long frame synchronization Note This bit has a meaning only if I2SSTD 11 PCM standard is used It is n...

Page 957: ...he SD and WS signals Bits 2 1 DATLEN Data length to be transferred 00 16 bit data length 01 24 bit data length 10 32 bit data length 11 Not allowed Note For correct operation these bits should be configured when the I2 S is disabled They are not used in SPI mode Bit 0 CHLEN Channel length number of bits per audio channel 0 16 bit wide 1 32 bit wide The bit write operation has a meaning only if DAT...

Page 958: ...only when the I2 S is in master mode It is not used in SPI mode Bit 8 ODD Odd factor for the prescaler 0 Real divider value is I2SDIV 2 1 Real divider value is I2SDIV 2 1 Refer to Section 30 7 4 on page 937 Note This bit should be configured when the I2S is disabled It is used only when the I2S is in master mode It is not used in SPI mode Bits 7 0 I2SDIV 7 0 I2S linear prescaler I2SDIV 7 0 0 or I2...

Page 959: ... Res Res Res Res Res Res Res Res Res Res Res Res Res FTLVL 1 0 FRLVL 1 0 FRE BSY OVR MODF CRCERR UDR CHSIDE TXE RXNE Reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 0x0C SPIx_DR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res DR 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 SPIx_CRCPR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CRCPOLY 15 0 Reset value 0 0 0 0 0 0...

Page 960: ...supporting the CAN Time Triggered Communication option 31 2 bxCAN main features Supports CAN protocol version 2 0 A B Active Bit rates up to 1 Mbit s Supports the Time Triggered Communication option Transmission Three transmit mailboxes Configurable transmit priority Time Stamp on SOF transmission Reception Two receive FIFOs with three stages Scalable filter banks 14 filter banks Identifier list f...

Page 961: ...ication tasks for a long time period without losing messages The standard HLP Higher Layer Protocol based on standard CAN drivers requires an efficient interface to the CAN controller Figure 378 CAN network topology 31 3 1 CAN 2 0B active core The bxCAN module handles the transmission and the reception of CAN messages fully autonomously Standard identifiers 11 bit and extended identifiers 29 bit a...

Page 962: ... can be done while the hardware is in Initialization mode To enter this mode the software sets the INRQ bit in the CAN_MCR register and waits until the hardware has confirmed the request by setting the INAK bit in the CAN_MSR register To leave Initialization mode the software clears the INQR bit bxCAN has left Initialization mode once the INAK bit has been cleared by hardware While in Initializati...

Page 963: ...setting the SLEEP bit in the CAN_MCR register In this mode the bxCAN clock is stopped however software can still access the bxCAN mailboxes If software requests entry to initialization mode by setting the INRQ bit while bxCAN is in Sleep mode it must also clear the SLEEP bit bxCAN can be woken up exit Sleep mode either by software clearing the SLEEP bit or on detection of CAN bus activity On CAN b...

Page 964: ...egister must be reset to enter Normal mode 31 5 1 Silent mode The bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register In Silent mode the bxCAN is able to receive valid data frames and valid remote frames but it sends only recessive bits on the CAN bus and it cannot start a transmission If the bxCAN has to send a dominant bit ACK bit overload flag active error flag the b...

Page 965: ...the acknowledge slot of a data remote frame in Loop Back Mode In this mode the bxCAN performs an internal feedback from its Tx output to its Rx input The actual value of the CANRX input pin is disregarded by the bxCAN The transmitted messages can be monitored on the CANTX pin 31 5 3 Loop back combined with silent mode It is also possible to combine Loop Back mode and Silent mode by setting the LBK...

Page 966: ...s the highest priority it will be scheduled for transmission The transmission of the message of the scheduled mailbox will start enter transmit state when the CAN bus becomes idle Once the mailbox has been successfully transmitted it will become empty again The hardware indicates a successful transmission by setting the RQCP and TXOK bits in the CAN_TSR register If the transmission fails the cause...

Page 967: ...ation option of the CAN standard To configure the hardware in this mode the NART bit in the CAN_MCR register must be set In this mode each transmission is started only once If the first attempt fails due to an arbitration loss or an error the hardware will not automatically restart the message transmission At the end of the first transmission attempt the hardware considers the request as completed...

Page 968: ...the FIFO through the FIFO output mailbox Valid message A received message is considered as valid when it has been received correctly according to the CAN protocol no error until the last but one bit of the EOF field and It passed through the identifier filtering successfully see Section 31 7 4 Identifier filtering Figure 384 Receive FIFO states FIFO management Starting from the empty state the fir...

Page 969: ...g message In this case the latest messages will be always available to the application If the FIFO lock function is enabled RFLM bit in the CAN_MCR register set the most recent message will be discarded and the software will have the three oldest messages in the FIFO available Reception related interrupts Once a message has been stored in the FIFO the FMP 1 0 bits are updated and an interrupt requ...

Page 970: ... identifiers All bits of the incoming identifier must match the bits specified in the filter registers Filter bank scale and mode configuration The filter banks are configured by means of the corresponding CAN_FMR register To configure a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR register The filter scale is configured by means of the corresponding FSCx bit in the C...

Page 971: ...ues Use the Filter Match Index as an index on an array to access the data destination location For non masked filters the software no longer has to compare the identifier If the filter is masked the software reduces the comparison to the masked bits only The index value of the filter number does not take into account the activation state of the filter banks In addition two independent numbering sc...

Page 972: ...ing to the following priority rules A 32 bit filter takes priority over a 16 bit filter For filters of equal scale priority is given to the Identifier List mode over the Identifier Mask mode For filters of equal scale and mode priority is given by the filter number the lower the number the higher the priority LVW ELW LOWHU 2 LOWHU LOWHU 2 LOWHU 1XP 1XP DQN DQN GHQWLILHU 06 9 0DVN ELW LVW ELW HDFWL...

Page 973: ... in the filters the message is discarded by hardware without disturbing the software 31 7 5 Message storage The interface between the software and the hardware for the CAN messages is implemented by means of mailboxes A mailbox contains all information related to a message identifier data control status and time stamp information Transmit mailbox The software sets up the message to be transmitted ...

Page 974: ...e available The filter match index is stored in the MFMI field of the CAN_RDTxR register The 16 bit time stamp value is stored in the TIME 15 0 field of CAN_RDTxR Figure 388 CAN error state diagram Table 167 Transmit mailbox mapping Offset to transmit mailbox base address Register name 0 CAN_TIxR 4 CAN_TDTxR 8 CAN_TDLxR 12 CAN_TDHxR Table 168 Receive mailbox mapping Offset to receive mailbox base ...

Page 975: ... recovering sequence automatically after it has entered Bus Off state If ABOM is cleared the software must initiate the recovering sequence by requesting bxCAN to enter and to leave initialization mode Note In initialization mode bxCAN does not monitor the CANRX signal therefore it cannot complete the recovery sequence To recover bxCAN must be in normal mode 31 7 7 Bit timing The bit timing logic ...

Page 976: ...ened by up to SJW so that the transmit point is moved earlier As a safeguard against programming errors the configuration of the Bit Timing Register CAN_BTR is only possible while the device is in Standby mode Note For a detailed description of the CAN bit timing and resynchronization mechanism refer to the ISO 11898 standard Figure 389 Bit timing 6 1 B6 7 6 0 17 6 120 1 7 7 0 WT W 6 6 03 32 17 75...

Page 977: ...LRQ LHOG WUO LHOG DWD LHOG 5 LHOG LHOG QWHU UDPH 6SDFH RU 2YHUORDG UDPH DWD UDPH 6WDQGDUG GHQWLILHU 1 5 2 62 575 U QWHU UDPH 6SDFH 62 575 U 2 5 UELWUDWLRQ LHOG WUO LHOG 5 LHOG LHOG QWHU UDPH 6SDFH RU 2YHUORDG UDPH 5HPRWH UDPH QWHU UDPH 6SDFH RU UURU UDPH 2YHUORDG UDPH QG RI UDPH RU UURU HOLPLWHU RU 2YHUORDG HOLPLWHU 2YHUORDG ODJ 2YHUORDG FKR 2YHUORDG HOLPLWHU 1RWHV 1 62 6WDUW 2I UDPH GHQWLILHU 575...

Page 978: ...n the CAN_TSR register set Transmit mailbox 1 becomes empty RQCP1 bit in the CAN_TSR register set Transmit mailbox 2 becomes empty RQCP2 bit in the CAN_TSR register set The FIFO 0 interrupt can be generated by the following events Reception of a new message FMP0 bits in the CAN_RF0R register are not 00 FIFO0 full condition FULL0 bit in the CAN_RF0R register set FIFO0 overrun condition FOVR0 bit in...

Page 979: ...he CAN hardware is in initialization mode Although the transmission of incorrect data will not cause problems at the CAN network level it can severely disturb the application A transmit mailbox can be only modified by software while it is in empty state refer to Figure 383 Transmit mailbox states The filter values can be modified either deactivating the associated filter banks or by setting the FI...

Page 980: ... the software has first set and cleared the INRQ bit of the CAN_MCR register 1 The Bus Off state is left automatically by hardware once 128 occurrences of 11 recessive bits have been monitored For detailed information on the Bus Off state refer to Section 31 7 6 Error management Bit 5 AWUM Automatic wakeup mode This bit controls the behavior of the CAN hardware on message reception during Sleep mo...

Page 981: ...its have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception Hardware signals this event by clearing the INAK bit in the CAN_MSR register Software sets this bit to request the CAN hardware to enter initialization mode Once software has set the INRQ bit the CAN hardware waits until the current CAN activity transmission or reception is completed ...

Page 982: ...that the CAN hardware is now in Sleep mode This bit acknowledges the Sleep mode request from the software set SLEEP bit in CAN_MCR register This bit is cleared by hardware when the CAN hardware has left Sleep mode to be synchronized on the CAN bus To be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the CAN RX signal Note The process of leaving Sleep mode i...

Page 983: ...th the lowest priority Bit 23 ABRQ2 Abort request for mailbox 2 Set by software to abort the transmission request for the corresponding mailbox Cleared by hardware when the mailbox becomes empty Setting this bit has no effect when the mailbox is not pending for transmission Bits 22 20 Reserved must be kept at reset value Bit 19 TERR2 Transmission error of mailbox 2 This bit is set when the previou...

Page 984: ...the corresponding mailbox Cleared by hardware when the mailbox becomes empty Setting this bit has no effect when the mailbox is not pending for transmission Bits 6 4 Reserved must be kept at reset value Bit 3 TERR0 Transmission error of mailbox0 This bit is set when the previous TX failed due to an error Bit 2 ALST0 Arbitration lost for mailbox0 This bit is set when the previous TX failed due to a...

Page 985: ...0 FMP0 1 0 FIFO 0 message pending These bits indicate how many messages are pending in the receive FIFO FMP is increased each time the hardware stores a new message in to the FIFO FMP is decreased each time the software releases the output mailbox by setting the RFOM0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 ...

Page 986: ...IE rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 18 Reserved must be kept at reset value Bit 17 SLKIE Sleep interrupt enable 0 No interrupt when SLAKI bit is set 1 Interrupt generated when SLAKI bit is set Bit 16 WKUIE Wakeup interrupt enable 0 No interrupt when WKUI is set 1 Interrupt generated when WKUI bit is set Bit 15 ERRIE Error interrupt enable 0 No interrupt will be generated when an error c...

Page 987: ...Interrupt generated when state of FMP 1 0 bits are not 00b Bit 3 FOVIE0 FIFO overrun interrupt enable 0 No interrupt when FOVR bit is set 1 Interrupt generated when FOVR bit is set Bit 2 FFIE0 FIFO full interrupt enable 0 No interrupt when FULL bit is set 1 Interrupt generated when FULL bit is set Bit 1 FMPIE0 FIFO message pending interrupt enable 0 No interrupt generated when state of FMP 1 0 bit...

Page 988: ...or condition of the last error detected on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared to 0 The LEC 2 0 bits can be set to value 0b111 by software They are updated by hardware to indicate the current communication status 000 No Error 001 Stuff Error 010 Form Error 011 Acknowledgment Error 100 Bit recessive Error 101 Bit dominant ...

Page 989: ... 31 SILM Silent mode debug 0 Normal operation 1 Silent Mode Bit 30 LBKM Loop back mode debug 0 Loop Back Mode disabled 1 Loop Back Mode enabled Bits 29 26 Reserved must be kept at reset value Bits 25 24 SJW 1 0 Resynchronization jump width These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization tRJW tq x SJW 1 0 ...

Page 990: ...ID 10 0 EXID 28 18 EXID 17 13 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXID 12 0 IDE RTR TXRQ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 21 STID 10 0 EXID 28 18 Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier depending on the IDE bit value Bit 20 3 EXID 17 0 Extended identifier The L...

Page 991: ...mission Bits 15 9 Reserved must be kept at reset value Bit 8 TGT Transmit global time This bit is active only when the hardware is in the Time Trigger Communication mode TTCM bit of the CAN_MCR register is set 0 Time stamp TIME 15 0 is not sent 1 Time stamp TIME 15 0 value is sent in the last two data bytes of the 8 byte message TIME 7 0 in data byte 7 and TIME 15 8 in data byte 6 replacing the da...

Page 992: ...3 7 0 DATA2 7 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA1 7 0 DATA0 7 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 24 DATA3 7 0 Data byte 3 Data byte 3 of the message Bits 23 16 DATA2 7 0 Data byte 2 Data byte 2 of the message Bits 15 8 DATA1 7 0 Data byte 1 Data byte 1 of the message Bits 7 0 DATA0 7 0 Data byte 0 Data byte 0 of the m...

Page 993: ...te 4 Data byte 4 of the message 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 STID 10 0 EXID 28 18 EXID 17 13 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXID 12 0 IDE RTR Res r r r r r r r r r r r r r r r Bits 31 21 STID 10 0 EXID 28 18 Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier depending on the IDE bit val...

Page 994: ...0 r r r r r r r r r r r r Bits 31 16 TIME 15 0 Message time stamp This field contains the 16 bit timer value captured at the SOF detection Bits 15 8 FMI 7 0 Filter match index This register contains the index of the filter the message stored in the mailbox passed through For more details on identifier filtering refer to Section 31 7 4 Identifier filtering on page 969 Filter Match Index paragraph B...

Page 995: ...DATA3 7 0 DATA2 7 0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA1 7 0 DATA0 7 0 r r r r r r r r r r r r r r r r Bits 31 24 DATA3 7 0 Data Byte 3 Data byte 3 of the message Bits 23 16 DATA2 7 0 Data Byte 2 Data byte 2 of the message Bits 15 8 DATA1 7 0 Data Byte 1 Data byte 1 of the message Bits 7 0 DATA0 7 0 Data Byte 0 Data byte 0 of the message A message can contain...

Page 996: ...A5 7 0 Data Byte 5 Data byte 1 of the message Bits 7 0 DATA4 7 0 Data Byte 4 Data byte 0 of the message 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res FINIT rw Bits 31 1 Reserved must be kept at reset value Bit 0 FINIT Filter initializat...

Page 997: ... Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res FBM13 FBM12 FBM11 FBM10 FBM9 FBM8 FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 14 Reserved must be kept at reset value Bits 13 0 FBMx Filter mode Mode of the registers of Filter x 0 Two 32 bit registers of filter bank x are in Identifier Mask m...

Page 998: ...ue Bits 13 0 FFAx Filter FIFO assignment for filter x The message passing through this filter will be stored in the specified FIFO 0 Filter assigned to FIFO 0 1 Filter assigned to FIFO 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res FACT1 3 FACT1 2 FACT1 1 FACT1 0 FACT9 FACT8 FACT7 FACT6...

Page 999: ...he register mapping addresses of the filter banks refer to the Table 169 on page 1000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0 rw rw rw rw rw rw rw rw rw rw ...

Page 1000: ...Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res RFOM0 FOVR0 FULL0 Res FMP0 1 0 Reset value 0 0 0 0 0 0x010 CAN_RF1R Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res RFOM1 FOVR1 FULL1 Res FMP1 1 0 Reset value 0 0 0 0 0 0x014 CAN_IER Res Res Res Res Res Res Res Res Res Res Res Res Res Res SLKIE...

Page 1001: ... x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x19C CAN_TDH1R DATA7 7 0 DATA6 7 0 DATA5 7 0 DATA4 7 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x1A0 CAN_TI2R STID 10 0 EXID 28 18 EXID 17 0 IDE RTR TXRQ Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0x1A4 CAN_TDT2R TIME 15 0 Res Res Res Res Res Res Res TGT Res Res Res Res DL...

Page 1002: ...5 7 0 DATA4 7 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x1D0 0x1FF Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x200 CAN_FMR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res FINIT Reset value 1 0x204 CAN_...

Page 1003: ...s Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 0x240 CAN_F0R1 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x244 CAN_F0R2 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x248 CAN_F1R1 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x24C...

Page 1004: ...ulk isochronous endpoint support USB Suspend Resume operations Frame locked clock pulse generation The following additional feature is also available depending on the product implementation see Section 32 3 USB implementation USB 2 0 Link Power Management support 32 3 USB implementation Table 170 describes the USB implementation in the devices Table 170 STM32F302xx USB implementation USB features ...

Page 1005: ...s handling data transmission reception and processing handshake packets as required by the USB standard Transaction formatting is performed by the hardware including CRC generation and checking Each endpoint is associated with a buffer description block indicating where the endpoint related memory area is located how large it is or how many bytes must be transmitted When a token for a valid functi...

Page 1006: ...onnected directly to a wakeup line to allow the system to immediately restart the normal clock generation and or support direct clock start stop 32 4 1 Description of USB blocks The USB peripheral implements all the features related to USB interfacing which include the following blocks Serial Interface Engine SIE The functions of this block include synchronization pattern recognition bit stuffing ...

Page 1007: ...p to 1024 bytes structured as 512 half words by 16 bits Arbiter This block accepts memory requests coming from the APB1 bus and from the USB interface It resolves the conflicts by giving priority to APB1 accesses while always reserving half of the memory bandwidth to complete all USB transfers This time duplex scheme implements a virtual dual port SRAM that allows memory access while an USB transa...

Page 1008: ... bit in the CNTR register Clearing the ISTR register then removes any spurious pending interrupt before any other macrocell operation is enabled At system reset the microcontroller must initialize all required registers and the packet buffer description table to make the USB peripheral able to properly generate interrupts and data transfers All registers not specific to any endpoint must be initia...

Page 1009: ... clock must have a minimum frequency of 10 MHz to avoid data overrun underrun problems Each endpoint is associated with two packet buffers usually one for transmission and the other one for reception Buffers can be placed anywhere inside the packet memory because their location and size is specified in a buffer description table which is also located in the packet memory at the address indicated b...

Page 1010: ...ndpoint must be enabled using the STAT_TX bits in the USB_EPnR register and COUNTn_TX must be initialized For reception STAT_RX bits must be set to enable reception and COUNTn_RX must be written with the allocated buffer size using the BL_SIZE and NUM_BLOCK fields Unidirectional endpoints except Isochronous and double buffered bulk endpoints need to initialize only bits and registers related to th...

Page 1011: ... in the USB_ISTR register Servicing of the CTR_TX event starts clearing the interrupt bit the application software then prepares another buffer full of data to be sent updates the COUNTn_TX table location with the number of byte to be transmitted during the next transfer and finally sets STAT_TX to 11 VALID to re enable transmissions While the STAT_TX bits are equal to 10 NAK any IN request addres...

Page 1012: ...iously listed actions take place The application software must first identify the endpoint which is requesting microcontroller attention by examining the EP_ID and DIR bits in the USB_ISTR register The CTR_RX event is serviced by first determining the transaction type SETUP bit in the USB_EPnR register the application software must clear the interrupt flag bit and get the number of received bytes ...

Page 1013: ...ll different endpoint types defined by the USB standard represent different traffic models and describe the typical requirements of different kind of data transfer operations When large portions of data are to be transferred between the host PC and the USB function the bulk endpoint type is the most suited model This is because the host schedules bulk transactions so as to fill all the available b...

Page 1014: ...uencing due to the unidirectional constraint required by double buffering feature the other one can be used by the application software to show which buffer it is currently using This new buffer flag is called SW_BUF In the following table the correspondence between USB_EPnR register bits and DTOG SW_BUF definition is explained for the cases of transmission and reception double buffered bulk endpo...

Page 1015: ...CTR event notification by clearing the interrupt flag and starting any required handling of the completed transaction When the application packet buffer usage is over the software toggles the SW_BUF bit writing 1 to it to notify the USB peripheral about the availability of that buffer In this way the number of NAKed transactions is limited only by the application elaboration time of a transaction ...

Page 1016: ...efined by the DTOG bit related to the endpoint direction DTOG_RX for reception isochronous endpoints DTOG_TX for transmission isochronous endpoints both in the related USB_EPnR register according to Table 173 As it happens with double buffered bulk endpoints the USB_EPnR registers used to implement Isochronous endpoints are forced to be used as unidirectional ones In case it is required to have Is...

Page 1017: ...ed Once the device is suspended its normal operation can be restored by a so called RESUME sequence which can be started from the host PC or directly from the peripheral itself but it is always terminated by the host PC The suspended USB peripheral must be anyway able to detect a RESET sequence reacting to this event as a normal USB reset event The actual procedure used to suspend the USB peripher...

Page 1018: ..._CNTR register 3 If the resume triggering event has to be identified bits RXDP and RXDM in the USB_FNR register can be used according to Table 174 which also lists the intended software action in all the cases If required the end of resume or reset sequence can be detected monitoring the status of the above mentioned bits by checking when they reach the 10 configuration which represent the Idle bu...

Page 1019: ...ters These registers affect the general behavior of the USB peripheral defining operating mode interrupt handling device address and giving access to the current frame number updated by the host PC USB control register USB_CNTR Address offset 0x40 Reset value 0x0003 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTR M PMAOVR M ERR M WKUP M SUSP M RESET M SOF M ESOF M L1REQ M Res L1 RESUME RE SUME F SUSP LP...

Page 1020: ...st is generated when the corresponding bit in the USB_ISTR register is set Note If LPM is not supported this bit is not implemented and considered as reserved Please refer to Section 32 3 USB implementation Bit 6 Reserved Bit 5 L1RESUME LPM L1 Resume request The microcontroller can set this bit to send a LPM L1 Resume signal to the host After the signaling ends this bit is cleared by hardware Note...

Page 1021: ...the corresponding USB_EPnR register the CTR bit is actually a read only bit For endpoint related interrupts the software can use the Direction of Transaction DIR and EP_ID read only bits to identify which endpoint made the last interrupt request and called the corresponding interrupt service routine Bit 2 LP_MODE Low power mode This mode is used when the suspend mode power constraints require that...

Page 1022: ...ever occur during normal operations Since the failed transaction is retried by the host the application software has the chance to speed up device operations during this interrupt handling to be ready for the next transaction retry however this does not happen during Isochronous transfers no isochronous transaction is anyway retried leading to a loss of data in this case This bit is read write but...

Page 1023: ...en and writing 1 has no effect Bit 9 SOF Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception this could be useful for isochronous ap...

Page 1024: ...the endpoint number which generated the interrupt request If several endpoint transactions are pending the hardware writes the endpoint identifier related to the endpoint having the highest priority defined in the following way Two endpoint sets are defined in order of priority Isochronous and double buffered bulk endpoints are considered first and then the other endpoints are examined If more tha...

Page 1025: ...ast received SOF packet The frame number is incremented for every frame sent by the host and it is useful for Isochronous transfers This bit field is updated on the generation of an SOF interrupt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res EF ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 rw rw rw rw rw rw rw rw Bits 15 8 Reserved Bit 7 EF Enable function This bit is set by the softw...

Page 1026: ...and size and it must be aligned to an 8 byte boundary the 3 least significant bits are always 0 At the beginning of every transaction addressed to this device the USB peripheral reads the element of this table related to the addressed endpoint to get its buffer start location and the buffer size Refer to Structure and usage of packet buffers on page 1008 Bits 2 0 Reserved forced by hardware to 0 1...

Page 1027: ...ndpoint related interrupt condition which is always activated The type of occurred transaction OUT or SETUP can be determined from the SETUP bit described below A transaction ended with a NAK or STALL handshake does not set this bit since no data is actually transferred as in the case of protocol errors or data toggle mismatches This bit is read write but only 0 can be written writing 1 has no eff...

Page 1028: ...X is at 0 This bit is read only Bits 10 9 EP_TYPE 1 0 Endpoint type These bits configure the behavior of this endpoint as described in Table 176 Endpoint type encoding on page 1030 Endpoint 0 must always be a control endpoint and each USB function must have at least one control endpoint which has address 0 but there may be other control endpoints if required Only control endpoints handle SETUP tra...

Page 1029: ... control one or to force a specific data toggle packet buffer usage When the application software writes 0 the value of DTOG_TX remains unchanged while writing 1 makes the bit value toggle This bit is read write but it can only be toggled by writing 1 Bits 5 4 STAT_TX 1 0 Status bits for transmission transfers These bits contain the information about the endpoint status listed in Table 178 These b...

Page 1030: ...ing 00 BULK DBL_BUF 01 CONTROL STATUS_OUT 10 ISO Not used 11 INTERRUPT Not used Table 178 Transmission status encoding STAT_TX 1 0 Meaning 00 DISABLED all transmission requests addressed to this endpoint are ignored 01 STALL the endpoint is stalled and all transmission requests result in a STALL handshake 10 NAK the endpoint is naked and all transmission requests result in a NAK handshake 11 VALID...

Page 1031: ...ket memory on these devices should be accessed only by byte 8 bit or half word 16 bit accesses Word 32 bit accesses are not allowed The first packet memory location is located at 0x4000 6000 The buffer descriptor table entry associated with the USB_EPnR registers is described below A thorough explanation of packet buffers and the buffer descriptor table usage can be found in Structure and usage of...

Page 1032: ...byte count n USB_COUNTn_RX Address offset 1 x 16 bits word access scheme USB_BTABLE n 16 12 Address offset 2 x 16 bits word access scheme USB_BTABLE n 8 6 USB local address USB_BTABLE n 8 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res COUNTn_TX 9 0 rw rw rw rw rw rw rw rw rw rw Bits 15 10 These bits are not used since packet size is limited by USB specifications to 1023 bytes Thei...

Page 1033: ...2 1 0 BLSIZE NUM_BLOCK 4 0 COUNTn_RX 9 0 rw rw rw rw rw rw r r r r r r r r r r Bit 15 BL_SIZE Block size This bit selects the size of memory block used to define the allocated buffer area If BL_SIZE 0 the memory block is 2 byte large which is the minimum block allowed in a half word wide memory With this block size the allocated buffer size ranges from 2 to 62 bytes If BL_SIZE 1 the memory block i...

Page 1034: ...SB 1036 15 01111 30 bytes 512 bytes 16 10000 32 bytes 544 bytes 29 11101 58 bytes 960 bytes 30 11110 60 bytes 992 bytes 31 11111 62 bytes N A Table 179 Definition of allocated buffer memory continued Value of NUM_BLOCK 4 0 Memory allocated when BL_SIZE 0 Memory allocated when BL_SIZE 1 ...

Page 1035: ... RX 1 0 SETUP EP TYPE 1 0 EP_KIND CTR_TX DTOG_TX STAT_ TX 1 0 EA 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 USB_EP5R Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res CTR_RX DTOG_RX STAT_ RX 1 0 SETUP EP TYPE 1 0 EP_KIND CTR_TX DTOG_TX STAT_ TX 1 0 EA 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x18 USB_EP6R Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Re...

Page 1036: ...Res Res Res Res Res Res Res BTABLE 15 3 Res Res Res Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0x54 USB_LPMCSR Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res BESL 3 0 REMWAKE Res LPMACK LPMEN Reset value 0 0 0 0 0 0 0 Table 180 USB register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ...

Page 1037: ...e core and the system may be restored and program execution resumed The debug features are used by the debugger host when connecting to and debugging the STM32F302xx MCUs Two interfaces for debug are available Serial wire JTAG debug port Figure 395 Block diagram of STM32 MCU and Cortex M4 F level debug support Note The debug features embedded in the Cortex M4 core are a subset of the ARM CoreSight...

Page 1038: ... debug feature supported by the ARM Cortex M4 F core refer to the Cortex M4 with FPU r0p1 Technical Reference Manual and to the CoreSight Design Kit r0p1 TRM see Section 33 2 Reference ARM documentation 33 2 Reference ARM documentation Cortex M4 F r0p1 Technical Reference Manual TRM It is available from http infocenter arm com ARM Debug Interface V5 ARM CoreSight Design Kit revision r0p1 Technical...

Page 1039: ... JTAG DP and enables the SW DP This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins This sequence is 1 Send more than 50 TCK cycles with TMS SWDIO 1 2 Send the 16 bit sequence on TMS SWDIO 0111100111100111 MSB transmitted first 3 Send more than 50 TCK cycles with TMS SWDIO 1 33 4 Pinout and debug port pins The STM32F302xx MCUs are available in various packages with diff...

Page 1040: ...r This is because the deactivation of the JTAGSW pins is done in two cycles to guarantee a clean level on the nTRST and TCK input signals of the core Cycle 1 the JTAGSW input signals to the core are tied to 1 or 0 to 1 for nTRST TDI and TMS to 0 for TCK Cycle 2 the GPIO controller takes the control signals of the SWJTAG IO pins like controls of direction pull up down Schmitt trigger activation etc...

Page 1041: ...ernal pull up JTDI Internal pull up JTMS SWDIO Internal pull up TCK SWCLK Internal pull down Once a JTAG IO is released by the user software the GPIO controller takes control again The reset states of the GPIO control registers put the I Os in the equivalent state NJTRST Input pull up JTDI Input pull up JTMS SWDIO Input pull up JTCK SWCLK Input pull down JTDO Input floating The software can then u...

Page 1042: ... the debug pins remember that they will be first configured either in input pull up nTRST TMS TDI or pull down TCK or output tristate TDO for a certain duration after reset until the instant when the user software releases the pins When debug pins JTAG or SW or TRACE are mapped changing the corresponding IO pin configuration in the IOPORT controller has no effect 33 5 STM32F302xx JTAG TAP connecti...

Page 1043: ...re several ID codes inside the STM32F302xx MCUs ST strongly recommends tools designers to lock their debuggers using the MCU DEVICE ID code located in the external PPB memory map at address 0xE0042000 RXQGDU VFDQ 7 3 1 7567 RUWH 0 7 3 706 706 Q7567 706 Q7567 7 7 2 7 7 2 7 7 2 6 3 670 0 8 6HOHFWHG 5 LV ELW ZLGH 5 LV ELW ZLGH DL F ...

Page 1044: ... JTAG ID code equal to 0x06432041 33 6 3 Cortex M4 F TAP The TAP of the ARM Cortex M4 F integrates a JTAG ID code This ID code is the ARM default one and has not been modified This code is only accessible by the JTAG Debug Port This code is 0x4BA00477 corresponds to Cortex M4 F r0p1 see Section 33 2 Reference ARM documentation Only the DEV_ID 11 0 should be used for identification by the debugger ...

Page 1045: ... TRM for references please see Section 33 2 Reference ARM documentation Table 183 JTAG debug port data registers IR 3 0 Data register Details 1111 BYPASS 1 bit 1110 IDCODE 32 bits ID CODE 0x3BA00477 ARM Cortex M4 F r0p1 ID Code 1010 DPACC 35 bits Debug port access register This initiates a debug port and allows access to a debug port register When transferring data IN Bits 34 3 DATA 31 0 32 bit da...

Page 1046: ...ed Bit 0 DAPABORT write 1 to generate a DAP abort Table 184 32 bit debug port registers addressed through the shifted value A 3 2 Address A 3 2 value Description 0x0 00 Reserved must be kept at reset value 0x4 01 DP CTRL STAT register Used to Request a system or debug power up Configure the transfer operation for AP accesses Control the pushed compare and pushed verify operations Read some status ...

Page 1047: ...his can be adjusted by configuring the SWCLK frequency 33 8 2 SW protocol sequence Each sequence consist of three phases 1 Packet request 8 bits transmitted by the host 2 Acknowledge response 3 bits transmitted by the target 3 Data transfer phase 33 bits transmitted by the host or the target Refer to the Cortex M4 F r0p1 TRM for a detailed description of DPACC and APACC registers The packet reques...

Page 1048: ...W ID CODE register Otherwise the target will issue a FAULT acknowledge response on another transactions Further details of the SW DP state machine can be found in the Cortex M4 F r0p1 TRM and the CoreSight Design Kit r0p1TRM 33 8 4 DP and AP read write accesses Read accesses to the DP are not posted the target response can be immediate if ACK OK or can be delayed if ACK WAIT Read accesses to the A...

Page 1049: ...e is not set to ST code 0x2BA01477 identifies the SW DP 00 Write ABORT 01 Read Write 0 DP CTRL STAT Purpose is to request a system or debug power up configure the transfer operation for AP accesses control the pushed compare and pushed verify operations read some status flags overrun power up acknowledges 01 Read Write 1 WIRE CONTROL Purpose is to configure the physical serial port protocol like t...

Page 1050: ...AHP AP resisters are 6 bits wide up to 64 words or 256 bytes and consists of d Bits 7 4 the bits 7 4 APBANKSEL of the DP SELECT register e Bits 3 2 the 2 address bits of A 3 2 of the 35 bit packet request for SW DP The AHB AP of the Cortex M4 F includes 9 x 32 bits registers Refer to the Cortex M4 F r0p1 TRM for further details Table 189 Cortex M4 F AHB AP registers Address offset Register name No...

Page 1051: ...ex M4 F differentiates the reset of the debug part generally PORRESETn and the other one SYSRESETn This way it is possible for the debugger to connect under System Reset programming the Core Debug Registers to halt the core when fetching the reset vector Then the host can release the system reset and the core will immediately halt without having executed any instructions In addition it is possible...

Page 1052: ...feature gives the possibility to correct software bugs located in the Code Memory Space The use of a Software Patch or a Hardware Breakpoint is exclusive The FPB consists of 2 literal comparators for matching against literal loads from Code Space and remapping to a corresponding area in the System Space 6 instruction comparators for matching against instruction fetches from Code Space They can be ...

Page 1053: ... for low power modes To enter low power mode the instruction WFI or WFE must be executed The MCU implements several low power modes which can either deactivate the CPU clock or reduce the power of the CPU The core does not allow FCLK or HCLK to be turned off during a debug session As these are required for the debugger connection during a debug they must remain active The MCU integrates special me...

Page 1054: ...safety purposes 33 14 3 Debug MCU configuration register This register allows the configuration of the MCU under DEBUG This concerns Low power mode support Timer and watchdog counter support bxCAN communication support Trace pin assignment This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004 It is asynchronously reset by the PORESET and not the system reset It can be written by t...

Page 1055: ...ition the MCU generate a system reset during Standby mode so that exiting from Standby is identical than fetching from reset Bit 1 DBG_STOP Debug Stop mode 0 FCLK Off HCLK Off In STOP mode the clock controller disables all clocks including HCLK and FCLK When exiting from STOP mode the clock configuration is identical to the one after RESET CPU clocked by the 8 MHz internal RC oscillator HSI Conseq...

Page 1056: ... 24 23 22 21 20 19 18 17 16 Res DBG_I2C3_SMBUS_TIMEOUT 1 Res Res Res Res DBG_CAN_STOP Res Res DBG_I2C2_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT Res Res Res Res Res rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res DBG_IWDG_STOP DBG_WWDG_STOP DBG_RTC_STOP Res Res Res Res Res DBG_TIM6_STOP Res DBG_TIM4_STOP 2 DBG_TIM3_STOP 2 DBG_TIM2_STOP rw rw rw rw rw rw rw 1 Only in STM32F302x6 8 and STM32F3...

Page 1057: ...of the RTC counter is fed even if the core is halted 1 The clock of the RTC counter is stopped when the core is halted Bits 9 5 Reserved must be kept at reset value Bit 4 DBG_TIM6_STOP TIM6 counter stopped when core is halted 0 The counter clock of TIM6 is fed even if the core is halted 1 The counter clock of TIM6 is stopped and the output is disabled when the core is halted Bit 3 Reserved must be...

Page 1058: ...d the ETM The output data stream encapsulates the trace source ID that is then captured by a trace port analyzer TPA The core embeds a simple TPIU especially designed for low cost debug consisting of a special version of the CoreSight TPIU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Re...

Page 1059: ...tion it is available in JTAG mode and in Serial Wire mode and provides better bandwidth output capabilities than asynchronous trace FORMATTER 4RACE OUT SERIALIZER 42 42 42 4 42 37 DOMAIN 42 DOMAIN XTERNAL 00 BUS 40 5 40 5 SYNCHRONOUS SYNCHRONOUS 4 4 AI Table 191 Asynchronous TRACE pin assignment TPUI pin name Trace synchronous mode STM32F302xx pin assignment Type Description TRACESWO O TRACE Async...

Page 1060: ...E_MODE 1 0 of the Debug MCU configuration Register DBGMCU_CR By default the TRACE pins are not assigned This register is mapped on the external PPB and is reset by the PORESET and not by the SYSTEM reset It can be written by the debugger under SYSTEM reset Note By default the TRACECLKIN input clock of the TPIU is tied to GND It is assigned to HCLK two clock cycles after the bit TRACE_IOEN has been...

Page 1061: ... corresponding byte was a data this bit gives bit0 of the data if the corresponding byte was an ID change this bit indicates when that ID change takes effect Note Refer to the ARM CoreSight Architecture Specification v1 0 ARM IHI 0029B for further information 33 15 4 TPUI frame synchronization packets The TPUI can generate two types of synchronization packets The Frame Synchronization packet or Fu...

Page 1062: ...which follows If the bit SYNENA of the ITM is set then the ITM synchronization packets will follow 0x80_00_00_00_00_00 formatted by the TPUI trace source ID added 33 15 6 Synchronous mode The trace data output size can be configured to 4 2 or 1 pin TRACED 3 0 The output clock is output to the debugger TRACECK Here TRACECLKIN is driven internally and is connected to HCLK only when TRACE is used Not...

Page 1063: ...race it is important to be aware that The default clock of the STM32F302xx MCUs is the internal RC oscillator Its frequency under reset is different from the one after reset release This is because the RC calibration is the default one under system reset and is updated at each system reset release Consequently the trace port analyzer TPA should not enable the trace with the TRACE_IOEN bit under sy...

Page 1064: ...c Trace Port Mode 01 Serial Wire Output manchester default value 10 Serial Wire Output NRZ 11 reserved 0xE0040304 Formatter and flush control Bit 31 9 always 0 Bit 8 TrigIn always 1 to indicate that triggers are indicated Bit 7 4 always 0 Bit 3 2 always 0 Bit 1 EnFCont In Sync Trace mode Select_Pin_Protocol register bit1 0 00 this bit is forced to 1 the formatter is automatically enabled in contin...

Page 1065: ...ault is 0x1 for a 1 bit port size Write TPIU Formatter and Flush Control Register to 0x102 default value Write the TPIU Select Pin Protocol to select the sync or async mode Example 0x2 for async NRZ mode UART like Write the DBGMCU control register to 0x20 bit IO_TRACEN to assign TRACE I Os for async mode A TPIU Sync packet is emitted at this time FF_FF_FF_7F Configure the ITM and write the ITM Sti...

Page 1066: ...ODE 1 0 TRACE_IOEN Res Res DBG_STANDBY DBG_STOP DBG_SLEEP Reset value 0 0 0 0 0 0 0xE004 2008 DBGMCU_ APB1_FZ Res DBG_I2C3_SMBUS_TIMEOUT Res Res Res Res DBG_CAN_STOP Res Res DBG_I2C2_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT Res Res Res Res Res Res Res Res DBG_IWDG_STOP DBG_WWDG_STOP DBG_RTC_STOP Res Res Res Res Res DBG_TIM6_STOP Res DBG_TIM4_STOP DBG_TIM3_STOP DBG_TIM2_STOP Reset value 0 0 0 0 0 0 0 0...

Page 1067: ...rs or other end applications for use as part of the security keys in order to increase the security of code in Flash memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal Flash memory to activate secure boot processes etc The 96 bit unique device identifier provides a reference number which is unique for any device and ...

Page 1068: ...11 10 9 8 7 6 5 4 3 2 1 0 UID 47 32 r r r r r r r r r r r r r r r r Bits 31 8 UID 63 40 LOT_NUM 23 0 Lot number ASCII encoded Bits 7 0 UID 39 32 WAF_NUM 7 0 Wafer number 8 bit unsigned number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UID 95 80 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID 79 64 r r r r r r r r r r r r r r r r Bits 31 0 UID 95 64 LOT_NUM 55 24 Lot ...

Page 1069: ...CAN_MCR 979 CAN_MSR 981 CAN_RDHxR 995 CAN_RDLxR 995 CAN_RDTxR 994 CAN_RF0R 984 CAN_RF1R 985 CAN_RIxR 993 CAN_TDHxR 992 CAN_TDLxR 992 CAN_TDTxR 991 CAN_TIxR 990 CAN_TSR 982 COMP1_CSR 413 COMP2_CSR 415 COMP4_CSR 418 COMP6_CSR 420 CRC_CR 85 CRC_DR 84 CRC_IDR 84 CRC_INIT 85 CRC_POL 86 D DAC_CR 401 DAC_DHR12L1 404 DAC_DHR12R1 403 DAC_DHR8R1 404 DAC_DOR1 404 DAC_SR 405 DAC_SWTRIGR 403 DBGMCU_APB1_FZ 105...

Page 1070: ...PAMP1_CSR 431 OPAMP2_CSR 433 P purpose 619 PWR_CR 109 PWR_CSR 110 R RCC_AHBENR 138 RCC_AHBRSTR 147 RCC_APB1ENR 141 RCC_APB1RSTR 136 RCC_APB2ENR 140 RCC_APB2RSTR 134 RCC_BDCR 144 RCC_CFGR 128 RCC_CFGR2 148 RCC_CFGR3 150 RCC_CIR 132 RCC_CR 127 RCC_CSR 145 RTC_ALRMAR 750 RTC_ALRMBR 751 RTC_ALRMBSSR 762 RTC_BKPxR 763 RTC_CALR 757 RTC_CR 742 RTC_DR 740 RTC_ISR 745 RTC_PRER 748 RTC_SHIFTR 753 RTC_SSR 75...

Page 1071: ...703 TIMx_CR1 515 596 675 700 TIMx_CR2 516 597 676 702 TIMx_DCR 542 616 689 TIMx_DIER 521 602 677 702 TIMx_DMAR 543 616 689 TIMx_EGR 525 604 679 703 TIMx_OR 544 TIMx_PSC 536 613 685 704 TIMx_RCR 537 686 TIMx_SMCR 519 599 TIMx_SR 523 603 678 703 TSC_CR 446 TSC_ICR 449 TSC_IER 448 TSC_IOASCR 451 TSC_IOCCR 452 TSC_IOGCSR 452 TSC_IOGxCR 453 TSC_IOHCR 450 TSC_IOSCR 451 TSC_ISR 450 U USART_BRR 890 USART_...

Page 1072: ...he manual Updated Table Available features related to each product Analog to digital converters Figure ADC block diagram Figure ADC block diagram Figure VBAT channel block diagram Section ADC configuration register ADCx_CFGR x 1 2 Section ADC Analog Watchdog 2 Configuration Register ADCx_AWD2CR x 1 2 Section ADC Analog Watchdog 3 Configuration Register ADCx_AWD3CR x 1 2 Section ADC Differential Mo...

Page 1073: ...cription Table Flash module organization Option byte description Table Option byte organization Table Description of the option bytes Flexible memory controller FMC New chapter Power control PWR Section Independent A D and D A converter supply and reference voltage Reset and clock control RCC Section Clocks Section RCC registers General purpose I Os GPIO Section GPIO main features Section GPIO reg...

Page 1074: ... IC sound SPI I2S Section SPI implementation Universal synchronous asynchronous receiver transmitter USART Section USB implementation Debug support DBG Section Debug MCU APB1 freeze register DBGMCU_APB1_FZ 22 Sep 2015 5 System and memory overview Updated Figure 3 STM32F302xD E system architecture Flexible static memory controller FSMC Renamed FMC as FSMC in the section title and introduction Digit...

Page 1075: ... Advanced control timers TIM1 Updated RCC section Updated Figure 14 STM32F302x6 8 clock tree replacing USARTx x 1 2 3 by USART1 Updated Figure 13 STM32F302xD E clock tree adding x2 factor going to TIM2 3 4 when PLLCLK is timer clock source Updated Section 9 4 2 Clock configuration register RCC_CFGR renaming USBPRES by USBPRE and adding bit22 USBPRE description Updated Section 9 4 9 RTC domain cont...

Page 1076: ...e about the TSC control register configuration forbidden Updated Section 19 6 1 TSC control register TSC_CR adding note for CTPL 3 0 bits and PGPSC 2 0 bits Updated USART section Updated Section Table 152 STM32F302xx USART features replacing USART4 5 by UART4 5 Updated Section 29 5 17 Wakeup from Stop mode using USART adding paragraph determining the maximum USART baudrate Updated whole USART docu...

Page 1077: ...4 adding new paragraph Updated Section SRAM NOR Flash write timing registers 1 4 FMC_BWTR1 4 adding new paragraph Updated Figure 49 NAND Flash PC Card controller waveforms for common memory access replacing MEMxHIZ by MEMxHIZ 1 and adding note 2 Updated Section 14 6 5 NAND Flash prewait functionality Updated Common memory space timing register 2 4 FMC_PMEM2 4 MEMHOLD 7 0 description Updated Attrib...

Page 1078: ...ling trigger selection register EXTI_FTSR2 Section 13 3 11 Software interrupt event register EXTI_SWIER2 and Section 13 3 12 Pending register EXTI_PR2 bit 0 reserved Updated DMA section updated Table 34 Programmable data width endian behavior when bits PINC MINC 1 Updated I2C2 section Updated Figure 286 Setup and hold timings Updated Section 28 4 4 I2C initialization updating and adding notes in S...

Page 1079: ...0 and COMP2INMSEL 2 0 bit description Updated Section 17 5 3 COMP4 control and status register COMP4_CSR COMP4OUTSEL 3 0 and COMP4INMSEL 2 0 bit description Updated Section 17 5 4 COMP6 control and status register COMP6_CSR COMP6OUTSEL 3 0 COMP6INMSEL 2 0 and COMP6MODE 3 2 bit description Added note depending on the product when a timer is not available the corresponding combination is reserved in...

Page 1080: ...Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such prod...

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