DocID025202 Rev 7
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RM0365
Analog-to-digital converters (ADC)
392
15.5.19 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR,
x=1
..
2)
Address offset: 0xA4
Reset value: 0x0000 0000
15.5.20 ADC Differential Mode Selection Register (ADCx_DIFSEL, x=1
..
2)
Address offset: 0xB0
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AWD3CH[18:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AWD3CH[15:1]
Res.
rw
rw
rw
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rw
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rw
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rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:1
AWD3CH[18:1]
: Analog watchdog 3 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 3.
AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3
AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3
When AWD3CH[18:1] = 000..0, the analog Watchdog 3 is disabled
Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers.
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 0 Reserved, must be kept at reset value.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DIFSEL[18:16]
r
r
r
15
14
13
12
11
10
9
8
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5
4
3
2
1
0
DIFSEL[15:1]
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
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rw