DocID025202 Rev 7
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RM0365
Reset and clock control (RCC)
154
9.4.13 Clock
configuration register 3 (RCC_CFGR3)
Address: 0x30
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res
Res
Res
Res
Res
Res
TIM34
SW
(1)
TIM2
UART5SW[1:0]
UART4SW[1:0] USART3SW[1:0]
USART2SW[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res
Res
TIM17
SW
Res
TIM16
SW
TIM15
SW
Res
TIM1
SW
Res
I2C3
SW
I2C2
SW
I2C1
SW
Res
Res
USART1SW[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
1. Only on STM32F302xDxE.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25
TIM34SW
: Timer34 clock source selection
Set and reset by software to select TIM34 clock source.
The bit is writable only when the following conditions occur: system clock source is the PLL
and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
Note: STM32F30
2
xDxE only.
Bit 24
TIM2SW
: Timer2 clock source selection
Set and reset by software to select TIM2 clock source.
The bit is writable only when the following conditions occur: clock system = PLL, and AHB or
APB2 subsystem clocks are not divided by more than 2 cumulatively.
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
Note: STM32F30
2
xDxE only.
Bits 23:22
UART5SW[1:0]:
UART5 clock source selection (STM32F302xB/C devices only)
This bit is set and cleared by software to select the UART5 clock source.
00: PCLK selected as UART5 clock source (default)
01: System clock (SYSCLK) selected as UART5 clock
10: LSE clock selected as UART5 clock
11: HSI clock selected as UART5 clock
Bits 21:20
UART4SW[1:0]:
UART4 clock source selection (STM32F302xB/C devices only)
This bit is set and cleared by software to select the UART4 clock source.
00: PCLK selected as UART4 clock source (default)
01: System clock (SYSCLK) selected as UART4 clock
10: LSE clock selected as UART4 clock
11: HSI clock selected as UART4 clock