Reset and clock control (RCC)
RM0365
117/1080
DocID025202 Rev 7
Figure 13. STM32F302xD/E clock tree
1. For full details about the internal and external clock source characteristics, please refer to the Electrical
characteristics section in your device datasheet.
2. TIM1 can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB
069
,I$3%SUHVFDOHU
[HOVH[
$ + %
/6(
6:
6<6&/.
)/,7)&/.
WR)ODVKSURJUDPPLQJLQWHUIDFH
WR,&[[
,665&
6<6&/.
([WFORFN
WR,6[[
86%
SUHVFDOHU
86%&/.WR86%LQWHUIDFH
+&/.
WR$+%EXVFRUHPHPRU\DQG
'0$
WR&RUWH[V\VWHPWLPHU
)+&/.&RUWH[IUHHUXQQLQJFORFN
3/&/.
+6,
/6(
WR7,0
WR86$57[[
WR7,0
WR$3%SHULSKHUDOV
3&/.
WR86$57
7,0
WR$'&[\
[\
/6,5&
N+]
0+]
+6(26&
57&&/.
WR57&
$3%
SUHVFDOHU
0+]
+6,5&
+6(
+6,
3//&/.
3//
[[
«[
3//65&
3//08/
35(',9
WR)0&
+6,
6<6&/.
WR$3%SHULSKHUDOV
3&/.
,I$3%SUHVFDOHU
[HOVH[
3&/.
6<6&/.
+6,
/6(
$3%
SUHVFDOHU
$+%
SUHVFDOHU
$'&
SUHVFDOHU
$'&SUHVFDOHU
[
6<6&/.
0&2
/6,
+6(
+6,
3//&/.
,:'*&/.
WR,:'*
/6,
57&6(/>@
0&2SUHVFDOHU
0&2
/6(26&
N+]
&66
+6,
,6B&.,1
26&B287
26&B,1
26&B,1
26&B287
[