DocID025202 Rev 7
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RM0365
Inter-integrated circuit (I2C) interface
834
•
When the SCL falling edge is internally detected, a delay is inserted before sending
SDA output. This delay is
t
SDADEL
= SDADEL x t
PRESC
+ t
I2CCLK
where
t
PRESC
= (PRESC+1)
x t
I2CCLK
.
T
SDADEL
impacts the hold time
t
HD;DAT.
The total SDA output delay is:
t
SYNC1
+ {[SDADEL x (PRESC+1) + 1] x t
I2CCLK
}
t
SYNC1
duration depends on these parameters:
–
SCL falling slope
–
When enabled, input delay brought by the analog filter: t
AF(min)
< t
AF
< t
AF(max)
ns.
–
When enabled, input delay brought by the digital filter: t
DNF
= DNF
x
t
I2CCLK
–
Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods)
In order to bridge the undefined region of the SCL falling edge, the user must program
SDADEL in such a way that:
{t
f (max)
+t
HD;DAT (min)
-t
AF(min)
- [(
DNF
+3) x t
I2CCLK
]} / {(PRESC +1) x t
I2CCLK
}
≤
SDADEL
SDADEL
≤
{t
HD;DAT (max)
-t
AF(max)
- [(
DNF+4) x t
I2CCLK
]} / {(PRESC +1) x t
I2CCLK
}
Note:
t
AF(min)
/
t
AF(max)
are part of the equation only when the analog filter is enabled. Refer to
device datasheet for t
AF
values.
The maximum t
HD;DAT
could be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode
and Fast-mode Plus, but must be less than the maximum of t
VD;DAT
by a transition time.
This maximum must only be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before
it releases the clock.
The SDA rising edge is usually the worst case, so in this case the previous equation
becomes:
SDADEL
≤
{t
VD;DAT (max)
-t
r (max)
-
260 ns
- [(
DNF+4) x t
I2CCLK
]} / {(PRESC +1) x t
I2CCLK
}.
Note:
This condition can be violated when NOSTRETCH=0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Table 138: I2C-SMBUS specification data setup and hold times
for t
f
, t
r
, t
HD;DAT
and
t
VD;DAT
standard values.
•
After t
SDADEL
delay, or after sending SDA output in case the slave had to stretch the
clock because the data was not yet written in I2C_TXDR register, SCL line is kept at
low level during the setup time. This setup time is
t
SCLDEL
= (1) x t
PRESC
where
t
PRESC
= (PRESC+1) x t
I2CCLK.
t
SCLDEL
impacts the setup time
t
SU;DAT .
In order to bridge the undefined region of the SDA transition (rising edge usually worst
case), the user must program SCLDEL in such a way that:
{[t
r (max)
+ t
SU;DAT (min)
] / [
(PRESC+1)] x t
I2CCLK
]} - 1 <=
SCLDEL
Table 138: I2C-SMBUS specification data setup and hold times
for t
r
and
t
SU;DAT
standard values.
The SDA and SCL transition time values to be used are the ones in the application. Using
the maximum values from the standard increases the constraints for the SDADEL and
SCLDEL calculation, but ensures the feature whatever the application.
