Renesas SH7124 R5F7124, Hardware Manual

Page: 81 / 782

Section 4 Clock Pulse Generator (CPG)
Rev. 3.00 Sep. 27, 2007 Page 61 of 758
REJ09B0243-0300
4.4 Register Descriptions
The CPG has the following registers.
For details on the addresses of these registers and the states of these registers in each processing
state, see section 20, List of Registers
Table 4.5 Register Configuration
Register Name
Abbrevia-
tion
R/W Initial Value Address Access Size
Frequency control register FRQCR R/W H'36DB H'FFFFE800 16
Oscillation stop detection
control register OSCCR R/W H'00 H'FFFFE814 8
4.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the
internal clock (I
φ
), bus clock (B
φ
), peripheral clock (P
φ
), and MTU2 clock (MP
φ
). FRQCR can be
accessed only in words.
FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT
overflow).
Before making changes to FRQCR, stop clock supply to each module except the CPU, on-chip
ROM, and on-chip-RAM.
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
- - - - IFC[2:0] BFC[2:0] PFC[2:0] MPFC[2:0]