Renesas SH7124 R5F7124, Hardware Manual

Page: 427 / 782

Section 11 Watchdog Timer (WDT)
Rev. 3.00 Sep. 27, 2007 Page 407 of 758
REJ09B0243-0300
11.3.3 Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR:
These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 11.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
15 8 7 0
H'5A Write data
Address: H'FFFFE810
WTCNT write
15 8 7 0
H'A5 Write data
Address: H'FFFFE812
WTCSR write
Figure 11.2 Writing to WTCNT and WTCSR