Renesas SH7124 R5F7124, Hardware Manual

Page: 757 / 782

Rev. 3.00 Sep. 27, 2007 Page 737 of 758
REJ09B0243-0300
Main Revisions and Additions in this Edition
Item Page Revision (See Manual for Details)
– – Added
VQFN-64 and VQFN-52 specifications
Descriptions of on-chip 32-kbyte flash memory for
SH7124
Deleted
Items Specification
Multi-function
timer pulse unit 2
(MTU2)
•
Pulse output modes
One shot, toggle, PWM,
complementary PWM, and
reset-synchronized PWM
modes
Table 1.1 Features 4
Amended
Instruction T Bit
SUBV Rm,Rn Underflow
Table 2.12 Arithmetic Operation
Instructions 40
4.1 Features 55 Deleted
•
Five clocks generated independently
An internal clock (If) for the CPU and cache; a
peripheral clock (Pf) for the on-chip peripheral modules;
a bus clock (Bf = CK) for the external bus interface; and
a MTU2 clock (MPf) for the on-chip MTU2 module.
Table 4.4 Frequency Division
Ratios Specifiable with FRQCR 60 Deleted
Notes: 2. The output frequency of the PLL circuit is the
product of the frequency of the input from the
crystal resonator or EXTAL pin and the
multiplication ratio (
×
8) of the PLL circuit. This
output frequency must be 50 MHz or lower.