Renesas SH7124 R5F7124 Hardware Manual Download Page 298

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Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 3.00 Sep. 27, 2007 Page 278 of 758

REJ09B0243-0300

TGRA_3=TCDR+1

TCDR

TGRA_4

TGRC_4

TDDR=1

H'0000

Buffer register TGRC_4

Temporary register TEMP2

Compare register TGRA_4

Output waveform

TCNT_3

TCNT_4

TCNTS

Output waveform is active-low.

Data1

Data2

Data1

Data2

Data1

Data2

Transfer from temporary register
to compare register

Initial output

Figure 9.41 Example of Operation without Dead Time

Summary of Contents for SH7124 R5F7124

Page 1: ...ine Family SH7125 R5F7125 SH7124 R5F7124 Rev 3 00 REJ09B0243 0300 SH7125 Group SH7124 Group The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revisions and additions Details should always be checked by referring to the relevant text ...

Page 2: ...Rev 3 00 Sep 27 2007 Page ii of xx ...

Page 3: ...ty and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth ab...

Page 4: ...ialization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of ...

Page 5: ... items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage notes are given as required as the final part of each section 7 List of Registers 8 Electrical Characteristics 9 Appendix 10 Main Revisions and Addition...

Page 6: ...ly categorized into parts on the CPU system control functions peripheral functions and electrical characteristics In order to understand the details of the CPU s functions Read the SH 1 SH 2 SH DSP Software Manual In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register The addre...

Page 7: ... TM RISC engine C C Compiler Assembler Optimizing Linkage Editor Compiler Package V 9 00 User s Manual REJ10B0152 SuperH TM RISC engine High performance Embedded Workshop 3 User s Manual REJ10B0025 SuperH RISC engine High Performance Embedded Workshop 3 Tutorial REJ10B0023 Application note Document Title Document No SuperH RISC engine C C Compiler Package Application Note REJ05B0463 All trademarks...

Page 8: ...Rev 3 00 Sep 27 2007 Page viii of xx ...

Page 9: ... Memory Data Formats 22 2 3 3 Immediate Data Formats 23 2 4 Features of Instructions 23 2 4 1 RISC Type 23 2 4 2 Addressing Modes 26 2 4 3 Instruction Formats 29 2 5 Instruction Set 33 2 5 1 Instruction Set by Type 33 2 5 2 Data Transfer Instructions 37 2 5 3 Arithmetic Operation Instructions 39 2 5 4 Logic Operation Instructions 41 2 5 5 Shift Instructions 42 2 5 6 Branch Instructions 43 2 5 7 Sy...

Page 10: ... Stop 68 4 8 Usage Notes 69 4 8 1 Note on Crystal Resonator 69 4 8 2 Notes on Board Design 69 Section 5 Exception Handling 71 5 1 Overview 71 5 1 1 Types of Exception Handling and Priority 71 5 1 2 Exception Handling Operations 72 5 1 3 Exception Handling Vector Table 73 5 2 Resets 75 5 2 1 Types of Resets 75 5 2 2 Power On Reset 75 5 2 3 Manual Reset 76 5 3 Address Errors 77 5 3 1 Address Error S...

Page 11: ...errupt Priority Registers A to F and H to M IPRA to IPRF and IPRH to IPRM 99 6 4 Interrupt Sources 102 6 4 1 External Interrupts 102 6 4 2 On Chip Peripheral Module Interrupts 103 6 4 3 User Break Interrupt 103 6 5 Interrupt Exception Handling Vector Table 104 6 6 Interrupt Operation 107 6 6 1 Interrupt Sequence 107 6 6 2 Stack after Interrupt Exception Handling 110 6 7 Interrupt Response Time 110...

Page 12: ... chip FLASH and on chip RAM 147 8 4 Access to on chip Peripheral I O Register 148 Section 9 Multi Function Timer Pulse Unit 2 MTU2 151 9 1 Features 151 9 2 Input Output Pins 157 9 3 Register Descriptions 158 9 3 1 Timer Control Register TCR 162 9 3 2 Timer Mode Register TMDR 166 9 3 3 Timer I O Control Register TIOR 169 9 3 4 Timer Compare Match Clear Register TCNTCMPCLR 188 9 3 5 Timer Interrupt ...

Page 13: ...er TITCR 229 9 3 28 Timer Interrupt Skipping Counter TITCNT 231 9 3 29 Timer Buffer Transfer Set Register TBTER 232 9 3 30 Timer Dead Time Enable Register TDER 234 9 3 31 Timer Waveform Control Register TWCR 235 9 3 32 Bus Master Interface 236 9 4 Operation 237 9 4 1 Basic Functions 237 9 4 2 Synchronous Operation 243 9 4 3 Buffer Operation 245 9 4 4 Cascaded Operation 249 9 4 5 PWM Modes 254 9 4 ...

Page 14: ...s in Reset Synchronous PWM Mode 344 9 7 17 Contention between Overflow Underflow and Counter Clearing 345 9 7 18 Contention between TCNT Write and Overflow Underflow 346 9 7 19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset Synchronized PWM Mode 346 9 7 20 Output Level in Complementary PWM Mode and Reset Synchronized PWM Mode 347 9 7 21 Interrupts in Module Standby Mode 347 9 ...

Page 15: ...08 11 4 1 Canceling Software Standbys 408 11 4 2 Using Watchdog Timer Mode 408 11 4 3 Using Interval Timer Mode 409 11 5 Usage Note 410 Section 12 Serial Communication Interface SCI 411 12 1 Features 411 12 2 Input Output Pins 413 12 3 Register Descriptions 414 12 3 1 Receive Shift Register SCRSR 415 12 3 2 Receive Data Register SCRDR 415 12 3 3 Transmit Shift Register SCTSR 415 12 3 4 Transmit Da...

Page 16: ...s 477 13 3 Register Descriptions 478 13 3 1 A D Data Registers 0 to 7 ADDR0 to ADDR7 479 13 3 2 A D Control Status Registers_0 and _1 ADCSR_0 and ADCSR_1 479 13 3 3 A D Control Registers_0 and _1 ADCR_0 and ADCR_1 482 13 3 4 A D Trigger Select Register_0 ADTSR_0 484 13 4 Operation 488 13 4 1 Single Mode 488 13 4 2 Continuous Scan Mode 488 13 4 3 Single Cycle Scan Mode 489 13 4 4 Input Sampling and...

Page 17: ...tween Word Write and Count Up Processes of CMCNT 509 14 5 4 Conflict between Byte Write and Count Up Processes of CMCNT 510 14 5 5 Compare Match between CMCNT and CMCOR 510 Section 15 Pin Function Controller PFC 511 15 1 Register Descriptions 519 15 1 1 Port A I O Register L PAIORL 520 15 1 2 Port A Control Registers L1 to L4 PACRL1 to PACRL4 520 15 1 3 Port B I O Registers L and H PBIORL and PBIO...

Page 18: ...9 17 3 Input Output Pins 581 17 4 Register Descriptions 581 17 4 1 Registers 581 17 4 2 Programming Erasing Interface Registers 584 17 4 3 Programming Erasing Interface Parameters 590 17 5 On Board Programming Mode 605 17 5 1 Boot Mode 605 17 5 2 User Program Mode Only in On Chip 128 Kbyte and 64 Kbyte ROM Version 609 17 6 Protection 618 17 6 1 Hardware Protection 618 17 6 2 Software Protection 61...

Page 19: ...Control Register RAMCR 668 19 4 Sleep Mode 669 19 4 1 Transition to Sleep Mode 669 19 4 2 Canceling Sleep Mode 669 19 5 Software Standby Mode 670 19 5 1 Transition to Software Standby Mode 670 19 5 2 Canceling Software Standby Mode 671 19 6 Module Standby Mode 672 19 6 1 Transition to Module Standby Mode 672 19 6 2 Canceling Module Standby Function 672 19 7 Usage Note 672 19 7 1 Current Consumptio...

Page 20: ...tion Interface SCI Timing 719 21 3 7 Port Output Enable POE Timing 721 21 3 8 A D Converter Timing 722 21 3 9 Conditions for Testing AC Characteristics 723 21 4 A D Converter Characteristics 724 21 5 Flash Memory Characteristics 725 21 6 Usage Note 726 21 6 1 Notes on Connecting VCL Capacitor 726 Appendix 727 A Pin States 727 B Product Code Lineup 731 C Package Dimensions 732 Main Revisions and Ad...

Page 21: ...w cost high performance and high functioning systems even for applications that were previously impossible with microcomputers such as real time control which demands high speeds In addition this LSI includes on chip peripheral functions necessary for system configuration such as a ROM a RAM timers a serial communication interface SCI an A D converter an interrupt controller INTC and I O ports The...

Page 22: ... language oriented 62 basic instructions Note Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH 2 For details see section 5 8 4 Notes on Slot Illegal Instruction Exception Handling Operating modes Operating modes Single chip mode Operating states Program execution state Exception handling state Power down modes Sleep mode Softwa...

Page 23: ...et for each module Vector addresses A vector address for each interrupt source User debugging interface H UDI E10A emulator support Clock pulse generator CPG Clock mode Input clock can be selected from external input or crystal resonator Four types of clocks generated CPU clock Maximum 50 MHz Bus clock Maximum 40 MHz Peripheral clock Maximum 40 MHz MTU2 clock Maximum 40 MHz Watchdog timer WDT On c...

Page 24: ... modes Synchronization of multiple counters Complementary PWM output mode Non overlapping waveforms output for 6 phase inverter control Automatic dead time setting 0 to 100 PWM duty cycle specifiable Output suppression A D conversion delaying function Dead time compensation Interrupt skipping at crest or trough Reset synchronized PWM mode Three phase PWM waveforms in positive and negative phases c...

Page 25: ...nels can be sampled simultaneously I O ports 37 general input output pins and eight general input pins SH7125 23 general input output pins and eight general input pins SH7124 Input or output can be selected for each bit Packages QFP 64 0 8 pitch SH7125 LQFP 64 0 5 pitch SH7125 LQFP 48 0 65 pitch SH7124 VQFN 64 0 4 pitch SH7125 and SH7124 VQFN 52 0 4 pitch SH7124 Power supply voltage Vcc 4 0 to 5 5...

Page 26: ...ntroller CPG Clock pulse generator WDT Watchdog timer CPU Central processing unit PFC Pin function controller MTU2 Multi function timer pulse unit 2 POE Port output enable SCI Serial communication interface CMT Compare match timer ADC A D converter I O port PFC Power down mode control Peripheral bus Pφ I bus Bφ L bus Iφ Peripheral bus controller SH2 CPU UBC INTC WDT CPG H UDI MTU2 POE SCI CMT ADC ...

Page 27: ... 60 59 58 57 56 55 54 53 52 51 PA3 IRQ1 RXD1 TRST PA4 IRQ2 TXD1 TMS PA5 IRQ3 SCK1 PA6 TCLKA PA7 TCLKB SCK2 TCK PA8 TCLKC RXD2 TDI PA9 TCLKD TXD2 TDO POE8 PA10 RXD0 VSS PA11 TXD0 ADTRG VCC PA12 SCK0 PA13 SCK1 PA14 RXD1 PA15 TXD1 PE0 TIOC0A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PE13 TIOC4B MRES PE12 TIOC4A PE11 TIOC3D V CC PE9 TIOC3B V SS PE10 TIOC3C V CL PE8 TIOC3A PE7 T...

Page 28: ...A1 POE1 TXD0 V CC PA2 IRQ0 SCK0 V SS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA3 IRQ1 RXD1 TRST PA4 IRQ2 TXD1 TMS PA5 IRQ3 SCK1 PA6 TCLKA PA7 TCLKB SCK2 TCK PA8 TCLKC RXD2 TDI PA9 TCLKD TXD2 TDO POE8 PA10 RXD0 VSS PA11 TXD0 ADTRG VCC PA12 SCK0 PA13 SCK1 PA14 RXD1 PA15 TXD1 PE0 TIOC0A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PE13 TIOC4B MRES PE12 TIOC4A PE11 TIOC3D V CC P...

Page 29: ... PA1 POE1 TXD0 PA3 IRQ1 RXD1 TRST PA4 IRQ2 TXD1 TMS PA6 TCLKA PA7 TCLKB SCK2 TCK VSS PA8 TCLKC RXD2 TDI VCC PA9 TCLKD TXD2 TDO POE8 PE0 TIOC0A PE1 TIOC0B RXD0 PE2 TIOC0C TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PE15 TIOC4D IRQOUT PE14 TIOC4C PE13 TIOC4B MRES V CC PE12 TIOC4A V SS PE11 TIOC3D V CL PE9 TIOC3B PE10 TIOC3C PE8 TIOC3A PE3 TIOC0D SCK0 LQFP 48 Top view Pins ...

Page 30: ...AL WDTOVF RES PA0 POE0 TXD0 V CL 52 51 50 49 48 47 46 45 44 43 42 41 40 PA1 POE1 TXD0 PA3 IRQ1 RXD1 TRST PA4 IRQ2 TXD1 TMS PA6 TCLKA PA7 TCLKB SCK2 TCK VSS VSS PA8 TCLKC RXD2 TDI VCC PA9 TCLKD TXD2 TDO POE8 PE0 TIOC0A PE1 TIOC0B RXD0 PE2 TIOC0C TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PE15 TIOC4D IRQOUT PE14 TIOC4C PE13 TIOC4B MRES V CC PE12 TIOC4A V SS PE11 TIOC3D V CL PE9 TI...

Page 31: ...ower supply for internal power down External capacitance pins for internal power down power supply Connect these pins to Vss via a 0 1 to 0 47 µF capacitor placed close to the pins PLLVss I PLL ground Ground pin for the on chip PLL oscillator EXTAL I External clock Connected to a crystal resonator An external clock signal may also be input to the EXTAL pin Clock XTAL O Crystal Connected to a cryst...

Page 32: ...ns Selectable as level input or edge input The rising edge falling edge and both edges are selectable as edges IRQOUT O Interrupt request output Shows that an interrupt cause has occurred The interrupt cause can be recognized even in the bus release state TCLKA TCLKB TCLKC TCLKD I MTU2 timer clock input External clock input pins for the timer TIOC0A TIOC0B TIOC0C TIOC0D I O MTU2 input capture outp...

Page 33: ...output enable Request signal input to place the waveform output pins and channel 0 pins of MTU2 in high impedance state In the SH7125 while POE3 function is selected in the PFC the pin is pulled up inside this LSI if no signals are input to them TXD2 to TXD0 O Transmit data Transmit data output pins RXD2 to RXD0 I Receive data Receive data input pins Serial communication interface SCI SCK2 to SCK0...

Page 34: ...ut output port pins PB16 PB5 PB3 to PB1 SH7125 I O General port 5 bit input output port pins PB5 PB3 PB1 SH7124 3 bit input output port pins PE15 to PE0 SH7125 I O General port 16 bit input output port pins PE15 to PE8 PE3 to PE0 SH7124 12 bit input output port pins I O ports PF7 to PF0 I General port 8 bit input port pins TCK I Test clock Test clock input pin TMS I Test mode select Inputs the tes...

Page 35: ...this LSI enters the normal mode The emulator functions are available in ASE mode When no signal is input this pin is pulled up inside this LSI ASEBRK I Break request E10A emulator break input pin E10A interface ASEBRKAK O Break mode acknowledge Indicates that the E10A emulator has entered its break mode Note The WDTOVF pin should not be pulled down When absolutely necessary pull it down through a ...

Page 36: ...Section 1 Overview Rev 3 00 Sep 27 2007 Page 16 of 758 REJ09B0243 0300 ...

Page 37: ...ions 62 Addressing modes 11 Register direct Rn Register indirect Rn Post increment register indirect Rn Pre decrement register indirect Rn Register indirect with displacement disp 4 Rn Index register indirect R0 Rn GBR indirect with displacement disp 8 GBR Index GBR indirect R0 GBR PC relative with displacement disp 8 PC PC relative disp 8 disp 12 Rn Immediate imm 8 ...

Page 38: ...31 M GBR 31 VBR Q I3 I2 I1 I0 S T 31 0 MACH 31 0 PR 31 0 PC MACL Notes 1 R0 can be used as an index register in index register indirect or index GBR indirect addressing mode For some instructions only R0 is used as the source or destination register 2 R15 is used as a hardware stack pointer during exception handling General register Rn Status register SR Global base register GBR Vector base regist...

Page 39: ... GBR is used as a base address in GBR indirect addressing mode for data transfer of on chip peripheral module registers VBR is used as a base address of the exception handling including interrupts vector table Status register SR Bit Initial value R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R...

Page 40: ... BF S SETT CLRT Indicates carry borrow overflow or underflow in the following instructions ADDV ADDC SUBV SUBC NEGC DIV0U DIV0S DIV1 SHAR SHAL SHLR SHLL ROTR ROTL ROTCR ROTCL Global base register GBR This register indicates a base address in GBR indirect addressing mode The GBR indirect addressing mode is used for data transfer of the on chip peripheral module registers and logic operations Vector...

Page 41: ...destination address from subroutine procedures Program counter PC The PC indicates the point which is four bytes two instructions after the current execution instruction 2 2 4 Initial Values of Registers Table 2 1 lists the initial values of registers after a reset Table 2 1 Initial Values of Registers Type of register Register Default General register R0 to R14 Undefined R15 SP SP value set in th...

Page 42: ...can be accessed from any address Locate however word data at an address 2n longword data at 4n Otherwise an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n In such cases the data accessed cannot be guaranteed The hardware stack area pointed by the hardware stack pointer SP R15 uses onl...

Page 43: ...t 2 4 Features of Instructions 2 4 1 RISC Type The instructions are RISC type instructions with the following features Fixed 16 Bit Length All instructions have a fixed length of 16 bits This improves program code efficiency One Instruction per Cycle Since pipelining is used basic instructions can be executed in one cycle Data Size The basic data size for operations is longword Byte word or longwo...

Page 44: ...operation is executed in one to two cycles and a 16 16 64 64 multiply and accumulate operation in two to three cycles A 32 32 64 multiply operation and a 32 32 64 64 multiply and accumulate operation are each executed in two to four cycles T Bit The result of a comparison is indicated by the T bit in SR and a conditional branch is performed according to whether the result is True or False Processi...

Page 45: ...to a register using the method whereby immediate data is loaded when an instruction is executed and the data is accessed using the register indirect addressing mode Table 2 6 Access to Absolute Address Type CPU in this LSI Example of Other CPUs Absolute address MOV L disp PC R1 MOV B R1 R0 DATA L H 12345678 MOV B H 12345678 R0 Note Immediate data is referenced by disp PC 16 Bit 32 Bit Displacement...

Page 46: ...ffective address is register Rn Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand Rn Rn 1 2 4 Rn 1 2 4 Rn After instruction execution Byte Rn ...

Page 47: ...o extended Rn disp 1 2 4 Rn Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Index register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 GBR indirect with displacement disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to the operand ...

Page 48: ... the operand size With a longword operand the lower 2 bits of PC are masked PC PC disp 2 or PC H FFFFFFFC disp 4 H FFFFFFFC 2 4 disp zero extended With longword operand Word PC disp 2 Longword PC H FFFFFFFC disp 4 PC relative disp 8 Effective address is PC with 8 bit displacement disp added after being sign extended and multiplied by 2 PC 2 disp sign extended PC disp 2 PC disp 2 disp 12 Effective ...

Page 49: ...tended imm 8 8 bit immediate data imm of MOV ADD or CMP EQ instruction is sign extended imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 2 4 3 Instruction Formats This section describes the instruction formats and the meaning of the source and destination operands The meaning of the operands depends on the instruction code The following symbols are used in t...

Page 50: ...Rn Control register or system register nnnn register direct STS MACH Rn n type xxxx nnnn xxxx xxxx 15 0 Control register or system register nnnn pre decrement register indirect STC L SR Rn mmmm register direct Control register or system register LDC Rm SR mmmm post increment register indirect Control register or system register LDC L Rm SR mmmm register indirect JMP Rm m type xxxx mmmm xxxx xxxx 1...

Page 51: ...er indirect nnnn register direct MOV L Rm Rn mmmm register direct nnnn pre decrement register indirect MOV L Rm Rn nm type xxxx nnnn mmmm xxxx 15 0 mmmm register direct nnnn index register indirect MOV L Rm R0 Rn md type xxxx xxxx mmmm dddd 15 0 mmmmdddd register indirect with displacement R0 register direct MOV B disp Rm R0 nd4 type xxxx xxxx nnnn dddd 15 0 R0 register direct nnnndddd register in...

Page 52: ...pe xxxx xxxx dddd dddd 15 0 dddddddd PC relative BF label d12 type xxxx dddd dddd dddd 15 0 dddddddddddd PC relative BRA label label disp PC nd8 type xxxx nnnn dddd dddd 15 0 dddddddd PC relative with displacement nnnn register direct MOV L disp PC Rn iiiiiiii immediate Index GBR indirect AND B imm R0 GBR iiiiiiii immediate R0 register direct AND imm R0 i type xxxx xxxx iiii iiii 15 0 iiiiiiii imm...

Page 53: ... transfer SWAP Upper lower swap Data transfer instructions 5 XTRCT Extraction of middle of linked registers 39 ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow CMP cond Comparison DIV1 Division DIV0S Signed division initialization DIV0U Unsigned division initialization DMULS Signed double precision multiplication DMULU Unsigned double precision multiplication ...

Page 54: ... Binary subtraction with underflow 33 AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST T bit setting for logical AND Logic operation instructions 6 XOR Exclusive logical OR 14 ROTL 1 bit left shift ROTR 1 bit right shift ROTCL 1 bit left shift with T bit ROTCR 1 bit right shift with T bit SHAL Arithmetic 1 bit left shift SHAR Arithmetic 1 bit right shift SHLL Log...

Page 55: ...rocedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure Branch instructions 9 RTS Return from subroutine procedure 11 CLRT T bit clear CLRMAC MAC register clear LDC Load into control register LDS Load into system register NOP No operation RTE Return from exception handling SETT T bit setting SLEEP Transition to power down mode STC Store from control...

Page 56: ...es summary of operation Explanation of Symbols Transfer direction xx Memory operand M Q T Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit n n bit left shift n n bit right shift Value when no wait cycles are inserted 1 Value of T bit after instruction is executed Explanation of Symbols No change Notes 1 The table shows the mini...

Page 57: ...Rn 0110nnnnmmmm0000 1 MOV W Rm Rn Rm Sign extension Rn 0110nnnnmmmm0001 1 MOV L Rm Rn Rm Rn 0110nnnnmmmm0010 1 MOV B Rm Rn Rn 1 Rn Rm Rn 0010nnnnmmmm0100 1 MOV W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 1 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 1 MOV B Rm Rn Rm Sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 1 MOV W Rm Rn Rm Sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 1 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnn...

Page 58: ...110 1 MOV B R0 disp GBR R0 disp GBR 11000000dddddddd 1 MOV W R0 disp GBR R0 disp 2 GBR 11000001dddddddd 1 MOV L R0 disp GBR R0 disp 4 GBR 11000010dddddddd 1 MOV B disp GBR R0 disp GBR Sign extension R0 11000100dddddddd 1 MOV W disp GBR R0 disp 2 GBR Sign extension R0 11000101dddddddd 1 MOV L disp GBR R0 disp 4 GBR R0 11000110dddddddd 1 MOVA disp PC R0 disp 4 PC R0 11000111dddddddd 1 MOVT Rn T Rn 0...

Page 59: ...0011nnnnmmmm0010 1 Comparison result CMP GE Rm Rn If Rn Rm with signed data 1 T 0011nnnnmmmm0011 1 Comparison result CMP HI Rm Rn If Rn Rm with unsigned data 1 T 0011nnnnmmmm0110 1 Comparison result CMP GT Rm Rn If Rn Rm with signed data 1 T 0011nnnnmmmm0111 1 Comparison result CMP PZ Rn If Rn 0 1 T 0100nnnn00010001 1 Comparison result CMP PL Rn If Rn 0 1 T 0100nnnn00010101 1 Comparison result CMP...

Page 60: ...nnmmmm1101 1 MAC L Rm Rn Signed operation of Rn Rm MAC MAC 32 32 64 64 bits 0000nnnnmmmm1111 2 to 5 MAC W Rm Rn Signed operation of Rn Rm MAC MAC 16 16 64 64 bits 0100nnnnmmmm1111 2 to 4 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 0000nnnnmmmm0111 2 to 5 MULS W Rm Rn Signed operation of Rn Rm MAC 16 16 32 bits 0010nnnnmmmm1111 1 to 3 MULU W Rm Rn Unsigned operation of Rn Rm MAC 16 16 32 bits 0010nnnnmmmm...

Page 61: ...1 1 OR Rm Rn Rn Rm Rn 0010nnnnmmmm1011 1 OR imm R0 R0 imm R0 11001011iiiiiiii 1 OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii 3 TAS B Rn If Rn is 0 1 T 1 MSB of Rn 0100nnnn00011011 4 Test result TST Rm Rn Rn Rm if the result is 0 1 T 0010nnnnmmmm1000 1 Test result TST imm R0 R0 imm if the result is 0 1 T 11001000iiiiiiii 1 Test result TST B imm R0 GBR R0 GBR imm if the result is 0 1 T 1100110...

Page 62: ... ROTCL Rn T Rn T 0100nnnn00100100 1 MSB ROTCR Rn T Rn T 0100nnnn00100101 1 LSB SHAL Rn T Rn 0 0100nnnn00100000 1 MSB SHAR Rn MSB Rn T 0100nnnn00100001 1 LSB SHLL Rn T Rn 0 0100nnnn00000000 1 MSB SHLR Rn 0 Rn T 0100nnnn00000001 1 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 1 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 1 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 1 SHLR8 Rn Rn 8 Rn 0100nnnn00011001 1 SHLL16 Rn Rn 16 Rn 0100...

Page 63: ... PC PC if T 0 nop 10001001dddddddd 3 1 BT S label Delayed branch if T 1 disp 2 PC PC if T 0 nop 10001101dddddddd 2 1 BRA label Delayed branch disp 2 PC PC 1010dddddddddddd 2 BRAF Rm Delayed branch Rm PC PC 0000mmmm00100011 2 BSR label Delayed branch PC PR disp 2 PC PC 1011dddddddddddd 2 BSRF Rm Delayed branch PC PR Rm PC PC 0000mmmm00000011 2 JMP Rm Delayed branch Rm PC 0100mmmm00101011 2 JSR Rm D...

Page 64: ...BR Rm 4 Rm 0100mmmm00100111 3 LDS Rm MACH Rm MACH 0100mmmm00001010 1 LDS Rm MACL Rm MACL 0100mmmm00011010 1 LDS Rm PR Rm PR 0100mmmm00101010 1 LDS L Rm MACH Rm MACH Rm 4 Rm 0100mmmm00000110 1 LDS L Rm MACL Rm MACL Rm 4 Rm 0100mmmm00010110 1 LDS L Rm PR Rm PR Rm 4 Rm 0100mmmm00100110 1 NOP No operation 0000000000001001 1 RTE Delayed branch Stack area PC SR 0000000000101011 5 SETT 1 T 00000000000110...

Page 65: ...Rn PR Rn 0100nnnn00100010 1 TRAPA imm PC SR Stack area imm 4 VBR PC 11000011iiiiiiii 8 Note Number of execution cycles until this LSI enters sleep mode About the number of execution cycles The table lists the minimum number of execution cycles In practice the number of execution cycles will be increased depending on the conditions such as When there is a conflict between instruction fetch and data...

Page 66: ...set by WDT occurs From any state when RES 0 From any state when RES 1 and MRES 0 Power on reset state Manual reset state RES 0 Reset state RES 1 RES 1 MRES 1 Exception handling state Exception processing source occurs Exception processing ends Program execution state NMI interrupt or IRQ interrupt occurs Sleep mode SSBY bit 1 and STBYMD bit 1 for SLEEP instruction SSBY bit 0 for SLEEP instruction ...

Page 67: ...am counter PC and the initial value of the stack pointer SP are fetched from the exception handling vector table Then a branch is made for the start address to execute a program When an interrupt occurs the PC and status register SR are saved in the stack area pointed to by SP The start address of an exception handling routine is fetched from the exception handling vector table and a branch to the...

Page 68: ...Section 2 CPU Rev 3 00 Sep 27 2007 Page 48 of 758 REJ09B0243 0300 ...

Page 69: ...hese pins in the other way than the shown combinations When power is applied to the system be sure to conduct power on reset The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip mode For the on chip flash memory programming mode boot mode user boot mode and user program mode which are on chip programming modes are available Table 3 1 Selection of Operating Modes P...

Page 70: ...mode related pin Table 3 2 Pin Configuration Pin Name Input Output Function MD1 Input Designates operating mode through the level applied to this pin FWE Input Enables by hardware programming erasing of the on chip flash memory 3 3 Operating Modes 3 3 1 Mode 3 Single Chip Mode All ports can be used in this mode however the external address cannot be used ...

Page 71: ... operating modes are shown in figures 3 1 to 3 3 Mode 3 Single chip mode On chip ROM 128 kbytes On chip RAM 8 kbytes Reserved area On chip peripheral I O registers H 00000000 H FFFF9FFF H FFFFA000 H FFFFBFFF H FFFFC000 H FFFFFFFF H 0001FFFF H 00020000 Figure 3 1 Address Map in SH7125 SH7124 128 Kbytes Flash Memory Version ...

Page 72: ... 0300 H FFFF9FFF H FFFFA000 H FFFFBFFF H FFFFC000 H FFFFFFFF H 00000000 H 0000FFFF H 00010000 Mode 3 Single chip mode On chip ROM 64 kbytes On chip RAM 8 kbytes Reserved area On chip peripheral I O registers Figure 3 2 Address Map in SH7125 SH7124 64 Kbytes Flash Memory Version ...

Page 73: ...243 0300 H FFFF9FFF H FFFFA000 H FFFFBFFF H FFFFC000 H FFFFFFFF H 00000000 H 00007FFF H 00008000 Mode 3 Single chip mode On chip ROM 32 kbytes On chip RAM 8 kbytes Reserved area On chip peripheral I O registers Figure 3 3 Address Map in SH7124 32 Kbytes Flash Memory Version ...

Page 74: ...n operating these modules clear module standby state according to the procedure in section 19 Power Down Modes 3 6 Note on Changing Operating Mode When changing operating mode while power is applied to this LSI make sure to do it in the power on reset state that is the low level is applied to the RES pin Note See section 21 3 2 Control Signal Timing tMDS MD1 RES Figure 3 4 Reset Input Timing when ...

Page 75: ...clock Bφ CK for the external bus interface and a MTU2 clock MPφ for the on chip MTU2 module Frequency change function Frequencies of the internal clock Iφ bus clock Bφ peripheral clock Pφ and MTU2 clock MPφ can be changed independently using the divider circuit within the CPG Frequencies are changed by software using the frequency control register FRQCR setting Power down mode control The clock ca...

Page 76: ...tion control register Standby control register 1 Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 Standby control register 6 Peripheral clock Pφ Bus clock Bφ CK EXTAL XTAL FRQCR OSCCR STBCR2 STBCR1 STBCR3 STBCR4 STBCR5 STBCR6 CPG control unit MTU2 clock MPφ Clock frequency control circuit Standby control circuit Legend 1 2 1 4 1 8 Divider ...

Page 77: ...op Detection Circuit This circuit detects an abnormal condition in the crystal oscillator Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency according to the setting in the frequency control register FRQCR Standby Control Circuit The standby control circuit controls the state of the on chip oscillator circuit and other modules in sleep or standby mode ...

Page 78: ...dule Operating Clock Operating Module Internal clock Iφ CPU Peripheral clock Pφ POE UBC SCI ROM A D RAM CMT WDT Bus clock Bφ MTU2 clock MPφ MTU2 4 2 Input Output Pins Table 4 2 shows the CPG pin configuration Table 4 2 Pin Configuration Pin Name Abbr I O Description XTAL Output Connects a crystal resonator Crystal input output pins clock input pins EXTAL Input Connects a crystal resonator or an ex...

Page 79: ...ernal clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on chip modules in this LSI which eliminates the need to generate a high frequency clock outside the LSI Since the input clock frequency ranging from 10 MHz to 12 5 MHz can be used the internal clock Iφ frequency ranges from 10 MHz to 50 MHz Maximum operating frequencies Iφ 50 MHz Bφ 40 MHz Pφ 4...

Page 80: ...ency control register 2 The output frequency of the PLL circuit is the product of the frequency of the input from the crystal resonator or EXTAL pin and the multiplication ratio 8 of the PLL circuit 3 The input to the divider is always the output from the PLL circuit 4 The internal clock Iφ frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin the multiplic...

Page 81: ...rol register OSCCR R W H 00 H FFFFE814 8 4 4 1 Frequency Control Register FRQCR FRQCR is a 16 bit readable writable register that specifies the frequency division ratios for the internal clock Iφ bus clock Bφ peripheral clock Pφ and MTU2 clock MPφ FRQCR can be accessed only in words FRQCR is initialized to H 36DB only by a power on reset except a power on reset due to a WDT overflow Before making ...

Page 82: ...cy of PLL circuit If a prohibited value is specified subsequent operation is not guaranteed 000 Setting prohibited 001 1 2 010 Setting prohibited 011 1 4 initial value 100 1 8 Other than above Setting prohibited 11 to 9 BFC 2 0 011 R W Bus Clock Bφ Frequency Division Ratio Specify the division ratio of the bus clock Bφ frequency with respect to the output frequency of PLL circuit If a prohibited v...

Page 83: ...d 000 Setting prohibited 001 1 2 010 Setting prohibited 011 1 4 initial value 100 1 8 Other than above Setting prohibited 5 to 3 011 R W Reserved These bits are always read as B 011 The write value should always be B 011 2 to 0 MPFC 2 0 011 R W MTU2 Clock MPφ Frequency Division Ratio Specify the division ratio of the MTU2 clock MPφ frequency with respect to the output frequency of PLL circuit If a...

Page 84: ... The write value should always be 0 2 OSCSTOP 0 R Oscillation Stop Detection Flag Setting conditions When a stop in the clock input is detected during normal operation When software standby mode is entered Clearing conditions By a power on reset input through the RES pin When software standby mode is canceled 1 0 R Reserved This bit is always read as 0 The write value should always be 0 0 OSCERS 0...

Page 85: ...M 3 Set the desired values in bits IFC2 to IFC0 BFC2 to BFC0 PFC2 to PFC0 and MPFC2 to MPFC0 bits Since the frequency multiplication ratio in the PLL circuit is fixed at 8 the frequencies are determined only be selecting division ratios When specifying the frequencies satisfy the following condition internal clock Iφ bus clock Bφ peripheral clock Pφ When using the MTU2 clock specify the frequencie...

Page 86: ...nce frequency of 10 to 12 5 MHz It is recommended to consult the crystal resonator manufacturer concerning the compatibility of the crystal resonator and the LSI EXTAL XTAL Rd CL2 CL1 CL1 CL2 18 to 22 pF Reference values Figure 4 2 Connection of Crystal Resonator Example Table 4 6 Damping Resistance Values Reference Values Frequency MHz 10 12 5 Rd Ω Reference Values 0 0 Figure 4 3 shows an equival...

Page 87: ...e make the external clock high level to stop it when in software standby mode During operation make the external input clock frequency 10 to 12 5 MHz When leaving the XTAL pin open make sure the parasitic capacitance is less than 10 pF Even when inputting an external clock be sure to wait at least the oscillation stabilization time in power on sequence or in releasing software standby mode in orde...

Page 88: ...D signals in the MTU2 are assigned are always placed in high impedance state regardless of the PFC setting For details refer to appendix A Pin States Even in software standby mode these pins are always placed in high impedance state For details refer to appendix A Pin States These pins enter the normal state after software standby mode is canceled Under an abnormal condition where oscillation stop...

Page 89: ...termined in consultation with the resonator manufacturer The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin 4 8 2 Notes on Board Design Measures against radiation noise are taken in this LSI If further reduction in radiation noise is needed it is recommended to use a multiple layer board and provide a layer exclusive to the system ground When us...

Page 90: ...itry around the PLL Separate the PLL power lines PLLVss and the system power lines Vcc Vss at the board power supply source and be sure to insert bypass capacitors CB and CPB close to the pins PLLVSS VCL VCC VSS CPB 0 1 µF CB 0 1 µF Recommended values are shown Note CB and CPB are laminated ceramic type Figure 4 6 Recommended External Circuitry around PLL ...

Page 91: ... Manual reset Interrupt User break break before instruction execution Address error CPU address error instruction fetch Instruction General illegal instructions undefined code Illegal slot instruction undefined code placed immediately after a delayed branch instruction 1 or instruction that changes the PC value 2 Trap instruction TRAPA instruction Address error CPU address error data access Interr...

Page 92: ...iately after a delayed branch instruction or an instruction that changes the PC value is detected When exception handling starts the CPU operates Exception Handling Triggered by Reset The initial values of the program counter PC and stack pointer SP are fetched from the exception handling vector table PC from the address H 00000000 and SP from the address H 00000004 when a power on reset PC from t...

Page 93: ...s the vector numbers and vector table address offsets Table 5 4 shows how vector table addresses are calculated Table 5 3 Vector Numbers and Vector Table Address Offsets Exception Handling Source Vector Number Vector Table Address Offset Power on reset PC 0 H 00000000 to H 00000003 SP 1 H 00000004 to H 00000007 Manual reset PC 2 H 00000008 to H 0000000B SP 3 H 0000000C to H 0000000F General illega...

Page 94: ...120 to H 00000123 255 H 000003FC to H 000003FF Note For details on the vector numbers and vector table address offsets of on chip peripheral module interrupts see table 6 3 in section 6 Interrupt Controller INTC Table 5 4 Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address vector table address offset vector number 4 Ad...

Page 95: ... Power On Reset by RES Pin When the RES pin is driven low this LSI enters the power on reset state To reliably reset this LSI the RES pin should be kept low for at least the oscillation settling time when applying the power or when in standby mode when the clock is halted or at least 20 tcyc when the clock is operating During the power on reset state CPU internal states and all registers of on chi...

Page 96: ...address of the program counter PC is fetched from the exception handling vector table 2 The initial value of the stack pointer SP is fetched from the exception handling vector table 3 The vector base register VBR is cleared to H 00000000 and the interrupt mask bits I3 to I0 of the status register SR are set to H F B 1111 4 The values fetched from the exception handling vector table are set in the ...

Page 97: ...ce None normal Instruction fetched from on chip peripheral module space Address error occurs Instruction fetched from external memory space in single chip mode Address error occurs Word data accessed from even address None normal Data read write CPU Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None normal Longword data accessed from other...

Page 98: ...stack 2 The program counter PC is saved to the stack The PC value to be saved is the start address of the instruction which caused an address error exception When the instruction that caused the exception is placed in the delay slot the address of the delayed branch instruction which is placed immediately before the delay slot 3 The start address of the exception handling routine is fetched from t...

Page 99: ...t 1 User break User break controller UBC 1 IRQ IRQ0 to IRQ3 pins external input 4 SH7125 3 SH7124 On chip peripheral module Multi function timer pulse unit 2 MTU2 28 Watchdog timer WDT 1 A D converter A D_0 and A D_1 2 Compare match timer CMT_0 and CMT_1 2 Serial communication interface SCI_0 SCI_1 and SCI_2 12 Port output enable POE 2 All interrupt sources are given different vector numbers and v...

Page 100: ...o IPRM Table 5 8 Interrupt Priority Type Priority Level Comment NMI 16 Fixed priority level Cannot be masked User break 15 Fixed priority level Can be masked IRQ 0 to 15 On chip peripheral module Set with interrupt priority registers A to F and H to M IPRA to IPRF and IPRH to IPRM 5 4 3 Interrupt Exception Handling When an interrupt occurs the interrupt controller INTC ascertains its priority leve...

Page 101: ...ue JMP JSR BRA BSR RTS RTE BT BF TRAPA BF S BT S BSRF BRAF LDC Rm SR LDC L Rm SR General illegal instructions Undefined code anywhere besides in a delay slot Note The operation is not guaranteed when undefined instructions other than H F000 to H FFFF are decoded 5 5 2 Trap Instructions When a TRAPA instruction is executed the trap instruction exception handling starts The CPU operates as follows 1...

Page 102: ...tack The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC 3 The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the exception that occurred Program execution branches to that address and the program starts This branch is not a d...

Page 103: ...legal Instruction Trap Instruction Interrupt Instruction in delay slot 2 2 3 Immediately after interrupt disabled instruction 1 4 Legend Accepted Not accepted Does not occur Notes 1 Interrupt disabled instructions LDC LDC L STC STC L LDS LDS L STS and STS L 2 An exception is accepted before the execution of a delayed branch instruction However when an address error or a slot illegal instruction ex...

Page 104: ...ndling Ends Types Stack State Address error when the instruction that caused an exception is placed in the delay slot SP Address of delayed branch instruction SR 32 bits 32 bits Address error other than above SP SR 32 bits 32 bits Address of instruction that caused exception Interrupt SP SR 32 bits 32 bits Address of instruction after executed instruction Trap instruction SP SR 32 bits 32 bits Add...

Page 105: ...00 Sep 27 2007 Page 85 of 758 REJ09B0243 0300 Types Stack State Illegal slot instruction SP Address of delayed branch instruction SR 32 bits 32 bits General illegal instruction SP SR 32 bits 32 bits Address of general illegal instruction ...

Page 106: ...interrupts etc and address error exception handling will start after the first exception handling is ended Address errors will also occur in the stacking for this address error exception handling To ensure that address error exception handling does not go into an endless loop no address errors are accepted at that point This allows program control to be passed to the handling routine for address e...

Page 107: ...is as follows Compiler This instruction is not allocated in the delay slot in the compiler V 4 and its subsequent versions Real time OS for µITRON specifications 1 HI7000 4 HI SH7 This instruction does not exist in the delay slot within the OS 2 HI7000 This instruction is in part allocated to the delay slot within the OS which may cause the slot illegal instruction exception handling in this LSI 3...

Page 108: ...Section 5 Exception Handling Rev 3 00 Sep 27 2007 Page 88 of 758 REJ09B0243 0300 ...

Page 109: ...Section 6 Interrupt Controller INTC The interrupt controller INTC ascertains the priority of interrupt sources and controls interrupt requests to the CPU 6 1 Features 16 levels of interrupt priority NMI noise canceller function Occurrence of interrupt can be reported externally IRQOUT pin ...

Page 110: ...request SR CPU I3 I2 I1 I0 Internal bus Bus interface IPRA to IPRF IPRH to IPRM ICR0 IRQSR IRQCR Module bus INTC UBC User break controller WDT Watchdog timer CMT Compare match timer SCI Serial communication interface MTU2 Multi function timer pulse unit 2 A D A D converter POE Port output enable ICR0 Interrupt control register 0 IRQCR IRQ control register IRQSR IRQ status register IPRA to IPRF IPR...

Page 111: ...guration Table 6 1 Pin Configuration Name Abbr I O Function Non maskable interrupt input pin NMI Input Input of non maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3 Input Input of maskable interrupt request signals Interrupt request output pin IRQOUT Output Output of notification signal when an interrupt has occurred ...

Page 112: ... W H Fx00 H FFFFE904 8 16 Interrupt priority register A IPRA R W H 0000 H FFFFE906 8 16 Interrupt priority register B IPRB R W H 0000 H FFFFE908 8 16 Interrupt priority register C IPRC R W H 0000 H FFFFE980 16 Interrupt priority register D IPRD R W H 0000 H FFFFE982 16 Interrupt priority register E IPRE R W H 0000 H FFFFE984 16 Interrupt priority register F IPRF R W H 0000 H FFFFE986 16 Interrupt ...

Page 113: ...0 0 0 0 0 0 R R R R R R R R W R R R R R R R R NMIL NMIE Bit Bit Name Initial Value R W Description 15 NMIL R NMI Input Level Indicates the state of the signal input to the NMI pin This bit can be read to determine the NMI pin level This bit cannot be modified 0 State of the NMI input is low 1 State of the NMI input is high 14 to 9 All 0 R Reserved These bits are always read as 0 The write value sh...

Page 114: ...e should always be 0 7 6 IRQ31S IRQ30S 0 0 R W R W IRQ3 Sense Select Set the interrupt request detection mode for pin IRQ3 00 Interrupt request is detected at the low level of pin IRQ3 01 Interrupt request is detected at the falling edge of pin IRQ3 10 Interrupt request is detected at the rising edge of pin IRQ3 11 Interrupt request is detected at both the falling and rising edges of pin IRQ3 5 4 ...

Page 115: ...detected at the rising edge of pin IRQ1 11 Interrupt request is detected at both the falling and rising edges of pin IRQ1 1 0 IRQ01S IRQ00S 0 0 R W R W IRQ0 Sense Select SH7125 Set the interrupt request detection mode for pin IRQ0 00 Interrupt request is detected at the low level of pin IRQ0 01 Interrupt request is detected at the falling edge of pin IRQ0 10 Interrupt request is detected at the ri...

Page 116: ...igh and 0 when the level on the pin is low IRQ3L IRQ2L IRQ1L IRQ0L IRQ3F IRQ2F IRQ1F IRQ0F Bit Bit Name Initial Value R W Description 15 to 12 All 1 R Reserved These bits are always read as 1 11 IRQ3L R Indicates the state of pin IRQ3 0 State of pin IRQ3 is low 1 State of pin IRQ3 is high 10 IRQ2L R Indicates the state of pin IRQ2 0 State of pin IRQ2 is low 1 State of pin IRQ2 is high 9 IRQ1L R In...

Page 117: ...ected 0 An IRQ3 interrupt has not been detected Clearing condition Driving pin IRQ3 high 1 An IRQ3 interrupt has been detected Setting condition Driving pin IRQ3 low When edge detection mode is selected 0 An IRQ3 interrupt has not been detected Clearing conditions Writing 0 after reading IRQ3F 1 Accepting an IRQ3 interrupt 1 An IRQ3 interrupt request has been detected Setting condition Detecting t...

Page 118: ...s Writing 0 after reading IRQ2F 1 Accepting an IRQ2 interrupt 1 An IRQ2 interrupt request has been detected Setting condition Detecting the specified edge of pin IRQ2 1 IRQ1F 0 R W Indicates the status of an IRQ1 interrupt request When level detection mode is selected 0 An IRQ1 interrupt has not been detected Clearing condition Driving pin IRQ1 high 1 An IRQ1 interrupt has been detected Setting co...

Page 119: ...n IRQ0 Note The initial value is 1 when the level on the corresponding IRQ pin is high and 0 when the level on the pin is low 6 3 4 Interrupt Priority Registers A to F and H to M IPRA to IPRF and IPRH to IPRM Interrupt priority registers are twelve 16 bit readable writable registers that set priority levels from 0 to 15 for interrupts except NMI For the correspondence between interrupt request sou...

Page 120: ...1001 Priority level 9 1010 Priority level 10 1011 Priority level 11 1100 Priority level 12 1101 Priority level 13 1110 Priority level 14 1111 Priority level 15 highest 11 to 8 IPR 11 8 0000 R W Set priority levels for the corresponding interrupt source 0000 Priority level 0 lowest 0001 Priority level 1 0010 Priority level 2 0011 Priority level 3 0100 Priority level 4 0101 Priority level 5 0110 Pri...

Page 121: ... Priority level 12 1101 Priority level 13 1110 Priority level 14 1111 Priority level 15 highest 3 to 0 IPR 3 0 0000 R W Set priority levels for the corresponding interrupt source 0000 Priority level 0 lowest 0001 Priority level 1 0010 Priority level 2 0011 Priority level 3 0100 Priority level 4 0101 Priority level 5 0110 Priority level 6 0111 Priority level 7 1000 Priority level 8 1001 Priority le...

Page 122: ...h pin using the interrupt priority register A IPRA In the case that the low level detection is selected an interrupt request signal is sent to the INTC while the IRQ pin is driven low The interrupt request signal stops to be sent to the INTC when the IRQ pin becomes high It is possible to confirm that an interrupt is requested by reading the IRQ flags IRQ3F to IRQ0F in the IRQ status register IRQS...

Page 123: ...nterrupt has occurred Priority levels between 0 and 15 can be allocated to individual on chip peripheral modules in interrupt priority registers C to F and H to M IPRC to IPRF and IPRH to IPRM On chip peripheral module interrupt exception handling sets the interrupt mask level bits I3 to I0 in the status register SR to the priority level value of the on chip peripheral module interrupt that was ac...

Page 124: ...s on calculation of vector table addresses see table 5 4 in section 5 Exception Handling IRQ interrupts and on chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A to F and H to M IPRA to IPRF and IPRH to IPRM However when interrupt sources whose priority levels are allocated with the same IPR are requested ...

Page 125: ... 67 H 0000010C IPRA3 to IPRA0 TGIA_0 88 H 00000160 IPRD15 to IPRD12 TGIB_0 89 H 00000164 TGIC_0 90 H 00000168 TGID_0 91 H 0000016C TCIV_0 92 H 00000170 IPRD11 to IPRD8 TGIE_0 93 H 00000174 MTU2_0 TGIF_0 94 H 00000178 TGIA_1 96 H 00000180 IPRD7 to IPRD4 TGIB_1 97 H 00000184 TCIV_1 100 H 00000190 IPRD3 to IPRD0 MTU2_1 TCIU_1 101 H 00000194 MTU2_2 TGIA_2 104 H 000001A0 IPRE15 to IPRE12 TGIB_2 105 H 0...

Page 126: ... 130 H 00000208 POE MTU2 OEI1 132 H 00000210 IPRF3 to IPRF0 OEI3 133 H 00000214 CMT_0 CMI_0 184 H 000002E0 IPRJ15 to IPRJ12 CMT_1 CMI_1 188 H 000002F0 IPRJ11 to IPRJ8 WDT ITI 196 H 00000310 IPRJ3 to IPRJ0 ADI_0 200 H 00000320 IPRK15 to IPRK12 A D_0 and A D_1 ADI_1 201 H 00000324 SCI_0 ERI_0 216 H 00000360 IPRL15 to IPRL12 RXI_0 217 H 00000364 TXI_0 218 H 00000368 TEI_0 219 H 0000036C SCI_1 ERI_1 2...

Page 127: ...d If the priority level of the selected request is higher than the level in bits I3 to I0 the interrupt controller accepts the request and sends an interrupt request signal to the CPU 4 When the interrupt controller accepts an interrupt a low level is output from the IRQOUT pin 5 The CPU detects the interrupt request sent from the interrupt controller in the decode stage of an instruction to be ex...

Page 128: ...tently accepted again read the interrupt source flag after it has been cleared confirm that it has been cleared and then execute an RTE instruction Interrupt requests that are designated as edge detect type are held pending until the interrupt requests are accepted IRQ interrupts however can be cancelled by accessing the IRQ status register IRQSR Interrupts held pending due to edge detection are c...

Page 129: ...e IRQOUT is output when the request priority level is higher than the level in bits I3 I0 of SR 2 When the accepted interrupt is sensed by edge a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution namely before saving SR to stack However if the interrupt controller accepts an interrupt with a higher priority th...

Page 130: ...the start address of the next instruction instruction at the return address after the executed instruction 2 Always make sure that SP is a multiple of 4 Figure 6 4 Stack after Interrupt Exception Handling 6 7 Interrupt Response Time Table 6 4 lists the interrupt response time which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of...

Page 131: ...terrupt exception handling until fetch of first instruction of exception handling routine starts 8 Icyc m1 m2 m3 8 Icyc m1 m2 m3 8 Icyc m1 m2 m3 Performs the saving PC and SR and vector address fetch Interrupt response time Total 9 Icyc 2 Pcyc m1 m2 m3 X 9 Icyc 1 Pcyc m1 m2 m3 X 9 Icyc 2 Pcyc m1 m2 m3 X Minimum 12 Icyc 2 Pcyc 12 Icyc 1 Pcyc 12 Icyc 2 Pcyc SR PC and vector table are all in on chip ...

Page 132: ...Note The interrupt source flag should be cleared in the interrupt handler To ensure that an interrupt source that should have been cleared is not inadvertently accepted again read the interrupt source flag after it has been cleared confirm that it has been cleared and then execute an RTE instruction ...

Page 133: ...els A and B User break can be requested as either the independent or sequential condition on channels A and B sequential break setting channel A and then channel B match with break conditions but not in the same bus cycle Address Comparison bits are maskable in 1 bit units One of the two address buses L bus address LAB and I bus address IAB can be selected Data 32 bit maskable One of the two data ...

Page 134: ... BDMRB BRSR BRDR BRCR User break interrupt request Legend BBRA Break bus cycle register A BARA Break address register A BAMRA Break address mask register A BDRA Break data register A BDMRA Break data mask register A BBRB Break bus cycle register B BARB Break address register B BAMRB Break address mask register B BDRB Break data register B BDMRB Break data mask register B BETR Execution times break...

Page 135: ... Break bus cycle register A BBRA R W H 0000 H FFFFF308 16 Break data register A BDRA R W H 00000000 H FFFFF310 32 Break data mask register A BDMRA R W H 00000000 H FFFFF314 32 Break address register B BARB R W H 00000000 H FFFFF320 32 Break address mask register B BAMRB R W H 00000000 H FFFFF324 32 Break bus cycle register B BBRB R W H 0000 H FFFFF328 16 Break data register B BDRB R W H 00000000 H...

Page 136: ... BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Bit Bit Name Initial Value R W Description 31 to 0 BAA31 to BAA 0 All 0 R W Break Address A Store the address on the LAB or IAB specifying break conditions of channel A 7 2 2 Break Address Mask Register A BAMRA BAMRA is a 32 bit readable writable register BAMRA specifies bits masked in the break address specified by BARA Bit Initial value R W Bit Initial va...

Page 137: ...truction fetch or data access 4 read or write and 5 operand size in the break conditions of channel A Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R W R W R W R W R W R W R W R W R W R W CPA 2 0 CDA 1 0 IDA 1 0 RWA 1 0 SZA 1 0 Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write v...

Page 138: ...ition is the instruction fetch cycle 10 The break condition is the data access cycle 11 The break condition is the instruction fetch cycle or data access cycle 3 2 RWA 1 0 00 R W Read Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition 00 Condition comparison is not performed 01 The break condition is the read cycle 10 The break condition is the wr...

Page 139: ...R W R W R W R W R W R W R W BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 Bit Bit Name Initial Value R W Description 31 to 0 BDA31 to BDA0 All 0 R W Break Data Bit A Stores data which specifies a break condition in channel A If the I bus is selected in BBRA the br...

Page 140: ...MA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 BDMA8 BDMA7 BDMA6 BDMA5 BDMA4 BDMA3 BDMA2 BDMA1 BDMA0 Bit Bit Name Initial Value R W Description 31 to 0 BDMA31 to BDMA 0 All 0 R W Break Data Mask A Specifies bits masked in the break data of channel A specified by BDRA BDA31 to BDA0 0 Break data BDAn of channel...

Page 141: ... 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 Bit B...

Page 142: ...W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 Bit Bit Name Initial Value R W Description 31 to 0 BAMB31 to BAMB 0 All 0 R W Break Addr...

Page 143: ...W R W R W R W R W R W R W R W BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 Bit Bit Name Initial Value R W Description 31 to 0 BDB31 to BDB0 All 0 R W Break Data Bit B Stores data which specifies a break condition in channel B If the I bus is selected in BBRB the ...

Page 144: ...MB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Bit Bit Name Initial Value R W Description 31 to 0 BDMB31 to BDMB 0 All 0 R W Break Data Mask B Specifies bits masked in the break data of channel B specified by BDRB BDB31 to BDB0 0 Break data BDBn of channel...

Page 145: ... 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 8 CPB 2 0 000 R W Bus Master Select B for I Bus Select the bus master when the I bus is selected as the bus cycle of the channel B break condition However when the L bus is selected as the bus cycle the setting of the CPB2 to CPB0 bits is disabled 000 Condition comparison is not performed xx1 The CPU cycl...

Page 146: ... cycle 3 2 RWB 1 0 00 R W Read Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition 00 Condition comparison is not performed 01 The break condition is the read cycle 10 The break condition is the write cycle 11 The break condition is the read cycle or write cycle 1 0 SZB 1 0 0 R W Operand Size Select B Select the operand size of the bus cycle for th...

Page 147: ...s break conditions match flags and bits for setting a variety of break conditions Bit Initial value R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R R W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R R R W R W R W R R W R R R W UBIDB UBIDA SCM FCA SCM FCB SCM FD...

Page 148: ...on in the break conditions set for channel A is satisfied this flag is set to 1 In order to clear this flag write 0 into this bit 0 The L bus cycle condition for channel A does not match 1 The L bus cycle condition for channel A matches 14 SCMFCB 0 R W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied this flag is set to 1 In o...

Page 149: ...fetch cycle for channel A as before or after instruction execution 0 PC break of channel A is set before instruction execution 1 PC break of channel A is set after instruction execution 9 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 DBEA 0 R W Data Break Enable A Selects whether or not the data bus condition is included in the break condition of channel A...

Page 150: ...ects two conditions of channels A and B as independent or sequential conditions 0 Channels A and B are compared under independent conditions 1 Channels A and B are compared under sequential conditions channel A then channel B 2 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 ETBE 0 R W Number of Execution Times Break Enable Enables the execution times break ...

Page 151: ...m number is 2 12 1 times When a break condition is satisfied it decreases BETR A user break interrupt is requested when the break condition is satisfied after BETR becomes H 0001 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W BET 11 0 Bit Bit Name Initial Value R W Description 15 to 12 All 0 R Rese...

Page 152: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R SVF BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 Bit Bit Name Initial Value R W Description 31 SVF 0 R BRSR Valid Flag Indicates whether the branch source address is st...

Page 153: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R DVF BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 Bit Bit Name Initial Value R W Description 31 DVF 0 R BRDR Valid Flag Indicates whether a branch destination address is s...

Page 154: ...or SCMFCB and the I bus condition match flag SCMFDA or SCMFDB for the appropriate channel 3 The appropriate condition match flags SCMFCA SCMFDA SCMFCB and SCMFDB can be used to check if the set conditions match or not The matching of the conditions sets flags but they are not reset Before using them again 0 must first be written to them and then reset flags 4 There may be an occasion when a break ...

Page 155: ...ccur after execution the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction As with pre execution breaks this cannot be used with overrun fetch instructions When this kind of break is set for a delayed branch instruction and its delay slot a break is not generated until the first instruction at the branch destination ...

Page 156: ... as the operand size of the break bus cycle register BBRA or BBRB When data values are included in break conditions a break is generated when the address conditions and data conditions both match To specify byte data for this case set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register BDRA or BDRB and break data mask register BDMRA or BDMRB When word or byte is s...

Page 157: ...h the break should occur can be clearly determined except for when data is included in the break condition If the I bus is specified as a break condition the instruction at which the break should occur cannot be clearly determined 1 When instruction fetch before instruction execution is specified as a break condition The address of the instruction that matched the break condition is saved in the s...

Page 158: ...g PCTE in BRCR to 1 enables PC traces When branch branch instruction and interrupt exception is generated the branch source address and branch destination address are stored in BRSR and BRDR respectively 2 The values stored in BRSR and BRDR are as given below due to the kind of branch If a branch occurs due to a branch instruction the address of the branch instruction is saved in BRSR and the addr...

Page 159: ...not included in the condition Channel B Address H 00008010 Address mask H 00000006 Data H 00000000 Data mask H 00000000 Bus cycle L bus instruction fetch before instruction execution read operand size is not included in the condition A user break occurs after an instruction of address H 00000404 is executed or before instructions of addresses H 00008010 to H 00008016 are executed Example 1 2 Regis...

Page 160: ...a H 00000000 Data mask H 00000000 Bus cycle L bus instruction fetch before instruction execution write word Channel B Address H 00031415 Address mask H 00000000 Data H 00000000 Data mask H 00000000 Bus cycle L bus instruction fetch before instruction execution read operand size is not included in the condition On channel A no user break occurs since instruction fetch is not a write cycle On channe...

Page 161: ...0000 Data H 00000000 Data mask H 00000000 Bus cycle L bus instruction fetch before instruction execution read longword The number of execution times break enable 5 times Channel B Address H 00001000 Address mask H 00000000 Data H 00000000 Data mask H 00000000 Bus cycle L bus instruction fetch before instruction execution read longword On channel A a user break occurs after the instruction of addre...

Page 162: ...ccess Cycle Example 2 1 Register specifications BARA H 00123456 BAMRA H 00000000 BBRA H 0064 BDRA H 12345678 BDMRA H FFFFFFFF BARB H 000ABCDE BAMRB H 000000FF BBRB H 006A BDRB H 0000A512 BDMRB H 00000000 BRCR H 00000080 Specified conditions Channel A channel B independent mode Channel A Address H 00123456 Address mask H 00000000 Data H 12345678 Data mask H FFFFFFFF Bus cycle L bus data access read...

Page 163: ... B independent mode Channel A Address H 00314154 Address mask H 00000000 Data H 12345678 Data mask H FFFFFFFF Bus cycle I bus CPU cycle instruction fetch read operand size is not included in the condition Channel B Address H 00055555 Address mask H 00000000 Data H 00000078 Data mask H 0000000F Bus cycle I bus CPU cycle data access write byte On channel A a user break occurs when instruction fetch ...

Page 164: ...est priority When a post execution break or data access break occurs simultaneously with a re execution type exception including pre execution break that has higher priority the re execution type exception is accepted and the condition match flag is not set see the exception in the following note The break will occur and the condition match flag will be set only after the exception source of the r...

Page 165: ...EJ09B0243 0300 8 Do not set a post execution break at a SLEEP instruction or a branch instruction for which a SLEEP instruction is placed in the delay slot In addition do not set a data access break at a SLEEP instruction or one or two instructions before a SLEEP instruction ...

Page 166: ...Section 7 User Break Controller UBC Rev 3 00 Sep 27 2007 Page 146 of 758 REJ09B0243 0300 ...

Page 167: ...ytes Version 64 Kbytes Version 32 Kbytes Version Bus Width H 00000000 to H 00007FFF 32 Kbytes H 00008000 to H 0000FFFF 64 Kbytes H 00010000 to H 0001FFFF On chip FLASH 128 Kbytes Reserved Reserved 32 H 00020000 to H 83FFFFFF Reserved H 84000000 to H 84007FFF 32 Kbytes H 84008000 to H 8400FFFF 64 Kbytes H 84010000 to H 8401FFFF On chip FLASH programming area 128 Kbytes Reserved Reserved 8 H 8402000...

Page 168: ...bus access takes one Iclk cycle I bus access takes one Bclk cycle and peripheral bus access takes two Pclk cycles When the on chip peripheral I O register is accessed by the CPU the period required for preparation for data transfer to the I bus is a period of 3 Iclk cycles Figure 8 1 shows an example of timing of write access to the peripheral bus when Iclk Bclk Pclk 4 1 1 From the L bus to which ...

Page 169: ...e rising edge of Pclk on which data is transferred from the I bus to the peripheral bus Because of this data is transferred from the I bus to the peripheral bus in a period of 1 m Bclk m 0 to 3 when Bclk Pclk 4 1 The relation of the timing of data output to the I bus and the rising edge of Pclk depends on the state of program execution In the case shown in figure 8 2 where Iclk Bclk 1 1 the period...

Page 170: ...300 period is required because Iclk Bclk Pclk In the case shown in figure 8 3 where n 0 and m 1 the period required for access by the CPU is 3 Iclk 2 Bclk 2 Pclk 2 Iclk Iclk L bus Bclk I bus Pclk Peripheral bus Figure 8 3 Timing of Read Access to the Peripheral Bus Iclk Bclk Pclk 4 2 1 ...

Page 171: ... 12 phase PWM output is possible in combination with synchronous operation Buffer operation settable for channels 0 3 and 4 Phase counting mode settable independently for each of channels 1 and 2 Cascade connection operation Fast access via internal 16 bit bus 28 interrupt sources Automatic transfer of register data A D converter start trigger can be generated Module standby mode can be settable A...

Page 172: ... TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRU_5 TGRV_5 TGRW_5 General registers buffer registers TGRC_0 TGRD_0 TGRF_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 I O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A 1 TIOC1B 1 TIOC2A 1 TIOC2B 1 TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Input pins TIC5U TIC5V TIC5W Counter clear function TGR compare match or input capture TGR compare match or input ca...

Page 173: ... Phase counting mode Buffer operation Dead time compensation counter function A D converter start trigger TGRA_0 compare match or input capture TGRE_0 compare match TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TCNT_4 underflow trough in complemen tary PWM mode ...

Page 174: ...ut capture 1A 2 Compare match or input capture 1B 2 Overflow Underflow 4 sources Compare match or input capture 2A 2 Compare match or input capture 2B 2 Overflow Underflow 5 sources Compare match or input capture 3A Compare match or input capture 3B Compare match or input capture 3C Compare match or input capture 3D Overflow 5 sources Compare match or input capture 4A Compare match or input captur...

Page 175: ...tart request delaying function A D converter start request at a match between TADCOR A_4 and TCNT_4 A D converter start request at a match between TADCOR B_4 and TCNT_4 Interrupt skipping function Skips TGRA_3 compare match interrupts Skips TCIV_4 interrupts Legend Possible Not possible Notes 1 This pin is supported only by the SH7125 2 Input capture is supported only by the SH7125 ...

Page 176: ...TIORH TSR TIER Channel 4 TCNTS TCBR TDDR TCDR TOER TOCR TGCR BUS I F Common TCNT TGRA TGRB TMDR TCR TIOR TSR TIER TSYR TSTR Channel 2 TCNT TGRA TGRB TMDR TCR TIOR TSR TIER Channel 1 TCNT TGRA TGRB TGRC TGRD TGRE TGRF TMDR TCR TIORL TIORH TSR TIER Channel 0 TCNTU TGRU TCNTV TGRV TCNTW TGRW TCR TIOR TIER TSR Channel 5 Control logic Module data bus Control logic for channels 0 to 2 Control logic for ...

Page 177: ...output PWM output pin TIOC1B I O TGRB_1 input capture input output compare output PWM output pin 2 TIOC2A I O TGRA_2 input capture input output compare output PWM output pin TIOC2B I O TGRB_2 input capture input output compare output PWM output pin 3 TIOC3A I O TGRA_3 input capture input output compare output PWM output pin TIOC3B I O TGRB_3 input capture input output compare output PWM output pin...

Page 178: ... Timer I O control register L_3 TIORL_3 R W H 00 H FFFFC205 8 Timer I O control register H_4 TIORH_4 R W H 00 H FFFFC206 8 16 Timer I O control register L_4 TIORL_4 R W H 00 H FFFFC207 8 Timer interrupt enable register_3 TIER_3 R W H 00 H FFFFC208 8 16 Timer interrupt enable register_4 TIER_4 R W H 00 H FFFFC209 8 Timer output master enable register TOER R W H C0 H FFFFC20A 8 Timer gate control re...

Page 179: ...FC230 8 16 Timer interrupt skipping counter TITCNT R H 00 H FFFFC231 8 Timer buffer transfer set register TBTER R W H 00 H FFFFC232 8 Timer dead time enable register TDER R W H 01 H FFFFC234 8 Timer output level buffer register TOLBR R W H 00 H FFFFC236 8 Timer buffer operation transfer mode register_3 TBTM_3 R W H 00 H FFFFC238 8 16 Timer buffer operation transfer mode register_4 TBTM_4 R W H 00 ...

Page 180: ...4 8 16 32 Timer status register_0 TSR_0 R W H C0 H FFFFC305 8 Timer counter_0 TCNT_0 R W H 0000 H FFFFC306 16 Timer general register A_0 TGRA_0 R W H FFFF H FFFFC308 16 32 Timer general register B_0 TGRB_0 R W H FFFF H FFFFC30A 16 Timer general register C_0 TGRC_0 R W H FFFF H FFFFC30C 16 32 Timer general register D_0 TGRD_0 R W H FFFF H FFFFC30E 16 Timer general register E_0 TGRE_0 R W H FFFF H F...

Page 181: ...8 16 32 Timer general register B_2 TGRB_2 R W H FFFF H FFFFC40A 16 Timer counter U_5 TCNTU_5 R W H 0000 H FFFFC480 16 32 Timer general register U_5 TGRU_5 R W H FFFF H FFFFC482 16 Timer control register U_5 TCRU_5 R W H 00 H FFFFC484 8 Timer I O control register U_5 TIORU_5 R W H 00 H FFFFC486 8 Timer counter V_5 TCNTV_5 R W H 0000 H FFFFC490 16 32 Timer general register V_5 TGRV_5 R W H FFFF H FF...

Page 182: ...urce See tables 9 4 and 9 5 for details 4 3 CKEG 1 0 00 R W Clock Edge 0 and 1 These bits select the input clock edge When the input clock is counted using both edges the input clock period is halved e g MPφ 4 both edges MPφ 2 rising edge If phase counting mode is used on channels 1 and 2 this setting is ignored and the phase counting mode setting has priority Internal clock edge selection is vali...

Page 183: ...r another channel performing synchronous clearing synchronous operation 1 Notes 1 Synchronous operation is set by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT is not cleared because the buffer register setting has priority and compare match input capture does not occur Table 9 5 CCLR0 to CCLR2 Channels 1 and 2 Channel Bit 7 Reserved 2 Bit 6 CCLR1 Bit 5 CC...

Page 184: ...nal clock counts on TCLKB pin input 1 0 External clock counts on TCLKC pin input 1 External clock counts on TCLKD pin input Table 9 7 TPSC0 to TPSC2 Channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock counts on MPφ 1 1 Internal clock counts on MPφ 4 1 0 Internal clock counts on MPφ 16 1 Internal clock counts on MPφ 64 1 0 0 External clock counts on TCLKA pin in...

Page 185: ...nal clock counts on TCLKB pin input 1 0 External clock counts on TCLKC pin input 1 Internal clock counts on MPφ 1024 Note This setting is ignored when channel 2 is in phase counting mode Table 9 9 TPSC0 to TPSC2 Channels 3 and 4 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 4 0 0 0 Internal clock counts on MPφ 1 1 Internal clock counts on MPφ 4 1 0 Internal clock counts on MPφ 16 1 Int...

Page 186: ...nnel The MTU2 has five TMDR registers one each for channels 0 to 4 TMDR register settings should be changed only when TCNT operation is stopped Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W BFE BFB BFA MD 3 0 Bit Bit Name Initial Value R W Description 7 0 Reserved This bit is always read as 0 The write value should always be 0 6 BFE 0 R W Buffer Operation E Spec...

Page 187: ...ead as 0 and cannot be modified 0 TGRB and TGRD operate normally 1 TGRB and TGRD used together for buffer operation 4 BFA 0 R W Buffer Operation A Specifies whether TGRB is to operate in the normal way or TGRB and TGRD are to be used together for buffer operation When TGRD is used as a buffer register TGRD input capture output compare do not take place in modes other than complementary PWM mode bu...

Page 188: ...entary PWM mode 1 transmit at crest 3 1 0 Complementary PWM mode 2 transmit at trough 3 1 Complementary PWM mode 2 transmit at crest and trough 3 Legend x Don t care Notes 1 PWM mode 2 cannot be set for channels 3 and 4 2 Phase counting mode cannot be set for channels 0 3 and 4 3 Reset synchronous PWM mode and complementary PWM mode can only be set for channel 3 When channel 3 is set to reset sync...

Page 189: ...Note also that in PWM mode 2 the output at the point at which the counter is cleared to 0 is specified When TGRC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register TIORH_0 TIOR_1 TIOR_2 TIORH_3 TIORH_4 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W IOB 3 0 IOA 3 0 Bit Bit Name Initial Value R W De...

Page 190: ... Table 9 13 TIORL_3 Table 9 17 TIORL_4 Table 9 19 3 to 0 IOC 3 0 0000 R W I O Control C0 to C3 Specify the function of TGRC See the following tables TIORL_0 Table 9 21 TIORL_3 Table 9 25 TIORL_4 Table 9 27 TIORU_5 TIORV_5 TIORW_5 Bit name Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W IOC 4 0 Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits...

Page 191: ... Initial output is 0 Toggle output at compare match 0 0 Output retained 1 Initial output is 1 0 output at compare match 0 Initial output is 1 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 Toggle output at compare match 0 Input capture at rising edge 0 1 Input capture at falling edge 0 1 x Input capture at both edges 1 1 x x Input capture register Capture input sourc...

Page 192: ...1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture at both edges 1 x x Input capture register 2 Capture input source is channel 1 count clock Input capture at TCNT_1 count up count down Legen...

Page 193: ... 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture at both edges 1 x x Input capture register Input capture at generation of TGRC_0 compa...

Page 194: ...utput is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register Input capture at both edges Legend x Don ...

Page 195: ...utput at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register Input...

Page 196: ...tial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register 2 Input capture at both edges Legend x Don t care Notes 1 After power on reset 0 is...

Page 197: ...utput at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register Input...

Page 198: ...tial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register 2 Input capture at both edges Legend x Don t care Notes 1 After power on reset 0 is...

Page 199: ... output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture at both edges 1 x x Input capture register Capture input sourc...

Page 200: ...1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture at both edges 1 x x Input capture register 2 Capture input source is channel 1 count clock Input capture at TCNT_1 count up count down Legen...

Page 201: ...itial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture at both edges 1 x x Input capture register Input capture at generation of channel 0 TGRA_0 ...

Page 202: ...utput is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register Input capture at both edges Legend x Don ...

Page 203: ...utput at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register Input...

Page 204: ...tial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register 2 Input capture at both edges Legend x Don t care Notes 1 After power on reset 0 is...

Page 205: ...utput at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register Input...

Page 206: ...tial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 x 0 0 Input capture at rising edge 1 Input capture at falling edge 1 x Input capture register 2 Input capture at both edges Legend x Don t care Notes 1 After power on reset 0 is...

Page 207: ...1 x x Setting prohibited 1 0 0 0 Setting prohibited 1 Measurement of low pulse width of external input signal Capture at trough in complementary PWM mode 1 0 Measurement of low pulse width of external input signal Capture at crest in complementary PWM mode 1 Measurement of low pulse width of external input signal Capture at crest and trough in complementary PWM mode 1 0 0 Setting prohibited 1 Meas...

Page 208: ... are always read as 0 The write value should always be 0 2 CMPCLR5U 0 R W TCNT Compare Clear 5U Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture 0 Disables TCNTU_5 to be cleared to H 0000 at TCNTU_5 and TGRU_5 compare match or input capture 1 Enables TCNTU_5 to be cleared to H 0000 at TCNTU_5 and TGRU_5 compare match or input capture 1 CMPCLR5V 0 R W TCNT Comp...

Page 209: ...le Register TIER The TIER registers are 8 bit readable writable registers that control enabling or disabling of interrupt requests for each channel The MTU2 has seven TIER registers two for channel 0 and one each for channels 1 to 5 TIER_0 TIER_1 TIER_2 TIER_3 TIER_4 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA...

Page 210: ...ts TCIU by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2 In channels 0 3 and 4 bit 5 is reserved It is always read as 0 and the write value should always be 0 0 Interrupt requests TCIU by TCFU disabled 1 Interrupt requests TCIU by TCFU enabled 4 TCIEV 0 R W Overflow Interrupt Enable Enables or disables interrupt requests TCIV by the TCFV flag when the TCFV flag in TSR is ...

Page 211: ...te value should always be 0 0 Interrupt requests TGIC by TGFC bit disabled 1 Interrupt requests TGIC by TGFC bit enabled 1 TGIEB 0 R W TGR Interrupt Enable B Enables or disables interrupt requests TGIB by the TGFB bit when the TGFB bit in TSR is set to 1 0 Interrupt requests TGIB by TGFB bit disabled 1 Interrupt requests TGIB by TGFB bit enabled 0 TGIEA 0 R W TGR Interrupt Enable A Enables or disa...

Page 212: ...pare match between TCNT_0 and TGRE_0 disabled 1 A D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 TGIEF 0 R W TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0 0 Interrupt requests TGIF by TGFE bit disabled 1 Int...

Page 213: ...5U Enables or disables interrupt requests TGIU_5 issued when the CMFU5 bit in TSR_5 is set to 1 0 Interrupt requests TGIU_5 disabled 1 Interrupt requests TGIU_5 enabled 1 TGIE5V 0 R W TGR Interrupt Enable 5V Enables or disables interrupt requests TGIV_5 issued when the CMFV5 bit in TSR_5 is set to 1 0 Interrupt requests TGIV_5 disabled 1 Interrupt requests TGIV_5 enabled 0 TGIE5W 0 R W TGR Interru...

Page 214: ...me Initial Value R W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4 In channel 0 bit 7 is reserved It is always read as 1 and the write value should always be 1 0 TCNT counts down 1 TCNT counts up 6 1 R Reserved This bit is always read as 1 The write value should always be 1 5 TCFU 0 R W 1 Underflow Flag Status flag that ind...

Page 215: ...de this flag is also set Clearing condition When 0 is written to TCFV after reading TCFV 1 2 3 TGFD 0 R W 1 Input Capture Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 3 and 4 Only 0 can be written for flag clearing In channels 1 and 2 bit 3 is reserved It is always read as 0 and the write value should always be 0 Setting condi...

Page 216: ...RC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register Clearing condition When 0 is written to TGFC after reading TGFC 1 2 1 TGFB 0 R W 1 Input Capture Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match Only 0 can be written for flag cl...

Page 217: ...n TCNT TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register Clearing condition When 0 is written to TGFA after reading TGFA 1 2 Notes 1 Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way 2 If another flag setting condition occurs before writing 0 ...

Page 218: ... the occurrence of compare match between TCNT_0 and TGRF_0 Setting condition When TCNT_0 TGRF_0 and TGRF_0 is functioning as compare register Clearing condition When 0 is written to TGFF after reading TGFF 1 2 0 TGFE 0 R W 1 Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0 Setting condition When TCNT_0 TGRE_0 and TGRE_0 is functioning as com...

Page 219: ...5 0 R W 1 Compare Match Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match Setting conditions When TCNTU_5 TGRU_5 and TGRU_5 is functioning as output compare register When TCNTU_5 value is transferred to TGRU_5 by input capture signal and TGRU_5 is functioning as input capture register When TCNTU_5 value is transferred to TGRU_5 and TGRU_5 is f...

Page 220: ...s When TCNTV_5 TGRV_5 and TGRV_5 is functioning as output compare register When TCNTV_5 value is transferred to TGRV_5 by input capture signal and TGRV_5 is functioning as input capture register When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the pulse width of the external input signal The transfer timing is specified by the IOC bits in timer I O ...

Page 221: ... to TGRW_5 by input capture signal and TGRW_5 is functioning as input capture register When TCNTW_5 value is transferred to TGRW_5 and TGRW_5 is functioning as a register for measuring the pulse width of the external input signal The transfer timing is specified by the IOC bits in timer I O control register W_5 TIORW_5 2 Clearing condition When 0 is written to CMFW5 after reading CMFW5 1 Notes 1 W...

Page 222: ...These bits are always read as 0 The write value should always be 0 2 TTSE 0 R W Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation In channels 3 and 4 bit 2 is reserved It is always read as 0 and the write value should always be 0 When using channel 0 in other than PWM mode do not set this bit to 1 0 When compare match ...

Page 223: ...Capture Control Register TICCR TICCR is an 8 bit readable writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded The MTU2 has one TICCR in channel 1 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W I2BE I2AE I1BE I1AE Bit Bit Name Initial Value R W Description 7 to 4 All 0 R Reserved These bits are always read as 0 The write value...

Page 224: ...1BE 0 R W Input Capture Enable Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions 0 Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1 Includes the TIOC1B pin in the TGRB_2 input capture conditions 0 I1AE 0 R W Input Capture Enable Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions 0 Does not include the TIOC1A p...

Page 225: ... Value R W Description 15 14 BF 1 0 00 R W TADCOBRA_4 TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4 For details see table 9 29 13 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 UT4AE 0 R W Up Count TRG4AN Enable Enables or disables A D converter start requests TRG4AN du...

Page 226: ...4 down count operation 1 A D converter start requests TRG4BN enabled during TCNT_4 down count operation 3 ITA3AE 0 R W TGIA_3 Interrupt Skipping Link Enable Select whether to link A D converter start requests TRG4AN with TGIA_3 interrupt skipping operation 0 Does not link with TGIA_3 interrupt skipping 1 Links with TGIA_3 interrupt skipping 2 ITA4VE 0 R W TCIV_4 Interrupt Skipping Link Enable Sele...

Page 227: ...is enabled while interrupt skipping is disabled A D converter start requests will not be issued Do not set to 1 when complementary PWM mode is not selected Table 9 29 Setting of Transfer Timing by BF1 and BF0 Bits Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register 0 1 Transfers data from the cycle set buffer register to the cycle...

Page 228: ...W R W R W R W R W R W R W R W R W Note TADCORA_4 and TADCORB_4 must not be accessed in eight bits they should always be accessed in 16 bits 9 3 11 Timer A D Converter Start Request Cycle Set Buffer Registers TADCOBRA_4 and TADCOBRB_4 TADCOBRA_4 and TADCOBRB_4 are 16 bit readable writable registers When the crest or trough of the TCNT_4 count is reached these register values are transferred to TADC...

Page 229: ... 1 and 2 four each for channels 3 and 4 and three for channel 5 TGRA TGRB TGRC and TGRD function as either output compare or input capture registers TGRC and TGRD for channels 0 3 and 4 can also be designated for operation as buffer registers TGR buffer register combinations are TGRA and TGRC and TGRB and TGRD TGRE_0 and TGRF_0 function as compare registers When the TCNT_0 count matches the TGRE_0...

Page 230: ...7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R R R R W R W R W CST4 CST3 CST2 CST1 CST0 Bit Bit Name Initial Value R W Description 7 CST4 0 R W 6 CST3 0 R W Counter Start 4 and 3 These bits select operation or stoppage for TCNT If 0 is written to the CST bit during operation with the TIOC pin designated for output the counter stops but the TIOC pin output compare output level is retained If TIOR is wri...

Page 231: ... to TCNT_0 count operation is stopped 1 TCNT_2 to TCNT_0 performs count operation TSTR_5 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R W R W R W CSTU5 CSTV5 CSTW5 Bit Bit Name Initial Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 CSTU5 0 R W Counter Start U5 Selects operation or stoppage for TCNTU_5 0 TCNTU_5 ...

Page 232: ...se bits are used to select whether operation is independent of or synchronized with other channels When synchronous operation is selected the TCNT synchronous presetting of multiple channels and synchronous clearing by counter clearing on another channel are possible To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to the...

Page 233: ...d the TCNT synchronous presetting of multiple channels and synchronous clearing by counter clearing on another channel are possible To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to the SYNC bit the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR 0 TCNT_2 to TCNT_0 operates independently TCN...

Page 234: ...CH2 SCH3 SCH4 Bit Bit Name Initial Value R W Description 7 SCH0 0 R W Synchronous Start Controls synchronous start of TCNT_0 in the MTU2 0 Does not specify synchronous start for TCNT_0 in the MTU2 1 Specifies synchronous start for TCNT_0 in the MTU2 Clearing condition When 1 is set to the CST0 bit of TSTR in MTU2 while SCH0 1 6 SCH1 0 R W Synchronous Start Controls synchronous start of TCNT_1 in t...

Page 235: ...Controls synchronous start of TCNT_3 in the MTU2 0 Does not specify synchronous start for TCNT_3 in the MTU2 1 Specifies synchronous start for TCNT_3 in the MTU2 Clearing condition When 1 is set to the CST3 bit of TSTR in MTU2 while SCH3 1 3 SCH4 0 R W Synchronous Start Controls synchronous start of TCNT_4 in the MTU2 0 Does not specify synchronous start for TCNT_4 in the MTU2 1 Specifies synchron...

Page 236: ...ription 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 RWE 1 R W Read Write Enable Enables or disables access to the registers which have write protection capability against accidental modification 0 Disables read write access to the registers 1 Enables read write access to the registers Clearing condition When 0 is written to the RWE bit after reading...

Page 237: ...ese bits are always read as 1 The write value should always be 1 5 OE4D 0 R W Master Enable TIOC4D This bit enables disables the TIOC4D pin MTU2 output 0 MTU2 output is disabled inactive level 1 MTU2 output is enabled 4 OE4C 0 R W Master Enable TIOC4C This bit enables disables the TIOC4C pin MTU2 output 0 MTU2 output is disabled inactive level 1 MTU2 output is enabled 3 OE3D 0 R W Master Enable TI...

Page 238: ...ow level is output 9 3 19 Timer Output Control Register 1 TOCR1 TOCR1 is an 8 bit readable writable register that enables disables PWM synchronized toggle output in complementary PWM mode reset synchronized PWM mode and controls output level inversion of PWM output Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R W R R R W R W R W R W Note This bit can be set to 1 only once after a power ...

Page 239: ...lects the reverse phase output level in reset synchronized PWM mode complementary PWM mode See table 9 30 0 OLSP 0 R W Output Level Select P 3 This bit selects the positive phase output level in reset synchronized PWM mode complementary PWM mode See table 9 31 Notes 1 This bit can be set to 1 only once after a power on reset After 1 is written 0 cannot be written to the bit 2 Setting the TOCL bit ...

Page 240: ...l High level High level Low level Figure 9 2 shows an example of complementary PWM mode output 1 phase when OLSN 1 and OLSP 1 TCNT_3 and TCNT_4 values TGRA_3 TGRA_4 TDDR H 0000 Time TCNT_4 TCNT_3 Positive phase output Reverse phase output Active level Compare match output up count Initial output Initial output Active level Compare match output down count Compare match output down count Compare mat...

Page 241: ...BR to TOCR2 For details see table 9 32 5 OLS3N 0 R W Output Level Select 3N This bit selects the output level on TIOC4D in reset synchronized PWM mode complementary PWM mode See table 9 33 4 OLS3P 0 R W Output Level Select 3P This bit selects the output level on TIOC4B in reset synchronized PWM mode complementary PWM mode See table 9 34 3 OLS2N 0 R W Output Level Select 2N This bit selects the out...

Page 242: ...er register TOLBR to TOCR2 0 1 Transfers data from the buffer register TOLBR to TOCR2 at the crest of the TCNT_4 count Transfers data from the buffer register TOLBR to TOCR2 when TCNT_3 TCNT_4 is cleared 1 0 Transfers data from the buffer register TOLBR to TOCR2 at the trough of the TCNT_4 count Setting prohibited 1 1 Transfers data from the buffer register TOLBR to TOCR2 at the crest and trough o...

Page 243: ...l Low level High level Note The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start Table 9 36 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Table 9 37 TIOC3D Outpu...

Page 244: ... Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R W R W R W R W R W R W OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R W Description 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 OLS3N 0 R W Specifies the buffer value to be transferred to the OLS3N bit in TOCR2 4 OLS3P 0 R W Specifies the buffer value to be transferred to the OLS...

Page 245: ... Setting Procedure in Buffer Operation 9 3 22 Timer Gate Control Register TGCR TGCR is an 8 bit readable writable register that controls the waveform output necessary for brushless DC motor control in reset synchronized PWM mode complementary PWM mode These register settings are ineffective for anything other than complementary PWM mode reset synchronized PWM mode Bit Initial value R W 7 6 5 4 3 2...

Page 246: ... Level output 1 Reset synchronized PWM complementary PWM output 3 FB 0 R W External Feedback Signal Enable This bit selects whether the switching of the output of the positive reverse phase is carried out automatically with the MTU2 channel 0 TGRA TGRB TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR 0 Output switching is external input Input sources are channel 0 TGRA TGRB T...

Page 247: ... OFF ON 1 0 OFF ON OFF ON OFF OFF 1 OFF ON OFF OFF OFF ON 1 0 0 OFF OFF ON OFF ON OFF 1 ON OFF OFF OFF ON OFF 1 0 OFF OFF ON ON OFF OFF 1 OFF OFF OFF OFF OFF OFF 9 3 23 Timer Subcounter TCNTS TCNTS is a 16 bit read only counter that is used only in complementary PWM mode The initial value of TCNTS is H 0000 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 248: ... 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Note Accessing the TDDR in 8 bit units is prohibited Always access in 16 bit units 9 3 25 Timer Cycle Data Register TCDR TCDR is a 16 bit register used only in complementary PWM mode Set half the PWM carrier sync value as the TCDR register value This register is constantly compared with the TCNTS counter in complementary PW...

Page 249: ...ted Always access in 16 bit units 9 3 27 Timer Interrupt Skipping Set Register TITCR TITCR is an 8 bit readable writable register that enables or disables interrupt skipping and specifies the interrupt skipping count The MTU2 has one TITCR Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W T3AEN 3ACOR 2 0 T4VEN 4VCOR 2 0 Bit Bit Name Initial value R W Description...

Page 250: ...s the TGIA_3 interrupt skipping count to 1 0 1 0 Sets the TGIA_3 interrupt skipping count to 2 0 1 1 Sets the TGIA_3 interrupt skipping count to 3 1 0 0 Sets the TGIA_3 interrupt skipping count to 4 1 0 1 Sets the TGIA_3 interrupt skipping count to 5 1 1 0 Sets the TGIA_3 interrupt skipping count to 6 1 1 1 Sets the TGIA_3 interrupt skipping count to 7 Table 9 41 Setting of Interrupt Skipping Coun...

Page 251: ...unt in these bits is incremented every time a TGIA_3 interrupt occurs Clearing conditions When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR When the T3AEN bit in TITCR is cleared to 0 When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 3 0 R Reserved This bit is always read as 0 2 to 0 4VCNT 2 0 000 R TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is...

Page 252: ... skipping operation The MTU2 has one TBTER Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R W R W BTE 1 0 Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 BTE 1 0 00 R W These bits enable or disable transfer from the buffer registers used in complementary PWM mode to the temporary registers ...

Page 253: ...isters with interrupt skipping operation 2 1 1 Setting prohibited Notes 1 Data is transferred according to the MD3 to MD0 bit setting in TMDR For details refer to section 9 4 8 Complementary PWM Mode 2 When interrupt skipping is disabled the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register TITCR or the skipping count set bits 3ACOR and 4VCOR in TITCR are cleared t...

Page 254: ...TDER must be modified only while TCNT stops Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 R R R R R R R R W TDER Bit Bit Name Initial Value R W Description 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 TDER 1 R W Dead Time Enable Specifies whether to generate dead time 0 Does not generate dead time 1 Generates dead time Clearing condition When...

Page 255: ...WCR must be modified only while TCNT stops Bit Initial value R W 7 6 5 4 3 2 1 0 Note Do not set to 1 when complementary PWM mode is not selected 0 0 0 0 0 0 0 0 R W R R R R R R R W CCE WRE Bit Bit Name Initial Value R W Description 7 CCE 0 R W Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode 0 Does not clear counters at TGRA_3 compar...

Page 256: ...re 9 40 0 Outputs the initial value specified in TOCR 1 Retains the waveform output immediately before synchronous clearing Setting condition When 1 is written to WRE after reading WRE 0 Note Do not set to 1 when complementary PWM mode is not selected 9 3 32 Bus Master Interface The timer counters TCNT general registers TGR timer subcounter TCNTS timer cycle buffer register TCBR timer dead time da...

Page 257: ...for example 1 Example of Count Operation Setting Procedure Figure 9 4 shows an example of the count operation setting procedure Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Free running counter Start count operation Free running counter Periodic counter Start count operation 1 2 3 4 5 5 1 Select the counter clock...

Page 258: ...ates free running counter operation TCNT value H FFFF H 0000 CST bit TCFV Time Figure 9 5 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means o...

Page 259: ...rocedure for Waveform Output by Compare Match Figure 9 7 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode Set output timing Start count operation Waveform output 1 2 3 1 Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial value is outpu...

Page 260: ...e the pin level does not change TCNT value H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 9 8 Example of 0 Output 1 Output Operation Figure 9 9 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing on compare match B and settings have been made such that the output is toggled...

Page 261: ...e input capture input for channels 0 and 1 MPφ 1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if MPφ 1 is selected 1 Example of Input Capture Operation Setting Procedure Figure 9 10 shows an example of the input capture operation setting procedure Input selection Select input capture input Start count Input capture operation 1 2...

Page 262: ...ng and falling edges have been selected as the TIOCA pin input capture input edge the falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT value H 0180 H 0000 TIOCA TGRA H 0010 H 0005 Counter cleared by TIOCB input falling edge H 0160 H 0005 H 0160 H 0010 TGRB H 0180 TIOCB Time Figure 9 11 Example of I...

Page 263: ...ynchronous operation Synchronous presetting Counter clearing Synchronous clearing Clearing source generation channel Select counter clearing source Start count Set synchronous counter clearing Start count 1 3 5 4 5 2 Synchronous operation selection 1 Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation 2 When the TCNT counter of any of the channel...

Page 264: ...chronous clearing has been set for the channel 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters and the data set in TGRB_0 is used as the PWM cycle For details of PWM modes see section 9 4 5 PWM Modes TCNT_0 to TC...

Page 265: ...register and can only operate as a compare match register Table 9 43 shows the register combinations used in buffer operation Table 9 43 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRE_0 TGRF_0 3 TGRA_3 TGRC_3 TGRB_3 TGRD_3 4 TGRA_4 TGRC_4 TGRB_4 TGRD_4 When TGR is an output compare register When a compare match occurs the...

Page 266: ...er general register TCNT Input capture signal Figure 9 15 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 9 16 shows an example of the buffer operation setting procedure Buffer operation Select TGR function Set buffer operation Start count Buffer operation 1 2 3 1 Designate TGR as an input capture register or output compare register by means of TIOR 2 Designate ...

Page 267: ...d to timer general register TGRA This operation is repeated each time that compare match A occurs For details of PWM modes see section 9 4 5 PWM Modes TCNT value TGRB_0 H 0000 TGRC_0 TGRA_0 H 0200 H 0520 TIOCA H 0200 H 0450 H 0520 H 0450 TGRA_0 H 0450 H 0200 Transfer Time Figure 9 17 Example of Buffer Operation 1 2 When TGR is an input capture register Figure 9 18 shows an operation example in whi...

Page 268: ...r mode registers TBTM_0 TBTM_3 and TBTM_4 Either compare match initial setting or TCNT clearing can be selected for the transfer timing TCNT clearing as transfer timing is one of the following cases When TCNT overflows H FFFF to H 0000 When H 0000 is written to TCNT during counting When TCNT is cleared to H 0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note TBTM must be modi...

Page 269: ...low of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR Underflow occurs only when the lower 16 bit TCNT is in phase counting mode Table 9 44 shows the register combinations used in cascaded operation Note When phase counting mode is set for channel 1 the counter clock setting is invalid and the counters operates independently in phase counting mode Table 9 44 Cascaded Combinations Combination Upper 16...

Page 270: ...l value TIOC2B Input capture from TCNT_2 to TGRB_2 I1BE bit 1 TIOC2B TIOC1B Example of Cascaded Operation Setting Procedure Figure 9 20 shows an example of the setting procedure for cascaded operation Cascaded operation Set cascading Start count Cascaded operation 1 2 1 Set bits TPSC2 to TPSC0 in the channel 1 TCR to B 1111 to select TCNT_2 overflow underflow counting 2 Set the CST bit in TSTR for...

Page 271: ...ditions In this example the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing Under these conditions the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition For the TGRA_2 input capture condition the TIOC2A rising edge ...

Page 272: ...Time TIOC1A TIOC2A TCNT_1 H 0514 H 0514 H 0513 H 0512 H 0513 H 0512 H C256 H C256 H FFFF H 6128 H 6128 H 2064 H 2064 H 9192 H 9192 Figure 9 23 Cascaded Operation Example c Cascaded Operation Example d in SH7125 Figure 9 24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions ...

Page 273: ... Sep 27 2007 Page 253 of 758 REJ09B0243 0300 TCNT_2 value H 0000 H 0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H 0513 H 0512 H 0513 H D000 H FFFF H D000 TCNT_0 value Time TGRA_0 Compare match between TCNT_0 and TGRA_0 Figure 9 24 Cascaded Operation Example d ...

Page 274: ...put from the TIOCA and TIOCC pins at compare matches A and C and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D The initial output value is the value set in TGRA or TGRC If the set values of paired TGRs are identical the output value does not change when a compare match occurs In PWM mode 1 a maximum 8 phase PWM output is possible 2 PWM mode...

Page 275: ...B TGRC_0 TIOC0C 0 TGRD_0 TIOC0C TIOC0D TGRA_1 TIOC1A 1 TGRB_1 TIOC1A TIOC1B TGRA_2 TIOC2A 2 TGRB_2 TIOC2A TIOC2B TGRA_3 Cannot be set TGRB_3 TIOC3A Cannot be set TGRC_3 Cannot be set 3 TGRD_3 TIOC3C Cannot be set TGRA_4 Cannot be set TGRB_4 TIOC4A Cannot be set TGRC_4 Cannot be set 4 TGRD_4 TIOC4C Cannot be set Notes In PWM mode 2 PWM output is not possible for the TGR register in which the period...

Page 276: ...s an output compare register and select the initial value and output value 4 Set the cycle in the TGR selected in 2 and set the duty in the other TGR 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6 Set the CST bit in TSTR to 1 to start the count operation Figure 9 25 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation Figure 9 26 shows an example of PWM mode 1 operation In th...

Page 277: ...CNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 outputting a 5 phase PWM waveform In this case the value set in TGRB_1 is used as the cycle and the values set in the other TGRs are used as the duty levels TCNT value TGRB_1 H 0000 TIOC0A Counter cleared by TGRB_1 compare match Time TGRA_1 TGRD_0 TGRC_0 TGRB_...

Page 278: ...rewritten TGRB rewritten TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultan...

Page 279: ...t If overflow occurs when TCNT is counting up the TCFV flag in TSR is set if underflow occurs when TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag reveals whether TCNT is counting up or down Table 9 47 shows the correspondence between external clock pins and channels Table 9 47 Phase Counting Mode Clock Input Pins External Clock Pins...

Page 280: ... 30 shows an example of phase counting mode 1 operation and table 9 48 summarizes the TCNT up down count conditions TCNT value Time TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Up count Down count Figure 9 30 Example of Phase Counting Mode 1 Operation Table 9 48 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Oper...

Page 281: ...ount TCNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 9 31 Example of Phase Counting Mode 2 Operation Table 9 49 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care Hig...

Page 282: ...ount TCNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 9 32 Example of Phase Counting Mode 3 Operation Table 9 50 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care Hig...

Page 283: ...s Time Up count Down count TCNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 9 33 Example of Phase Counting Mode 4 Operation Table 9 51 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High level Don...

Page 284: ...r clearing by TGRC_0 compare match TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period TGRB_0 is used for input capture with TGRB_0 and TGRD_0 operating in buffer mode The channel 1 counter input clock is designated as the TGRB_0 input capture source and the pulse widths of 2 phase encoder 4 multiplication pulses are detec...

Page 285: ...3 0300 TCNT_1 TCNT_0 Channel 1 TGRA_1 speed period capture TGRA_0 speed control period TGRB_1 position period capture TGRC_0 position control period TGRB_0 pulse width capture TGRD_0 buffer operation Channel 0 TCLKA TCLKB Edge detection circuit Figure 9 34 Phase Counting Mode Application Example ...

Page 286: ...ut Pins for Reset Synchronized PWM Mode Channel Output Pin Description 3 TIOC3B PWM output pin 1 TIOC3D PWM output pin 1 negative phase waveform of PWM output 1 4 TIOC4A PWM output pin 2 TIOC4C PWM output pin 2 negative phase waveform of PWM output 2 TIOC4B PWM output pin 3 TIOC4D PWM output pin 3 negative phase waveform of PWM output 3 Table 9 53 Register Settings for Reset Synchronized PWM Mode ...

Page 287: ... timer gate control register TGCR and set the feedback signal input source and output chopping or gate signal direct output 4 Reset TCNT_3 and TCNT_4 to H 0000 5 TGRA_3 is the period register Set the waveform period value in TGRA_3 Set the transition timing of the PWM output waveforms in TGRB_3 TGRA_4 and TGRB_4 Set times within the compare match range of TCNT_3 X TGRA_3 X set value 6 Select enabl...

Page 288: ...ate as upcounters The counter is cleared when a TCNT_3 and TGRA_3 compare match occurs and then begins incrementing from H 0000 The PWM output pin output toggles with each occurrence of a TGRB_3 TGRA_4 TGRB_4 compare match and upon counter clears TGRA_3 TGRB_3 TGRB_4 H 0000 TGRA_4 TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Time TCNT_3 and TCNT_4 values Figure 9 36 Reset Synchronized PWM Mode Operat...

Page 289: ...sters used A function to directly cut off the PWM output by using an external signal is supported as a port function Table 9 54 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOC3A Toggle output synchronized with PWM period or I O port TIOC3B PWM output pin 1 TIOC3C I O port TIOC3D PWM output pin 1 non overlapping negative phase waveform of PWM output 1 PWM output without...

Page 290: ...output 3 compare register Maskable by TRWER setting TGRC_4 PWM output 2 TGRA_4 buffer register Always readable writable TGRD_4 PWM output 3 TGRB_4 buffer register Always readable writable Timer dead time data register TDDR Set TCNT_4 and TCNT_3 offset value dead time value Maskable by TRWER setting Timer cycle data register TCDR Set TCNT_4 upper limit value 1 2 carrier cycle Maskable by TRWER sett...

Page 291: ...PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 POE0 POE1 POE3 External cutoff input External cutoff interrupt Registers that can always be read or written from the CPU Registers that cannot be read or written from the CPU except for TCNTS which can only be read Registers that can be read or written from the CPU but for which access disabling can be set by TRWER TGRA_...

Page 292: ... 4 using the timer synchro register TSYR 6 Set the output PWM duty in the duty registers TGRB_3 TGRA_4 TGRB_4 and buffer registers TGRD_3 TGRC_4 TGRD_4 Set the same initial value in each corresponding TGR 7 This setting is necessary only when no dead time should be generated Make appropriate settings in the timer dead time enable register TDER so that no dead time is generated 8 Set the dead time ...

Page 293: ...ated in this way TCNT_4 is initialized to H 0000 When the CST bit is set to 1 TCNT_4 counts up in synchronization with TCNT_3 and switches to down counting when it matches TCDR On reaching H 0000 TCNT4 switches to up counting and the operation is repeated in this way TCNTS is a read only counter It need not be initialized When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up down counting down coun...

Page 294: ...he Ta interval Data is not transferred to the temporary register in the Tb interval Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up or H 0000 when counting down The ti...

Page 295: ...RC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Tb2 Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS Output waveform is active low H 6400 H 0080 H 6400 H 6400 H 0080 H 0080 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 9 40 Example of Complementary PWM Mode Operation ...

Page 296: ...R bit in the timer dead time enable register TDER should be cleared to 0 TGRC_3 and TGRA_3 should be set to 1 2 the PWM carrier cycle 1 and TDDR should be set to 1 Set the respective initial PWM duty values in buffer registers TGRD_3 TGRC_4 and TGRD_4 The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary ...

Page 297: ... relationship between the positive and negative phases This non overlap time is called the dead time The non overlap time is set in the timer dead time data register TDDR The value set in TDDR is used as the TCNT_3 counter start value and creates non overlap between TCNT_3 and TCNT_4 Complementary PWM mode should be cleared before changing the contents of TDDR 6 Dead Time Suppressing Dead time gen...

Page 298: ...4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS Output waveform is active low Data1 Data2 Data1 Data2 Data1 Data2 Transfer from temporary register to compare register Transfer from temporary register to compare register Initial output Initial output Figure 9 41 Example of Operation without Dead Time ...

Page 299: ...nd TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register TMDR The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest and from the current cycle wh...

Page 300: ...this case the value written to a buffer register is transferred after TCNTS halts The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register TMDR Figure 9 43 shows an example of data updating in complementary PWM mode This example shows the mode in which data updating is performed at both the counter crest and t...

Page 301: ...r from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H 0000 BR data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6 Temp_R GR Time Compare register Buffer register ...

Page 302: ...ister TMDR until TCNT_4 exceeds the value set in the dead time register TDDR Figure 9 44 shows an example of the initial output in complementary PWM mode An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 9 45 Timer output control register settings OLSN bit 0 initial output high active level low OLSP bit 0 initial output high active level l...

Page 303: ...itial output high active level low OLSP bit 0 initial output high active level low TCNT_3 and TCNT_4 values TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Time Active level TCNT_3 and TCNT_4 count start TSTR setting Complementary PWM mode TMDR setting Positive phase output Negative phase output Figure 9 45 Example of Initial Output in Complementary PWM Mode 2 ...

Page 304: ...ring prior to a are ignored In the T2 period compare match c that turns off the positive phase has the highest priority and compare matches occurring prior to c are ignored In normal cases compare matches occur in the order a b c d or c d a b as shown in figure 9 46 If compare matches deviate from the a b c d order since the time for which the negative phase is off is less than twice the dead time...

Page 305: ...d T1 period T1 period a b c a b d TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 9 46 Example of Complementary PWM Mode Waveform Output 1 T2 period T1 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase c d a a b b Figure 9 47 Example of Complementary PWM Mode Waveform Output 2 ...

Page 306: ...1 period T2 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 9 48 Example of Complementary PWM Mode Waveform Output 3 a b c d a b T2 period T1 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 9 49 Example of Complementary PWM Mode 0 and 100 Waveform Output 1 ...

Page 307: ...iod T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase a c d a b b Figure 9 50 Example of Complementary PWM Mode 0 and 100 Waveform Output 2 T2 period T1 period T1 period a b c d TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 9 51 Example of Complementary PWM Mode 0 and 100 Waveform Output 3 ...

Page 308: ... H 0000 Positive phase Negative phase T2 period T1 period T1 period a b c b d a Figure 9 52 Example of Complementary PWM Mode 0 and 100 Waveform Output 4 c a d b T2 period T1 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 9 53 Example of Complementary PWM Mode 0 and 100 Waveform Output 5 ...

Page 309: ...hes occur simultaneously but if a turn on compare match and turn off compare match for the same phase occur simultaneously both compare matches are ignored and the waveform does not change 12 Toggle Output Synchronized with PWM Cycle In complementary PWM mode toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control regist...

Page 310: ...hronous clearing with bits CCLR2 to CCLR0 in the timer control register TCR it is possible to have TCNT_3 TCNT_4 and TCNTS cleared by another channel Figure 9 55 illustrates the operation Use of this function enables counter clearing and restarting to be performed by means of an external signal TGRA_3 TCDR TDDR H 0000 Channel 1 Input capture A TCNT_1 TCNT_3 TCNT_4 TCNTS Synchronous counter clearin...

Page 311: ... the trough as indicated by 10 or 11 in figure 9 56 When synchronous clearing occurs outside that interval the initial value specified by the OLS bits in TOCR is output Even in the Tb interval at the trough if synchronous clearing occurs in the initial value output period indicated by 1 in figure 9 56 immediately after the counters start operation initial value output is not suppressed In the MTU2...

Page 312: ... to 0 and halt timer counter TCNT operation Perform TWCR setting while TCNT_3 and TCNT_4 are stopped 2 Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing 3 Set bits CST3 and CST4 in TSTR to 1 to start count operation Figure 9 57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Examples o...

Page 313: ...EJ09B0243 0300 TGRA_3 TGRB_3 TCDR TDDR H 0000 Positive phase Negative phase Output waveform is active low Synchronous clearing TCNT_3 MTU2 TCNT_4 MTU2 Bit WRE 1 Figure 9 58 Example of Synchronous Clearing in Dead Time during Up Counting Timing 3 in Figure 9 56 Bit WRE of TWCR in MTU2 is 1 ...

Page 314: ...58 REJ09B0243 0300 Positive phase Negative phase Output waveform is active low Synchronous clearing Bit WRE 1 TCNT_3 MTU2 TCNT_4 MTU2 TGRA_3 TGRB_3 TCDR TDDR H 0000 Figure 9 59 Example of Synchronous Clearing in Interval Tb at Crest Timing 6 in Figure 9 56 Bit WRE of TWCR in MTU2 is 1 ...

Page 315: ...8 REJ09B0243 0300 Positive phase Negative phase Output waveform is active low Synchronous clearing Bit WRE 1 TCNT_3 MTU2 TCNT_4 MTU2 TGRA_3 TGRB_3 TCDR TDDR H 0000 Figure 9 60 Example of Synchronous Clearing in Dead Time during Down Counting Timing 8 in Figure 9 56 Bit WRE of TWCR is 1 ...

Page 316: ...300 Positive phase Negative phase Output waveform is active low Synchronous clearing Bit WRE 1 TGRA_3 TGRB_3 TCDR TDDR H 0000 Initial value output is suppressed TCNT_3 MTU2 TCNT_4 MTU2 Figure 9 61 Example of Synchronous Clearing in Interval Tb at Trough Timing 11 in Figure 9 56 Bit WRE of TWCR is 1 ...

Page 317: ...lementary PWM mode 1 transfer at crest 2 Do not specify synchronous clearing by another channel do not set the SYNC0 to SYNC4 bits in the timer synchronous register TSYR to 1 or the CE0A CE0B CE0C CE0D CE1A CE1B CE1C and CE1D bits in the timer synchronous clear register TSYCR to 1 3 Do not set the PWM duty value to H 0000 4 Do not set the PSYE bit in timer output control register 1 TOCR1 to 1 TGRA...

Page 318: ...d at pin TIOC0A TIOC0B or TIOC0C the output on off state is switched automatically When the FB bit is 1 the output on off state is switched when the UF VF or WF bit in TGCR is cleared to 0 or set to 1 The drive waveforms are output from the complementary PWM mode 6 phase output pins With this 6 phase output in the case of on output it is possible to use complementary PWM mode output and perform ch...

Page 319: ...in TIOC4B pin TIOC4D pin 6 phase output When BDC 1 N 1 P 1 FB 0 output active level high Figure 9 64 Example of Output Phase Switching by External Input 2 TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6 phase output When BDC 1 N 0 P 0 FB 1 output active level high Figure 9 65 Example of Output Phase Switching by Means of UF VF WF Bit Settings 1 ...

Page 320: ...verter Start Request Setting In complementary PWM mode an A D converter start request can be issued using a TGRA_3 compare match TCNT_4 underflow trough or compare match on a channel other than channels 3 and 4 When start requests using a TGRA_3 compare match are specified A D conversion can be started at the crest of the TCNT_3 count A D converter start requests can be set by setting the TTGE bit...

Page 321: ...sabled by the settings of registers TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur Before changing the skipping count be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter 1 Example of Interrupt Skipping Operation Setting Procedure Figure 9 67 shows an example of the interrupt skipping operation setting...

Page 322: ... count can be performed Figure 9 68 Periods during which Interrupt Skipping Count can be Changed 2 Example of Interrupt Skipping Operation Figure 9 69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register TITCR TGIA_3 interrupt flag set signal Skipping counter T...

Page 323: ... transfer timing is two types That is from the buffer register to the temporary register and from the temporary register to the buffer register These timings depend on a programming timing to the buffer register after an interrupt is generated Note that the buffer transfer enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register TITCR Figure 9 72 show...

Page 324: ...ER Bit BTE0 in TBTER 1 No data is transferred from the buffer register to the temporary register in the buffer transfer disabled period bits BTE1 and BTE0 in TBTER are set to 0 and 1 respectively 2 Data is transferred from the temporary register to the general register even in the buffer transfer disabled period 3 After buffer transfer is enabled data is transferred from the buffer register to the...

Page 325: ...nsfer at the crest is selected The skipping count is set to two T3AEN is set to 1 Buffer transfer enabled period 2 0 1 2 0 1 TGIA_3 interrupt occurred TGIA_3 interrupt occurred TGIA_3 interrupt occurred TGIA_3 interrupt occurred Buffer register rewriting timing Buffer register rewriting timing Buffer register rewriting timing 2 When rewriting a buffer register after a carrier cycle passed from occ...

Page 326: ...ree Buffer transfer enabled period T3AEN is set to 1 Buffer transfer enabled period T4VEN is set to 1 Buffer transfer enabled period T3AEN and T4VEN are set to 1 0 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Skipping counter 3ACNT Skipping counter 4VCNT Figure 9 72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer Enabled Period ...

Page 327: ...RL_4 TIER_3 and TIER_4 TCNT_3 and TCNT_4 TGRA_3 and TGRA_4 TGRB_3 and TGRB_4 TOER TOCR TGCR TCDR and TDDR This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers control registers and counters When the applicable registers are read in the access disabled state undefined values are returned Writing to these registers is ignored 2 Halting of ...

Page 328: ...st cycle A D converter start request delaying function Set the timing of transfer from cycle set buffer register Set linkage with interrupt skipping Enable A D converter start request delaying function A D converter start request delaying function 1 2 1 Set the cycle in the timer A D converter start request cycle buffer register TADCOBRA_4 or TADCOBRB_4 and timer A D converter start request cycle ...

Page 329: ...ated by writing data to the timer A D converter start request cycle set buffer registers TADCOBRA_4 and TADCOBRB_4 Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A D converter start request control register TADCR_4 4 A D Converter Start Request Delaying Function Linked with Interrupt Skipping A D con...

Page 330: ...ipping clear the ITA3AE ITA4VE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR to 0 TADCORA_4 TCNT_4 A D converter start request TRG4AN Note When the interrupt skipping count is set to two TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A D request enabled period TCIV_4 A D request enabled period When linked with TGIA_3 and TCIV_4 i...

Page 331: ...counter TCIV_4 interrupt skipping counter TGIA_3 A D request enabled period TCIV_4 A D request enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping TADCORA_4 TCNT_4 00 01 00 01 02 00 01 00 01 02 UT4AE 1 DT4AE 0 Figure 9 76 Example of A D Converter Start Request Signal TRG4AN Operation Linked with ...

Page 332: ...SC1 and TPSC0 in TCR to select the counter clock 2 In TIOR select the high level or low level for the pulse width measuring condition 3 Set bits CST in TSTR to 1 to start count operation Notes 1 Do not set bits CMPCLR5U CMPCLR5V or CMPCLR5W in TCNTCMPCLR to 1 2 Do not set bits TGIE5U TGIE5V or TGIE5W in TIER_5 to 1 3 The value in TCNT is not captured in TGR 1 2 3 Figure 9 77 Example of External Pu...

Page 333: ... of the output waveform and reflecting it to duty the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation Tdead Tdelay Upper arm signal Lower arm signal Inverter output detection signal Dead time delay signal Figure 9 79 Delay in Dead Time in Complementary PWM Operation ...

Page 334: ...ion specified in TIOR is satisfied the TCNT_5 value is captured in TGR_5 5 For U phase dead time compensation when an interrupt is generated at the crest TGIA_3 or trough TCIV_4 in complementary PWM mode read the TGRU_5 value calculate the difference in time in TGRB_3 and write the corrected value to TGRD_3 in the interrupt processing For the V phase and W phase read the TGRV_5 and TGRW_5 values a...

Page 335: ... TGR can be selected by TIOR Figure 9 82 is an operating example in which TCNT is used as a free running counter without being cleared and the TCNT value is captured in TGR at the specified timing either crest or trough or both crest and trough Tdead Tdelay Upper arm signal Lower arm signal Inverter output monitor signal Dead time delay signal TGRA_4 3DE7 3E5B 3E5B 3ED3 3ED3 3F37 3F37 3FAF 3FAF 3D...

Page 336: ...the generation of interrupt request signals to be enabled or disabled individually When an interrupt request is generated the corresponding status flag in TSR is set to 1 If the corresponding enable disable bit in TIER is set to 1 at this time an interrupt is requested The interrupt request is cleared by clearing the status flag to 0 Relative channel priorities can be changed by the interrupt cont...

Page 337: ...e match TGFA_2 TGIB_2 TGRB_2 input capture compare match TGFB_2 TCIV_2 TCNT_2 overflow TCFV_2 TCIU_2 TCNT_2 underflow TCFU_2 3 TGIA_3 TGRA_3 input capture compare match TGFA_3 TGIB_3 TGRB_3 input capture compare match TGFB_3 TGIC_3 TGRC_3 input capture compare match TGFC_3 TGID_3 TGRD_3 input capture compare match TGFD_3 TCIV_3 TCNT_3 overflow TCFV_3 4 TGIA_4 TGRA_4 input capture compare match TGF...

Page 338: ...nd 2 and three for channel 5 The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel The interrupt request is cleared by clearing the TCFV flag to 0 The MTU2 has five overflow interrupts one for ea...

Page 339: ... D converter start signal TRGAN from the MTU2 is selected as the trigger in the A D converter A D conversion will start A D Converter Activation by Compare Match between TCNT_0 and TGRE_0 The A D converter can be activated by generating A D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0 When the TGFE flag in TSR2_0 is set to 1 by the occurre...

Page 340: ...Start Request Signals Target Registers Interrupt Source A D Converter Start Request Signal TGRA_0 and TCNT_0 TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 Input capture compare match TCNT_4 TCNT_4 Trough in complementary PWM mode TRGAN TGRE_0 and TCNT_0 TRG0N TADCORA and TCNT_4 TRG4AN TADCORB and TCNT_4 Compare match TRG4BN ...

Page 341: ...ormal mode and figure 9 86 shows TCNT count timing in external clock operation phase counting mode TCNT TCNT input clock Internal clock MPφ Falling edge Rising edge N 1 N N 1 Figure 9 83 Count Timing in Internal Clock Operation Channels 0 to 4 TCNT TCNT input clock Internal clock MPφ Rising edge N 1 N Figure 9 84 Count Timing in Internal Clock Operation Channel 5 MPφ TCNT TCNT input clock External...

Page 342: ...e count value matched by TCNT is updated When a compare match signal is generated the output value set in TIOR is output at the output compare output pin TIOC pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 9 87 shows output compare output timing normal mode and PWM mode and figure 9 88 shows output compare output timi...

Page 343: ...N N 1 TGR Compare match signal TIOC pin N MPφ Figure 9 88 Output Compare Output Timing Complementary PWM Mode Reset Synchronous PWM Mode Input Capture Signal Timing Figure 9 89 shows input capture signal timing TCNT Input capture input N N 1 N 2 N N 2 TGR Input capture signal MPφ Figure 9 89 Input Capture Input Signal Timing ...

Page 344: ...w the timing when counter clearing on compare match is specified and figure 9 92 shows the timing when counter clearing on input capture is specified MPφ TCNT Counter clear signal Compare match signal TGR N N H 0000 Figure 9 90 Counter Clear Timing Compare Match MPφ TCNT Counter clear signal Compare match signal TGR N N 1 H 0000 Figure 9 91 Counter Clear Timing Compare Match Channel 5 ...

Page 345: ...Pφ Figure 9 92 Counter Clear Timing Input Capture Buffer Operation Timing Figures 9 93 to 9 95 show the timing in buffer operation TGRA TGRB Compare match buffer signal TCNT TGRC TGRD n N N n n 1 MPφ Figure 9 93 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal TGRC TGRD N n n N 1 N N N 1 MPφ Figure 9 94 Buffer Operation Timing Input Capture ...

Page 346: ... N n H 0000 Figure 9 95 Buffer Transfer Timing when TCNT Cleared Buffer Transfer Timing Complementary PWM Mode Figures 9 96 to 9 98 show the buffer transfer timing in complementary PWM mode Buffer register TGRD_4 write signal Temporary register transfer signal TCNTS MPφ Temporary register n N n N H 0000 Figure 9 96 Transfer Timing from Buffer Register to Temporary Register TCNTS Stop ...

Page 347: ...r TGRD_4 write signal TCNTS MPφ Temporary register n N n N P x P H 0000 Figure 9 97 Transfer Timing from Buffer Register to Temporary Register TCNTS Operating Temporary register Buffer transfer signal TCNTS MPφ Compare register N n N P 1 P H 0000 Figure 9 98 Transfer Timing from Temporary Register to Compare Register ...

Page 348: ... 9 100 show the timing for setting of the TGF flag in TSR on compare match and TGI interrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt MPφ Figure 9 99 TGI Interrupt Timing Compare Match Channels 0 to 4 TGR TCNT TCNT input clock N N 1 N Compare match signal TGF flag TGI interrupt MPφ Figure 9 100 TGI Interrupt Timing Compare Match Channel 5 ...

Page 349: ...and 9 102 show the timing for setting of the TGF flag in TSR on input capture and TGI interrupt request signal timing TGR TCNT Input capture signal N N TGF flag TGI interrupt MPφ Pφ Figure 9 101 TGI Interrupt Timing Input Capture Channels 0 to 4 TGR TCNT Input capture signal N N TGF flag TGI interrupt MPφ Pφ Figure 9 102 TGI Interrupt Timing Input Capture Channel 5 ...

Page 350: ...interrupt request signal timing Figure 9 104 shows the timing for setting of the TCFU flag in TSR on underflow and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock H FFFF H 0000 TCFV flag TCIV interrupt MPφ Pφ Figure 9 103 TCIV Interrupt Setting Timing Underflow signal TCNT underflow TCNT input clock H 0000 H FFFF TCFU flag TCIU interrupt MPφ Pφ Figure 9 104 TCIU...

Page 351: ...it Figures 9 105 and 9 106 show the timing for status flag clearing by the CPU Status flag Write signal Address TSR address Interrupt request signal TSR write cycle T1 T2 MPφ Pφ Figure 9 105 Timing for Status Flag Clearing by CPU Channels 0 to 4 Status flag Write signal Address TSR address Interrupt request signal TSR write cycle T1 T2 MPφ Pφ Figure 9 106 Timing for Status Flag Clearing by CPU Cha...

Page 352: ...ates in the case of single edge detection and at least 2 5 states in the case of both edge detection The MTU2 will not operate properly at narrower pulse widths In phase counting mode the phase difference and overlap between the two input clocks must be at least 1 5 states and the pulse width must be at least 2 5 states Figure 9 107 shows the input clock conditions in phase counting mode Overlap P...

Page 353: ...N 1 Channel 5 f MPφ N Where f Counter frequency MPφ MTU2 peripheral clock operating frequency N TGR set value 9 7 4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 9 108 shows the timing in this case Counter clear signal Write signal Address TC...

Page 354: ...ent Operations If incrementing occurs in the T2 state of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 9 109 shows the timing in this case TCNT input clock Write signal Address TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data MPφ Figure 9 109 Contention between TCNT Write and Increment Operations ...

Page 355: ...h If a compare match occurs in the T2 state of a TGR write cycle the TGR write is executed and the compare match signal is also generated Figure 9 110 shows the timing in this case Compare match signal Write signal Address TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 MPφ Figure 9 110 Contention between TGR Write and Compare Match ...

Page 356: ...T2 state of a TGR write cycle the data that is transferred to TGR by the buffer operation is the data before write Figure 9 111 shows the timing in this case Address Write signal Compare match signal Compare match buffer signal TGR write cycle T1 T2 Buffer register address N N M Buffer register write data Buffer register TGR MPφ Figure 9 111 Contention between Buffer Register Write and Compare Mat...

Page 357: ...fer mode register TBTM if TCNT clear occurs in the T2 state of a TGR write cycle the data that is transferred to TGR by the buffer operation is the data before write Figure 9 112 shows the timing in this case Address Write signal TCNT clear signal Buffer transfer signal TGR write cycle T1 T2 Buffer register address N N M Buffer register write data Buffer register TGR MPφ Figure 9 112 Contention be...

Page 358: ...pture transfer for channels 0 to 4 and the data after input capture transfer for channel 5 Figures 9 113 and 9 114 show the timing in this case Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address MPφ N N M Figure 9 113 Contention between TGR Read and Input Capture Channels 0 to 4 Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal ...

Page 359: ...rformed for channels 0 to 4 For channel 5 write to TGR is performed and the input capture signal is generated Figures 9 115 and 9 116 show the timing in this case Input capture signal Write signal Address TCNT TGR write cycle T1 T2 M TGR M TGR address MPφ Figure 9 115 Contention between TGR Write and Input Capture Channels 0 to 4 Input capture signal Write signal Address TCNT TGR write cycle T1 T2...

Page 360: ...erflow Underflow Contention in Cascade Connection With timer counters TCNT_1 and TCNT_2 in a cascade connection when a contention occurs during TCNT_1 count during a TCNT_2 overflow underflow in the T2 state of the TCNT_2 write cycle the write to TCNT_2 is conducted and the TCNT_1 count signal is disabled At this point if there is match with TGRA_1 and the TCNT_1 value a compare signal is issued F...

Page 361: ...CNT_2 write data TCNT_2 address TCNT write cycle Address Write signal TCNT_2 TGRA_2 to TGRB_2 Ch2 compare match signal A B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare match signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D MPφ Figure 9 118 TCNT_2 Write and Overflow Underflow Contention with Cascade Connection ...

Page 362: ...A_3 TCDR TDDR H 0000 TCNT_3 TCNT_4 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 9 119 Counter Value during Complementary PWM Mode Stop 9 7 14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode conduct rewrites by buffer operation for the PWM cycle setting register TGRA_3 timer cycle data register...

Page 363: ... to 1 TGRC_3 functions as the buffer register for TGRA_3 At the same time TGRC_4 functions as the buffer register for TGRA_4 The TGFC bit and TGFD bit in TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers Figure 9 120 shows an example of operations for TGR_3 TGR_4 TIOC3 and TIOC4 with TMDR_3 s BFA and BFB bits set to 1 and TMDR_4 s BFA and BFB bits set to 0 TGRA_3...

Page 364: ...when specifying TGR3A compare match for the counter clear source TCNT_3 and TCNT_4 count up to H FFFF then a compare match occurs with TGRA_3 and TCNT_3 and TCNT_4 are both cleared At this point TSR s overflow flag TCFV bit is not set Figure 9 121 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H FFFF when a TGRA_3 compare match has be...

Page 365: ...ow and counter clearing occur simultaneously the TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 9 122 shows the operation timing when a TGR compare match is specified as the clearing source and when H FFFF is set in TGR Counter clear signal TCNT TCNT input clock H FFFF H 0000 TGF TCFV Disabled MPφ Figure 9 122 Contention between Overflow and Counter Clearing ...

Page 366: ...onized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset synchronized PWM mode if the counter is halted with the output pins TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D in the high level state followed by the transition to reset synchronized PWM mode and operation in that mode the initial pin output will not be correct When making a transition from normal ...

Page 367: ...a 32 bit counter in cascade connection the cascade counter value cannot be captured successfully even if input capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the ...

Page 368: ...ialization method for each of these modes is described in this section 9 8 2 Reset Start Operation The MTU2 output pins TIOC are initialized low by a reset and in standby mode Since MTU2 pin function selection is performed by the pin function controller PFC when the PFC is set the MTU2 pin states at that point are output to the ports When MTU2 output is selected by the PFC immediately after a rese...

Page 369: ...during operation etc and the procedures for restarting in a different mode after re setting are shown below The MTU2 has six operating modes as stated above There are thus 36 mode transition combinations but some transitions are not available with certain channel and mode combinations Possible mode transition combinations are shown in table 9 59 Table 9 59 Mode Transition Combinations After Before...

Page 370: ...n switch to PWM mode 2 In normal mode or PWM mode 2 if TGRC and TGRD operate as buffer registers setting TIOR will not initialize the buffer register pins If initialization is required clear buffer mode carry out initialization then set buffer mode again In PWM mode 1 if either TGRC or TGRD operates as a buffer register setting TIOR will not initialize the TGRC pin To initialize the TGRC pin clear...

Page 371: ...ule output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 9 124 Error Occurrence in Normal Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 After a reset the TMDR setting is for normal mode 3 For channels 3 and 4 enable output with TOER before initializing the pins with TIOR 4 Initialize the pins with TIOR The example sho...

Page 372: ...TU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 9 125 Error Occurrence in Normal Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 9 124 11 Set PWM mode 1 12 Initialize the pins with TIOR In PWM m...

Page 373: ...9 PFC PORT 10 TSTR 0 11 TMDR PWM2 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized cycle register n 0 to 15 High Z High Z Figure 9 126 Error Occurrence in Normal Mode Recovery in PWM Mode 2 1 to 10 are the same as in figure 9 124 11 Set PWM mode 2 12 Initialize the pins with TIOR In PWM mode 2 the cycle register pins are not initialize...

Page 374: ...R normal 3 TOER 1 5 PFC MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 9 127 Error Occurrence in Normal Mode Recovery in Phase Counting Mode 1 to 10 are the same as in figure 9 124 11 Set phase counting mode 12 Initialize the pins...

Page 375: ... out 12 TIOR disabled 13 TOER 0 14 TOCR 15 TMDR CPWM 16 TOER 1 17 PFC MTU2 18 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 9 128 Error Occurrence in Normal Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9 124 11 Initialize the normal mode waveform generation section with TIOR 12 Disable operation of the normal mode w...

Page 376: ...U2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TIOR 0 init 0 out 12 TIOR disabled 13 TOER 0 14 TOCR 15 TMDR RPWM 16 TOER 1 17 PFC MTU2 18 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 9 129 Error Occurrence in Normal Mode Recovery in Reset Synchronized PWM Mode 1 to 13 are the same as in figure 9 124 14 Select th...

Page 377: ... to 15 High Z High Z Figure 9 130 Error Occurrence in PWM Mode 1 Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Set PWM mode 1 3 For channels 3 and 4 enable output with TOER before initializing the pins with TIOR 4 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence In PWM mode 1 the...

Page 378: ...TOER 1 5 PFC MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized TIOC B n 0 to 15 High Z High Z Figure 9 131 Error Occurrence in PWM Mode 1 Recovery in PWM Mode 1 1 to 10 are the same as in figure 9 130 11 Not necessary when r...

Page 379: ...TR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM2 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized cycle register n 0 to 15 High Z High Z Figure 9 132 Error Occurrence in PWM Mode 1 Recovery in PWM Mode 2 1 to 10 are the same as in figure 9 130 11 Set PWM mode 2 12 Initialize the pins with TIOR In PWM...

Page 380: ...ER 1 5 PFC MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 9 133 Error Occurrence in PWM Mode 1 Recovery in Phase Counting Mode 1 to 10 are the same as in figure 9 130 11 Set phase counting mode 12 Initialize...

Page 381: ...R 1 18 PFC MTU2 19 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 9 134 Error Occurrence in PWM Mode 1 Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9 130 11 Set normal mode for initialization of the normal mode waveform generation section 12 Initialize the PWM mode 1 waveform ...

Page 382: ...7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TIOR 0 init 0 out 13 TIOR disabled 14 TOER 0 15 TOCR 16 TMDR RPWM 17 TOER 1 18 PFC MTU2 19 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 9 135 Error Occurrence in PWM Mode 1 Recovery in Reset Synchronized PWM Mode 1 to 14 are the same as ...

Page 383: ...cle register n 0 to 15 High Z High Z Figure 9 136 Error Occurrence in PWM Mode 2 Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Set PWM mode 2 3 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence In PWM mode 2 the cycle register pins are not initialized In the example TIOC A is the ...

Page 384: ...T 2 TMDR PWM2 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized cycle register n 0 to 15 High Z High Z Figure 9 137 Error Occurrence in PWM Mode 2 Recovery in PWM Mode 1 1 to 9 are the same as in figure 9 136 10 Set PWM...

Page 385: ...init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized cycle register Not initialized cycle register n 0 to 15 High Z High Z Figure 9 138 Error Occurrence in PWM Mode 2 Recovery in PWM Mode 2 1 to 9 are the same as in figure 9 136 10 Not necessary when res...

Page 386: ...ounting mode after re setting 1 RESET 2 TMDR PWM2 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized cycle register n 0 to 15 High Z High Z Figure 9 139 Error Occurrence in PWM Mode 2 Recovery in Phase Counting Mode 1 to 9 are the same as in fi...

Page 387: ...dule output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 9 140 Error Occurrence in Phase Counting Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Set phase counting mode 3 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence 4 Set MTU2 output with the PFC 5 The...

Page 388: ...er re setting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 9 141 Error Occurrence in Phase Counting Mode Recovery in PWM Mode 1 1 to 9 are the same as in figure 9 140 10 Set PWM mo...

Page 389: ...tting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Not initialized cycle register Figure 9 142 Error Occurrence in Phase Counting Mode Recovery in PWM Mode 2 1 to 9 are the same as in figure 9 140 10 Set PWM mo...

Page 390: ...hase counting mode after re setting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 9 143 Error Occurrence in Phase Counting Mode Recovery in Phase Counting Mode 1 to 9 are the same as in figure 9 140 10 Not...

Page 391: ...igh Z High Z Figure 9 144 Error Occurrence in Complementary PWM Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Select the complementary PWM output level and cyclic output enabling disabling with TOCR 3 Set complementary PWM 4 Enable channel 3 and 4 output with TOER 5 Set MTU2 output with the PFC 6 The count operation is started by TSTR 7...

Page 392: ...TOCR 3 TMDR CPWM 5 PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 9 145 Error Occurrence in Complementary PWM Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 9 144 11 ...

Page 393: ...etting when operation is restarted using the cycle and duty settings at the time the counter was stopped 1 RESET 2 TOCR 3 TMDR CPWM 5 PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC MTU2 12 TSTR 1 13 Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 9 146 Error Occurrence in Complementary PWM Mode Recovery in Complement...

Page 394: ...C MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TOER 0 13 TOCR 14 TMDR CPWM 15 TOER 1 16 PFC MTU2 17 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 9 147 Error Occurrence in Complementary PWM Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9 144 11 Set normal mode and make new sett...

Page 395: ...atch 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TOER 0 13 TOCR 14 TMDR RPWM 15 TOER 1 16 PFC MTU2 17 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 9 148 Error Occurrence in Complementary PWM Mode Recovery in Reset Synchronized PWM Mode 1 to 10 are the same as in figure 9 144 11 Set normal mode MTU2 output goes low 12 Disable channel ...

Page 396: ... Occurrence in Reset Synchronized PWM Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Select the reset synchronized PWM output level and cyclic output enabling disabling with TOCR 3 Set reset synchronized PWM 4 Enable channel 3 and 4 output with TOER 5 Set MTU2 output with the PFC 6 The count operation is started by TSTR 7 The reset synch...

Page 397: ...C MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 9 150 Error Occurrence in Reset Synchronized PWM Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 9 149 11 Set PWM mode 1 M...

Page 398: ...ER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TOER 0 12 TOCR 13 TMDR CPWM 14 TOER 1 15 PFC MTU2 16 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 9 151 Error Occurrence in Reset Synchronized PWM Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9 149 11 Disable channel 3 and 4 output with TOER 12 Select the...

Page 399: ...in reset synchronized PWM mode after re setting 1 RESET 2 TOCR 3 TMDR RPWM 5 PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC MTU2 12 TSTR 1 13 Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z High Z High Z High Z Figure 9 152 Error Occurrence in Reset Synchronized PWM Mode Recovery in Reset Synchronized PWM Mode 1 to 10 are t...

Page 400: ...Section 9 Multi Function Timer Pulse Unit 2 MTU2 Rev 3 00 Sep 27 2007 Page 380 of 758 REJ09B0243 0300 ...

Page 401: ...and the pins for channel 0 of the MTU2 can be placed in high impedance state by POE0 POE1 POE3 and POE8 pin falling edge or low level sampling High current pins can be placed in high impedance state when the high current pin output levels are compared and simultaneous active level output continues for one cycle or more High current pins and the pins for channel 0 of the MTU2 can be placed in high ...

Page 402: ...ut level comparison circuit OCSR1 ICSR1 Output level comparison circuit Output level comparison circuit Input level detection circuit Falling edge detection circuit Low level sampling circuit POE3 POE1 POE0 ICSR3 Input level detection circuit Falling edge detection circuit Low level sampling circuit POE8 Pφ 8 Pφ Pφ 16 Pφ 128 TIOC3D High impedance request signal for MTU2 high current pins High impe...

Page 403: ...ws output level comparisons with pin combinations Table 10 2 Pin Combinations Pin Combination I O Description PE9 TIOC3B and PE11 TIOC3D PE12 TIOC4A and PE14 TIOC4C PE13 TIOC4B and PE15 TIOC4D Output The high current pins for the MTU2 are placed in high impedance state when the pins simultaneously output an active level low level when the output level select P OLSP bit of the timer output control ...

Page 404: ...ation Register Name Abbrevia tion R W Initial Value Address Access Size Input level control status register 1 ICSR1 R W H 0000 H FFFFD000 8 16 32 Output level control status register 1 OCSR1 R W H 0000 H FFFFD002 8 16 Input level control status register 3 ICSR3 R W H 0000 H FFFFD008 8 16 32 Software port output enable register SPOER R W H 00 H FFFFD00A 8 Port output enable control register 1 POECR...

Page 405: ...d way Can be modified only once after a power on reset 1 2 POE3F POE1F POE0F PIE1 POE3M 1 0 POE1M 1 0 POE0M 1 0 Bit Bit Name Initial value R W Description 15 POE3F 0 R W 1 POE3 Flag Supported only by the SH7125 This flag indicates that a high impedance request has been input to the POE3 pin Clearing conditions By writing 0 to POE3F after reading POE3F 1 when the falling edge is selected by bits 7 ...

Page 406: ... is selected by bits 3 and 2 in ICSR1 Setting condition When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin 12 POE0F 0 R W 1 POE0 Flag This flag indicates that a high impedance request has been input to the POE0 pin Clearing conditions By writing 0 to POE0F after reading POE0F 1 when the falling edge is selected by bits 1 and 0 in ICSR1 By writing 0 to POE0F after reading POE0F 1 after...

Page 407: ...n sampled for 16 Pφ 8 clock pulses and all are low level 10 Accept request when POE3 input has been sampled for 16 Pφ 16 clock pulses and all are low level 11 Accept request when POE3 input has been sampled for 16 Pφ 128 clock pulses and all are low level 5 4 All 0 R W 2 Reserved These bits are always read as 0 The write value should always be 0 3 2 POE1M 1 0 00 R W 2 POE1 mode 1 0 These bits sele...

Page 408: ... power on reset 10 3 2 Output Level Control Status Register 1 OCSR1 OCSR1 is a 16 bit readable writable register that controls the enable disable of both output level comparison and interrupts and indicates status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R R R R R R R R Bit Initial value R W R W 1 R W 2 OSF1 OCE1 OIE1 Notes Writing 0 to this bit after rea...

Page 409: ...0 Interrupt requests disabled 1 Interrupt requests enabled 7 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Notes 1 Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way 2 Can be modified only once after a power on reset 10 3 3 Input Level Control Status Register 3 ICSR3 ICSR3 is a 16 bit readable writable register that se...

Page 410: ...16 or Pf 128 clock when low level sampling is selected by bits 1 and 0 in ICSR3 Setting condition When the input condition set by bits 1 and 0 in ICSR3 occurs at the POE8 pin 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 POE8E 0 R W 2 POE8 High Impedance Enable This bit specifies whether to place the pins in high impedance state when the POE8F bit in I...

Page 411: ...lses and all are low level 11 Accept request when POE8 input has been sampled for 16 Pφ 128 clock pulses and all are low level Notes 1 Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way 2 Can be modified only once after a power on reset 10 3 4 Software Port Output Enable Register SPOER SPOER is an 8 bit readable writable register that controls high impedance st...

Page 412: ...ions Power on reset By writing 0 to MTU2CH0HIZ after reading MTU2CH0HIZ 1 1 Places the pins in high impedance state Setting condition By writing 1 to MTU2CH0HIZ 0 MTU2CH34HIZ 0 R W MTU2 Channel 3 and 4 Output High Impedance This bit specifies whether to place the high current pins for the MTU2 in high impedance state 0 Does not place the pins in high impedance state Clearing conditions Power on re...

Page 413: ...s whether to place the PE3 TIOC1D pin for channel 0 in the MTU2 in high impedance state when either POE8F or MTU2CH0HIZ bit is set to 1 0 Does not place the pin in high impedance state 1 Places the pin in high impedance state 2 MTU2PE2ZE 0 R W MTU2 PE2 High Impedance Enable This bit specifies whether to place the PE2 TIOC1C pin for channel 0 in the MTU2 in high impedance state when either POE8F or...

Page 414: ...al value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 R R W R W R W R R W R W R W R R R R R R R R Note Can be modified only once after a power on reset MTU2 P1CZE MTU2 P2CZE MTU2 P3CZE Bit Bit Name Initial value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 MTU2P1CZE 1 R W MTU2 Port 1 Output Comparison High Impedance...

Page 415: ...ce state 12 MTU2P3CZE 1 R W MTU2 Port 3 Output Comparison High Impedance Enable This bit specifies whether to compare output levels for the MTU2 high current PE13 TIOC4B and PE15 TIOC4D pins and to place them in high impedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F POE1F POE3F and MTU2CH34HIZ bits is set to 1 0 Does not compare output levels or pla...

Page 416: ...E MTU2CH0HIZ MTU2 channel 0 pin PE1 TIOC0B Input level detection or SPOER setting MTU2PE1ZE POE8F POE8E MTU2CH0HIZ MTU2 channel 0 pin PE2 TIOC0C Input level detection or SPOER setting MTU2PE2ZE POE8F POE8E MTU2CH0HIZ MTU2 channel 0 pin PE3 TIOC0D Input level detection or SPOER setting MTU2PE3ZE POE8F POE8E MTU2CH0HIZ 10 4 1 Input Level Detection Operation If the input conditions set by ICSR1 occur...

Page 417: ...ling clock selected by ICSR1 If even one high level is detected during this interval the low level is not accepted The timing when the high current pins enter the high impedance state after the sampling clock is input is the same in both falling edge detection and in low level detection Pφ Sampling clock 3 POE input PE9 TIOC3B When low level is sampled at all points When high level is sampled at l...

Page 418: ...h a power on reset or by clearing all of the flags in bits 12 to 15 POE0F to POE3F and POE8F in ICSR1 However note that when low level sampling is selected by bits 0 to 7 in ICSR1 just writing 0 to a flag is ignored the flag is not cleared flags can be cleared by writing 0 to it only after a high level is input to the POE pin and is sampled High current pins that have entered high impedance state ...

Page 419: ...ed condition is satisfied during input level detection or output level comparison Table 10 5 shows the interrupt sources and their conditions Table 10 5 Interrupt Sources and Conditions Name Interrupt Source Interrupt Flag Condition OEI1 Output enable interrupt 1 POE3F POE1F POE0F and OSF1 PIE1 POE3F POE1F POE0F OIE1 OSF1 OEI3 Output enable interrupt 2 POE8F PIE3 POE8F ...

Page 420: ... pin is placed in the output state for one cycle of the peripheral clock Pf after which the function is switched to general input This also occurs when a power on reset is issued from the WDT for pins that are being handled as high impedance due to short circuit detection by the MTU2 Figure 10 5 shows the state of a pin for which the POE input has selected high impedance handling with the timer ou...

Page 421: ...earing software standby mode It can also be used as an interval timer 11 1 Features Can be used to ensure the clock settling time Use the WDT to revoke software standby mode Can switch between watchdog timer mode and interval timer mode Generates internal resets in watchdog timer mode Internal resets occur after counter overflow An interrupt is generated in interval timer mode An interval timer in...

Page 422: ...ontrol Bus interface WTCNT Divider Clock selector Internal bus Clock Standby mode Peripheral clock Pφ Standby cancellation Reset control Clock selection WDT Overflow WDTOVF Internal reset request Interrupt control Interrupt request Legend WTCSR WTCNT Watchdog timer control status register Watchdog timer counter Figure 11 1 Block Diagram of WDT ...

Page 423: ...1 1 lists the WDT pin configuration Table 11 1 WDT Pin Configuration Pin Name Abbreviation I O Description Watchdog timer overflow WDTOVF Output When an overflow occurs in watchdog timer mode an internal reset is generated and this pin outputs the low level for one clock cycle specified by the CKS2 to CKS0 bits in WTCSR ...

Page 424: ...3 1 Watchdog Timer Counter WTCNT WTCNT is an 8 bit readable writable register that increments on the selected clock When an overflow occurs it generates a reset in watchdog timer mode and an interrupt in interval time mode The WTCNT counter is not initialized by an internal reset due to the WDT overflow The WTCNT counter is initialized to H 00 only by a power on reset using the RES pin Use a word ...

Page 425: ...the upper byte Use a byte access to read WTCSR Note WTCSR differs from other registers in that it is more difficult to write to See section 11 3 3 Notes on Register Access for details Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W TME WT IT RSTS WOVF IOVF CKS 2 0 Bit Bit Name Initial Value R W Description 7 TME 0 R W Timer Enable Starts and stops timer operat...

Page 426: ...WTCNT has overflowed in interval timer mode This bit is not set in watchdog timer mode 0 No overflow 1 WTCNT has overflowed in interval timer mode 2 to 0 CKS 2 0 000 R W Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock Pφ The overflow period that is shown inside the parenthesis in the table is the value ...

Page 427: ...ers must be written by a word transfer instruction They cannot be written by a byte or longword transfer instruction When writing to WTCNT set the upper byte to H 5A and transfer the lower byte as the write data as shown in figure 11 2 When writing to WTCSR set the upper byte to H A5 and transfer the lower byte as the write data This transfer procedure writes the lower byte data to WTCNT or WTCSR ...

Page 428: ...WDT starts counting by detecting a change in the level input to the NMI or IRQ pin 5 When the WDT count overflows the CPG starts supplying the clock and the LSI resumes operation The WOVF flag in WTCSR is not set when this happens 11 4 2 Using Watchdog Timer Mode While operating in watchdog timer mode the WDT generates an internal reset of the type specified by the RSTS bit in WTCSR and asserts a ...

Page 429: ...imer Mode When WTCNT Count Clock is Specified to Pφ 32 by CKS2 to CKS0 11 4 3 Using Interval Timer Mode When operating in interval timer mode interval timer interrupts are generated at every overflow of the counter This enables interrupts to be generated at set periods 1 Clear the WT IT bit in WTCSR to 0 set the type of count clock in the CKS2 to CKS0 bits and set the initial value of the counter ...

Page 430: ...et to H FF in interval timer mode overflow does not occur when WTCNT reaches the immediate H 00 but occurs when WTCNT changes from H FF to H 00 after 257 cycles of count clock Whereas if WTCNT is set to H FF in watchdog timer mode overflow occurs when WTCNT changes from H FF to H 00 after one cycle of count clock ...

Page 431: ...any other communications chip that employs a standard asynchronous serial system There are twelve selectable serial data communication formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd or none Multiprocessor communications Receive error detection Parity overrun and framing errors Break detection Break is detected by reading the RXD pin level directly when a framing error ...

Page 432: ...ister Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Serial direction control register Internal data bus Pφ SCRDR Module data bus SCTDR SCRSR SCTSR SCSSR SCSMR SCSPTR SCSCR SCSDCR SCBRR Transmission reception control Baud rate generator Clock TEI TXI RXI ERI External clo...

Page 433: ...I0 receive data input TXD0 Output SCI0 transmit data output 1 SCK1 2 I O SCI1 clock input output RXD1 Input SCI1 receive data input TXD1 Output SCI1 transmit data output 2 SCK2 I O SCI2 clock input output RXD2 Input SCI2 receive data input TXD2 Output SCI2 transmit data output Notes 1 Pin names SCK RXD and TXD are used in the description for all channels omitting the channel designation 2 This pin...

Page 434: ... SCSDCR_0 R W H F2 H FFFFC00C 8 Serial port register_0 SCSPTR_0 R W H 01 H FFFFC00E 8 1 Serial mode register_1 SCSMR_1 R W H 00 H FFFFC080 8 Bit rate register_1 SCBRR_1 R W H FF H FFFFC082 8 Serial control register_1 SCSCR_1 R W H 00 H FFFFC084 8 Transmit data register_1 SCTDR_1 H FFFFC086 8 Serial status register_1 SCSSR_1 R W H 84 H FFFFC088 8 Receive data register_1 SCRDR_1 H FFFFC08A 8 Serial ...

Page 435: ...to SCRDR for storage and completes operation After that SCRSR is ready to receive data Since SCRSR and SCRDR work as a double buffer in this way data can be received continuously SCRDR is a read only register and cannot be written to by the CPU Bit Initial value R W 7 6 5 4 3 2 1 0 R R R R R R R R 12 3 3 Transmit Shift Register SCTSR SCTSR transmits serial data The SCI loads transmit data from the...

Page 436: ...ly SCTDR can always be written or read to by the CPU Bit Initial value R W 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W 12 3 5 Serial Mode Register SCSMR SCSMR is an 8 bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator The CPU can always read and write to SCSMR Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W...

Page 437: ...epending on the parity mode O E setting Receive data parity is checked according to the even odd O E mode setting 4 O E 0 R W Parity mode Selects even or odd parity when parity bits are added and checked The O E setting is used only in asynchronous mode and only when the parity enable bit PE is set to 1 to enable parity addition and checking The O E setting is ignored in clock synchronous mode or ...

Page 438: ... start bit of the next incoming character Notes 1 When transmitting a single 1 bit is added at the end of each transmitted character 2 When transmitting two 1 bits are added at the end of each transmitted character 2 MP 0 R W Multiprocessor Mode only in asynchronous mode Enables or disables multiprocessor mode The PE and O E bit settings are ignored in multiprocessor mode 0 Multiprocessor mode dis...

Page 439: ... transmit shift register SCTSR TXI can be canceled by clearing the TDRE flag to 0 after reading TDRE 1 or by clearing the TIE bit to 0 0 Transmit data empty interrupt request TXI is disabled 1 Transmit data empty interrupt request TXI is enabled 6 RIE 0 R W Receive Interrupt Enable Enables or disables a receive data full interrupt RXI and a receive error interrupt ERI to be issued when the RDRF fl...

Page 440: ...eiver disabled 1 1 Receiver enabled 2 Notes 1 Clearing RE to 0 does not affect the receive flags RDRF FER PER and ORER These flags retain their previous values 2 Serial reception starts when a start bit is detected in asynchronous mode or synchronous clock input is detected in clock synchronous mode Select the receive format in SCSMR before setting RE to 1 3 MPIE 0 R W Multiprocessor Interrupt Ena...

Page 441: ...ination of CKE1 and CKE0 the SCK pin can be used for serial clock output or serial clock input When selecting the clock output in clock synchronous mode set the C A bit in SCSMR to 1 and then set bits CKE1 and CKE0 For details on clock source selection see table 12 14 in section 12 4 Operation Asynchronous mode 00 Internal clock SCK pin used for input pin The input signal is ignored 01 Internal cl...

Page 442: ...E RDRF ORER FER PER TEND MPB MPBT Note Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way Bit Bit Name Initial value R W Description 7 TDRE 1 R W Transmit Data Register Empty Indicates whether data has been transferred from the transmit data register SCTDR to the transmit shift register SCTSR and SCTDR has become ready to be written with next serial transmit da...

Page 443: ... standby mode When 0 is written to RDRF after reading RDRF 1 1 Indicates that valid received data is stored in SCRDR Setting condition When serial reception ends normally and receive data is transferred from SCRSR to SCRDR Note SCRDR and the RDRF flag are not affected and retain their previous states even if an error is detected during data reception or if the RE bit in the serial control register...

Page 444: ...ing conditions By a power on reset or in standby mode When 0 is written to ORER after reading ORER 1 1 Indicates that an overrun error occurred during reception 2 Setting condition When the next serial reception is completed while RDRF 1 Notes 1 The ORER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0 2 The receive data prior to the overrun error is ret...

Page 445: ...hen 0 is written to FER after reading FER 1 1 Indicates that a framing error occurred during reception Setting condition When the SCI founds that the stop bit at the end of the received data is 0 after completing reception 2 Notes 1 The FER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0 2 In 2 stop bit mode only the first stop bit is checked for a valu...

Page 446: ...n reset or in standby mode When 0 is written to PER after reading PER 1 1 Indicates that a parity error occurred during reception 2 Setting condition When the number of 1s in the received data and parity does not match the even or odd parity specified by the O E bit in the serial mode register SCSMR Notes 1 The PER flag is not affected and retains its previous value when the RE bit in SCSCR is cle...

Page 447: ... is written to TDRE after reading TDRE 1 1 Indicates that transmission has ended Setting conditions By a power on reset or in standby mode When the TE bit in SCSCR is 0 When TDRE 1 during transmission of the last bit of a 1 byte serial transmit character 1 MPB 0 R Multiprocessor Bit Stores the multiprocessor bit found in the receive data When the RE bit in SCSCR is cleared to 0 its previous state ...

Page 448: ...T SPB0DT Bit Bit Name Initial value R W Description 7 EIO 0 R W Error Interrupt Only Enables or disables RXI interrupts While the EIO bit is set to 1 the SCI does not request an RXI interrupt to the CPU even if the RIE bit is set to 1 0 The RIE bit enables or disables RXI and ERI interrupts While the RIE bit is 1 RXI and ERI interrupts are sent to the INTC 1 While the RIE bit is 1 only the ERI int...

Page 449: ...it value is output through the SCK pin 0 Low level is output 1 High level is output 1 0 Reserved This bit is always read as 0 The write value should always be 0 0 SPB0DT 1 W Serial Port Break Data Controls the TXD pins together with the TE bit in SCSCR This bit is write only bit Undefined value is read However the TXD pin function should be selected with the Pin Function Controller PFC Setting val...

Page 450: ...W Description 7 to 4 All 1 R Reserved These bits are always read as 1 The write value should always be 1 3 DIR 0 R W Data Transfer Direction Selects the serial parallel conversion format Valid for an 8 bit transmit receive format 0 SCTDR contents are transmitted in LSB first order Receive data is stored in SCRDR in LSB first 1 SCTDR contents are transmitted in MSB first order Receive data is store...

Page 451: ...The CPU can always read and write to SCBRR The SCBRR setting is calculated as follows Bit Initial value R W 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Asynchronous mode N 106 1 64 22n 1 B Pφ Clock synchronous mode N 106 1 8 22n 1 B Pφ B Bit rate bits s N SCBRR setting for baud rate generator 0 N 255 The setting value should satisfy the electrical characteristics Pφ Operating f...

Page 452: ...p 27 2007 Page 432 of 758 REJ09B0243 0300 Table 12 3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0 0 Pφ 0 0 1 Pφ 4 0 1 2 Pφ 16 1 0 3 Pφ 64 1 1 Note The bit rate error in asynchronous is given by the following formula Error 1 100 N 1 B 64 22n 1 Pφ 106 ...

Page 453: ... 3 64 0 16 300 2 64 0 16 2 77 0 16 2 90 0 16 2 103 0 16 2 116 0 16 2 129 0 16 600 1 129 0 16 1 155 0 16 1 181 0 16 1 207 0 16 1 233 0 16 2 64 0 16 1200 1 64 0 16 1 77 0 16 1 90 0 16 1 103 0 16 1 116 0 16 1 129 0 16 2400 0 129 0 16 0 155 0 16 0 181 0 16 0 207 0 16 0 233 0 16 1 64 0 16 4800 0 64 0 16 0 77 0 16 0 90 0 16 0 103 0 16 0 116 0 16 0 129 0 16 9600 0 32 1 36 0 38 0 16 0 45 0 93 0 51 0 16 0 ...

Page 454: ...600 2 71 0 54 2 77 0 16 2 84 0 43 2 90 0 16 2 97 0 35 2 103 0 16 1200 1 142 0 16 1 155 0 16 1 168 0 16 1 181 0 16 1 194 0 16 1 207 0 16 2400 1 71 0 54 1 77 0 16 1 84 0 43 1 90 0 16 1 97 0 35 1 103 0 16 4800 0 142 0 16 0 155 0 16 0 168 0 16 0 181 0 16 0 194 0 16 0 207 0 16 9600 0 71 0 54 0 77 0 16 0 84 0 43 0 90 0 16 0 97 0 35 0 103 0 16 14400 0 47 0 54 0 51 0 16 0 55 0 76 0 60 0 39 0 64 0 16 0 68 ...

Page 455: ...29 0 16 300 2 220 0 16 2 233 0 16 2 246 0 16 3 64 0 16 600 2 110 0 29 2 116 0 16 2 123 0 24 2 129 0 16 1200 1 220 0 16 1 233 0 16 1 246 0 16 2 64 0 16 2400 1 110 0 29 1 116 0 16 1 123 0 24 1 129 0 16 4800 0 220 0 16 0 233 0 16 0 246 0 16 1 64 0 16 9600 0 110 0 29 0 116 0 16 0 123 0 24 0 129 0 16 14400 0 73 0 29 0 77 0 16 0 81 0 57 0 86 0 22 19200 0 54 0 62 0 58 0 69 0 61 0 24 0 64 0 16 28800 0 36 ...

Page 456: ... 3 187 3 218 3 249 500 3 77 3 93 3 108 3 124 3 140 3 155 1000 2 155 2 187 2 218 2 249 3 69 3 77 2500 1 249 2 74 2 87 2 99 2 112 2 124 5000 1 124 1 149 1 174 1 199 1 224 1 249 10000 0 249 1 74 1 87 1 99 1 112 1 124 25000 0 99 0 119 0 139 0 159 0 179 0 199 50000 0 49 0 59 0 69 0 79 0 89 0 99 100000 0 24 0 29 0 34 0 39 0 44 0 49 250000 0 9 0 11 0 13 0 15 0 17 0 19 500000 0 4 0 5 0 6 0 7 0 8 0 9 10000...

Page 457: ... 250 500 3 171 3 187 3 202 3 218 3 233 3 249 1000 3 85 3 93 3 101 3 108 3 116 3 124 2500 2 137 2 149 2 162 2 174 2 187 2 199 5000 2 68 2 74 2 80 2 87 2 93 2 99 10000 1 137 1 149 1 162 1 174 1 187 1 199 25000 0 219 0 239 1 64 1 69 1 74 1 79 50000 0 109 0 119 0 129 0 139 0 149 0 159 100000 0 54 0 59 0 64 0 69 0 74 0 79 250000 0 21 0 23 0 25 0 27 0 29 0 31 500000 0 10 0 11 0 12 0 13 0 14 0 15 1000000...

Page 458: ... 147 3 155 2500 2 212 2 224 2 237 2 249 5000 2 105 2 112 2 118 2 124 10000 1 212 1 224 1 237 1 249 25000 1 84 1 89 1 94 1 99 50000 0 169 0 179 0 189 0 199 100000 0 84 0 89 0 94 0 99 250000 0 33 0 35 0 37 0 39 500000 0 16 0 17 0 18 0 19 1000000 0 8 0 9 2500000 0 3 5000000 0 1 Legend Blank No setting possible Setting possible but error occurs Continuous transmission reception is disabled Note Settin...

Page 459: ... 12 list the maximum rates for external clock input Table 12 10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pφ MHz Maximum Bit Rate bits s n N 10 312500 0 0 12 375000 0 0 14 437500 0 0 16 500000 0 0 18 562500 0 0 20 625000 0 0 22 687500 0 0 24 750000 0 0 26 812500 0 0 28 875000 0 0 30 937500 0 0 32 1000000 0 0 34 1062500 0 0 36 1125000 0 0 38 11875...

Page 460: ...nput Asynchronous Mode Pφ MHz External Input Clock MHz Maximum Bit Rate bits s 10 2 5000 156250 12 3 0000 187500 14 3 5000 218750 16 4 0000 250000 18 4 5000 281250 20 5 0000 312500 22 5 5000 343750 24 6 0000 375000 26 6 5000 406250 28 7 0000 437500 30 7 5000 468750 32 8 0000 500000 34 8 5000 531250 36 9 0000 562500 38 9 5000 593750 40 10 0000 625000 ...

Page 461: ...e Pφ MHz External Input Clock MHz Maximum Bit Rate bits s 10 1 6667 1666666 7 12 2 0000 2000000 0 14 2 3333 2333333 3 16 2 6667 2666666 7 18 3 0000 3000000 0 20 3 3333 3333333 3 22 3 6667 3666666 7 24 4 0000 4000000 0 26 4 3333 4333333 3 28 4 6667 4666666 7 30 5 0000 5000000 0 32 5 3333 5333333 3 34 5 6667 5666666 7 36 6 0000 6000000 0 38 6 3333 6333333 3 40 6 6667 6666666 7 ...

Page 462: ...s the communication format and character length In receiving it is possible to detect framing errors parity errors overrun errors and breaks An internal or external clock can be selected as the SCI clock source When an internal clock is selected the SCI operates using the clock supplied by the on chip baud rate generator and can output a clock with a frequency 16 times the bit rate When an externa...

Page 463: ...ot set 1 bit 1 2 bits 1 0 Set 1 bit 1 Asynchronous 2 bits 1 x x x Clock synchronous 8 bit Not set None Legend x Don t care Table 12 14 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR SCSCR Settings Bit 7 C A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use the SCK pin 1 Clock with a frequency 16 times the bit rate is output 1 0 1 E...

Page 464: ...munication the communication line is normally held in the mark high state The SCI monitors the line and starts serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first parity bit high or low and stop bit high in that order When receiving in asynchronous mode the SCI synchronizes at the falling edge of the ...

Page 465: ...0 0 1 1 0 0 1 1 x x x x S 8 bit data STOP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 SCSMR Settings 1 2 3 4 5 6 7 8 9 10 11 12 Serial Transfer Format and Fra...

Page 466: ...f this output clock is equal to 16 times the desired bit rate 3 Transmitting and Receiving Data SCI Initialization Asynchronous Mode Before transmitting or receiving clear the TE and RE bits to 0 in the serial control register SCSCR then initialize the SCI as follows When changing the operation mode or the communication format always clear the TE and RE bits to 0 before following the procedure giv...

Page 467: ...output setting 5 Set the TE bit or RE bit in SCSCR to 1 Also make settings of the RIE TIE TEIE and MPIE bits At this time the TXD RXD and SCK pins are ready to be used The TXD pin is in a mark state during transmitting and RXD pin is in an idle state for waiting the start bit during receiving Set the PFC for the external pins to be used SCK TXD RXD Set TE and RE bits of SCSCR to 1 Set the RIE TIE ...

Page 468: ... and set SPB0IO to 1 Clear TE bit in SCSCR to 0 End of transmission No Yes No Yes No Yes No Yes 1 SCI status check and transmit data write Read SCSSR and check that the TDRE flag is set to 1 then write transmit data to SCTDR and clear the TDRE flag to 0 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then wr...

Page 469: ...e following order A Start bit One bit 0 is output B Transmit data 8 bit or 7 bit data is output in LSB first order C Parity bit or multiprocessor bit One parity bit even or odd parity or one multiprocessor bit is output A format in which neither parity nor multiprocessor bit is output can also be selected D Stop bit s One or two 1 bits stop bits are output E Mark state 1 is output continuously unt...

Page 470: ...0 1 1 0 D0 D1 D7 0 1 1 1 TDRE TEND Serial data Start bit Data Parity bit Stop bit Start bit Idle state mark state Data Parity bit Stop bit TXI interrupt request Data written to SCTDR and TDRE flag cleared to 0 by TXI interrupt handler One frame TXI interrupt request TEI interrupt request Figure 12 5 Example of Transmission in Asynchronous Mode 8 Bit Data Parity One Stop Bit ...

Page 471: ...dling 1 Receive error handling and break detection If a receive error occurs read the ORER PER and FER flags in SCSSR to identify the error After performing the appropriate error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can also be detected by reading the value of the...

Page 472: ...9B0243 0300 End Error processing Parity error processing Yes No Clear ORER PER and FER flags in SCSSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in SCSCR to 0 Figure 12 6 Sample Flowchart for Receiving Serial Data cont ...

Page 473: ... passed the RDRF flag is set to 1 and the received data is stored in SCRDR If a receive error is detected the SCI operates as shown in table 12 16 Note When a receive error occurs subsequent reception cannot be continued In addition the RDRF flag will not be set to 1 after reception be sure to clear the error flag to 0 4 If the EIO bit in SCSPTR is cleared to 0 and the RIE bit in SCSCR is set to 1...

Page 474: ...clock synchronous mode the SCIF transmits and receives data in synchronization with clock pulses This mode is suitable for high speed serial communication The SCI transmitter and receiver are independent so full duplex communication is possible while sharing the same clock Both the transmitter and receiver have a double buffered structure so that data can be read or written during transmission or ...

Page 475: ...14 When the SCI operates on an internal clock it outputs the clock signal at the SCK pin Eight clock pulses are output per transmitted or received character When the SCI is not transmitting or receiving the clock signal remains in the high state When only reception is performed the synchronous clock continues to be output until an overrun error occurs or the RE bit is cleared to 0 For the receptio...

Page 476: ...r RE bit in SCR to 1 Also make settings of the RIE TIE TEIE and MPIE bits At this time the TXD RXD and SCK pins are ready to be used The TXD pin is in a mark state during transmitting When synchronous clock output clock master is set during receiving in clock synchronous mode outputting clocks from the SCK pin starts Note In simultaneous transmit and receive operations the TE and RE bits should bo...

Page 477: ...ata to SCTDR and clear TDRE flag in SCSSR to 0 All data transmitted Read TEND flag in SCSSR TEND 1 Clear TE bit in SCSCR to 0 End of transmission No Yes No Yes No Yes 1 SCI status check and transmit data write Read SCSSR and check that the TDRE flag is set to 1 then write transmit data to SCTDR and clear the TDRE flag to 0 2 Serial transmission continuation procedure To continue serial transmissio...

Page 478: ... selected the SCI outputs data in synchronization with the input clock Data is output from the TXD pin in order from the LSB bit 0 to the MSB bit 7 3 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is 0 the data is transferred from SCTDR to SCTSR and serial transmission of the next frame is started If the TDRE flag is 1 the TEND flag in SCSSR is set to 1 the M...

Page 479: ...data in SCRDR and clear RDRF flag in SCSSR to 0 All data received Clear RE bit in SCSCR to 0 End of reception Yes No Yes Yes No No Error handling 1 Receive error handling Read the ORER flag in SCSSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Reception cannot be resumed while the ORER flag is set to 1 2 SCI status check and receive data read Read SCSS...

Page 480: ...cks whether the RDRF flag is 0 and the receive data can be transferred from SCRSR to SCRDR If this check is passed the SCI sets the RDRF flag to 1 and stores the received data in SCRDR If a receive error is detected the SCI operates as shown in table 12 16 In this state subsequent reception cannot be continued In addition the RDRF flag will not be set to 1 after reception be sure to clear the RDRF...

Page 481: ...I interrupt handler RDRF ORER RXI interrupt request RXI interrupt request One frame ERI interrupt request by overrun error Transfer direction Figure 12 13 Example of SCI Receive Operation Transmitting and Receiving Serial Data Simultaneously Clock Synchronous Mode Figure 12 14 shows a sample flowchart for transmitting and receiving serial data simultaneously Use the following procedure for serial ...

Page 482: ...us check and receive data read Read SCSSR and check that the RDRF flag is set to 1 then read the receive data in SCRDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt 4 Serial transmission reception continuation procedure To continue serial transmission reception before the MSB bit 7 of the current frame is received finish reading the...

Page 483: ...station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0 multiprocessor bit added The receiving station skips data until data with a 1 multiprocessor bit is sent When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose ID matches then receive...

Page 484: ...ng station C ID 03 Receiving station D ID 04 Serial transmission line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 12 15 Example of Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A ...

Page 485: ...bled However data is not transmitted 2 SCI status check and transmit data write Read SCSSR and check that the TDRE flag is set to 1 then write transmit data to SCTDR Set the MPBT bit in SCSSR to 0 or 1 Finally clear the TDRE flag to 0 After initializing the SCI when an ID is written to SCTDR register so as to transmit the ID data is immediately transferred and then the TDER flag is set to 1 The MP...

Page 486: ...ata1 MPB Stop bit Data ID2 Start bit Stop bit Start bit Data Data2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine If not this station s ID MPIE bit is set to 1 again RXI interrupt request is not generated and SCRDR retains its state ID1 a Data does not match station s ID MPI...

Page 487: ...on and comparison Read SCSSR and check that the RDRF flag is set to 1 then read the receive data in SCRDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 4 SCI status check and data reception Read SCSSR and check that the RDRF flag is set to 1 then read the ...

Page 488: ...e 468 of 758 REJ09B0243 0300 End Error processing Yes No Clear ORER and FER flags in SCSSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCSCR to 0 5 Figure 12 18 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 489: ...TDRE flag in the serial status register SCSSR is set to 1 a TDR empty interrupt request is generated When the RDRF flag in SCSSR is set to 1 an RDR full interrupt request is generated When the ORER FER or PER flag in SCSSR is set to 1 an ERI interrupt request is generated When the TEND flag in SCSSR is set to 1 a TEI interrupt request is generated The TXI interrupt indicates that transmit data can...

Page 490: ...SCK pin according to the settings of the C A bit in SCSMR and bits CKE1 and CKE0 in SCSCR Reset Internal data bus Clock output enable signal Serial clock output signal Serial clock input signal Serial input enable signal Bit 3 Bit 2 Reset Q D R SCKIO SCK C Q D R SCKDT SPTRW SPTRW C Figure 12 19 SPB1IO bit SPB1DT bit and SCK Pin SPTRW SCSPTR write Internal data bus Transmit enable signal Bit 0 Rese...

Page 491: ...at the TDRE flag is set to 1 12 7 2 Multiple Receive Error Occurrence If multiple receive errors occur at the same time the status flags in SCSSR are set as shown in table 12 18 When an overrun error occurs data is not transferred from the receive shift register SCRSR to the receive data register SCRDR and the received data will be lost Table 12 18 SCSSR Status Flag Values and Transfer of Received...

Page 492: ...al Until TE bit is set to 1 enabling transmission after initializing TXD pin does not work During the period mark status is performed by SPB0DT bit Therefore the SPB0DT bit should be set to 1 high level output To send a break signal during serial transmission clear the SPB0DT bit to 0 low level then clear the TE bit to 0 halting transmission When the TE bit is cleared to 0 the transmitter is initi...

Page 493: ... Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1 Equation 1 M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N Where M Receive margin N Ratio of bit rate to clock N 16 D Clock duty D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equati...

Page 494: ...les of the peripheral operating clock after the SCK external clock is changed from 0 to 1 TE and RE must be set to 1 only while the SCK external clock is 1 12 7 7 Module Standby Mode Setting SCI operation can be disabled or enabled using the standby control register The initial setting is for SCI operation to be halted Register access is enabled by clearing module standby mode For details see sect...

Page 495: ...φ 25 MHz Three operating modes Single mode Single channel A D conversion Continuous scan mode Repetitive A D conversion on up to four channels Single cycle scan mode Continuous A D conversion on up to four channels Data registers Conversion results are held in a 16 bit data register for each channel Sample and hold function Three methods for conversion start Software Conversion start trigger from ...

Page 496: ... Bus interface Successive approximations register Multiplexer ADDRm ADDRn ADCSR ADTSR ADCR ANm ANn Legend ADCR A D control register ADCSR A D control status register ADTSR A D trigger select register ADDRm to ADDRn A D data registers m to n Note The register number corresponds to the channel number of the module m to n 0 to 7 ADTRG Conversion start trigger from MTU2 Pφ Pφ 2 Pφ 3 Pφ 4 AVCC AVSS Fig...

Page 497: ...nput Analog block power supply and reference voltage AVSS Input Analog block ground and reference voltage Common ADTRG Input A D external trigger input pin AN0 Input Analog input pin 0 AN1 Input Analog input pin 1 Group 0 AN2 Input Analog input pin 2 A D module 0 A D_0 AN3 Input Analog input pin 3 Group 1 AN4 Input Analog input pin 4 AN5 Input Analog input pin 5 Group 0 AN6 Input Analog input pin ...

Page 498: ...egister 1 ADDR1 R H 0000 H FFFFC902 16 A D data register 2 ADDR2 R H 0000 H FFFFC904 16 A D data register 3 ADDR3 R H 0000 H FFFFC906 16 A D control status register_0 ADCSR_0 R W H 0000 H FFFFC910 16 A D control register_0 ADCR_0 R W H 0000 H FFFFC912 16 A D data register 4 ADDR4 R H 0000 H FFFFC980 16 A D data register 5 ADDR5 R H 0000 H FFFFC982 16 A D data register 6 ADDR6 R H 0000 H FFFFC984 1...

Page 499: ...11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 3 2 A D Control Status Registers_0 and _1 ADCSR_0 and ADCSR_1 ADCSR for each module controls A D conversion operations Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R R R W R R W R W R W R W R W R W R W R W R W R W Note Writing 0 to this bit after readi...

Page 500: ...led When changing the operating mode first clear the ADST bit to 0 10 0 R Reserved This bit is always read as 0 The write value should always be 0 9 CONADF 0 R W ADF Control Controls setting of the ADF bit in 2 channel scan mode The setting of this bit is valid only when triggering of A D conversion is enabled TRGE 1 in 2 channel scan mode The setting of this bit is ignored in single mode or 4 cha...

Page 501: ... 4 01 Pφ 3 10 Pφ 2 11 Pφ When changing the A D conversion time first clear the ADST bit to 0 CKSL 1 0 B 11 can be set while Pφ 25 MHz 5 4 ADM 1 0 00 R W A D Mode 1 and 0 Select the A D conversion mode 00 Single mode 01 4 channel scan mode 10 Setting prohibited 11 2 channel scan mode When changing the operating mode first clear the ADST bit to 0 3 ADCS 0 R W A D Continuous Scan Selects either singl...

Page 502: ... R R R R R R R ADST Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 ADST 0 R W A D Start Starts or stops A D conversion When this bit is set to 1 A D conversion is started When this bit is cleared to 0 A D conversion is stopped and the A D converter enters the idle state In single or single cycle scan mode this...

Page 503: ...5 AN0 AN1 AN4 AN5 1 0 AN2 AN6 AN0 to AN2 AN4 to AN6 1 AN3 AN7 AN0 to AN3 AN4 to AN7 1 0 0 1 1 0 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Analog Input Channels Bit 2 Bit 1 Bit 0 2 Channel Scan Mode CH2 CH1 CH0 A D_0 A D_1 0 0 0 AN0 AN4 1 AN0 AN1 AN4 AN5 1 0 AN2 AN6 1 AN2 AN3 AN6 AN7 1 0 0 1 1 0 1 Setting prohibited Setting prohibited Notes Continuous scan mode o...

Page 504: ...A D Trigger 1 Group 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A D conversion for group 1 when A D module 1 is in 2 channel scan mode 0000 External trigger pin ADTRG input 0001 TRGA input capture compare match for each MTU2 channel or TCNT_4 underflow trough in complementary PWM mode TRGAN 0010 MTU2 channel 0 compare match TRG0N 0011 MTU2 A D conversion start request delay...

Page 505: ...nel or TCNT_4 underflow trough in complementary PWM mode TRGAN 0010 MTU2 channel 0 compare match TRG0N 0011 MTU2 A D conversion start request delaying TRG4AN 0100 MTU2 A D conversion start request delaying TRG4BN 0101 Setting prohibited 0110 Setting prohibited 0111 Setting prohibited 1xxx Setting prohibited When switching the selector first clear the ADST bit in the A D control register ADCR to 0 ...

Page 506: ...ach MTU2 channel or TCNT_4 underflow trough in complementary PWM mode TRGAN 0010 MTU2 channel 0 compare match TRG0N 0011 MTU2 A D conversion start request delaying TRG4AN 0100 MTU2 A D conversion start request delaying TRG4BN 0101 Setting prohibited 0110 Setting prohibited 0111 Setting prohibited 1xxx Setting prohibited When switching the selector first clear the ADST bit in the A D control regist...

Page 507: ...hannel or TCNT_4 underflow trough in complementary PWM mode TRGAN 0010 MTU2 channel 0 compare match TRG0N 0011 MTU2 A D conversion start request delaying TRG4AN 0100 MTU2 A D conversion start request delaying TRG4BN 0101 Setting prohibited 0110 Setting prohibited 0111 Setting prohibited 1xxx Setting prohibited When switching the selector first clear the ADST bit in the A D control register ADCR to...

Page 508: ...rated 4 The ADST bit remains set to 1 during A D conversion When A D converion ends the ADST bit is automatically cleared to 0 and the A D converter enters the idle state When the ADST bit is cleared to 0 during A D conversion A D conversion stops and the A D converter enters the idle state 13 4 2 Continuous Scan Mode In continuous scan mode A D conversion is to be performed sequentially on the sp...

Page 509: ...utomatically cleared to 0 and the A D converter enters the idle state When the ADST bit is cleared to 0 during A D conversion A D conversion stops and the A D converter enters the idle state 13 4 4 Input Sampling and A D Conversion Time The A D converter has a built in sample and hold circuit for each module The A D converter samples the analog input when the A D conversion start delay time tD has...

Page 510: ... D conversion start delay time tD A D conversion time tCONV Analog input sampling time tSPL ADST write timing End of A D conversion ADF Address Write cycle A D synchronization time Up to 6 states Internal write signal Analog input sampling signal Idle state Sample and hold 2 states Figure 13 2 A D Conversion Timing ...

Page 511: ...KSL0 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A D conversion start delay time tD 2 6 2 5 2 4 2 3 Input sampling time tSPL 36 27 18 9 A D conversion time tCONV 258 262 194 197 130 132 66 67 Note All values represent the number of states for Pφ Table 13 5 A D Conversion Time Scan Mode Conversion Time Calculation Example STC CKSL1 CKSL0 Conversion Time State Pφ 25 MHz Pφ 40 MHz 0...

Page 512: ...e timing from setting of the ADST bit until the start of A D conversion is the same as when 1 is written to the ADST bit by software 13 4 6 External Trigger Input Timing A D conversion can be externally triggered When the TRGE bit in the A D control status register ADCSR is set to 1 while the TRGS3 to TRGS0 bits in the A D trigger select register_0 ADTSR_0 is set to external trigger input external...

Page 513: ... is to be started by triggers the different sources for groups 0 and 1 are specified in ADTSR A request for conversion by group 1 generated during conversion by group 0 is ignored Figure 13 4 shows an example of operation when TRG4AN of the MTU2 has been specified as the A D conversion start request by group 0 and TRG4BN of the MTU2 has been specified as the A D conversion start request by group 1...

Page 514: ...sion end interrupt request The ADI interrupt can be enabled by setting the ADIE bit in the A D control status register ADCSR to 1 or disabled by clearing the ADIE bit to 0 Table 13 6 A D Converter Interrupt Source Name Interrupt Source Interrupt Source Flag ADI0 A D_0 conversion completed ADF in ADCSR_0 ADI1 A D_1 conversion completed ADF in ADCSR_1 ...

Page 515: ...hanges from the minimum voltage value B 0000000000 H 000 to B 0000000001 H 001 see figure 13 6 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output changes from B 1111111110 H 3FE to B 1111111111 H 3FF see figure 13 6 Nonlinearity error The error with respect to the ideal A D conversion characteristic between zero vol...

Page 516: ...2007 Page 496 of 758 REJ09B0243 0300 111 110 101 100 011 010 001 000 1 1024 2 1024 1022 1024 1023 1024 FS Quantization error Digital output Ideal A D conversion characteristic Analog input voltage Figure 13 5 Definitions of A D Conversion Accuracy ...

Page 517: ...007 Page 497 of 758 REJ09B0243 0300 FS Digital output Ideal A D conversion characteristic Nonlinearity error Analog input voltage Offset error Actual A D conversion characteristic Full scale error Figure 13 6 Definitions of A D Conversion Accuracy ...

Page 518: ...g may be insufficient and it may not be possible to guarantee A D conversion accuracy However for A D conversion in single mode with a large capacitance provided externally the input load will essentially comprise only the internal input resistance of 10 kΩ and the signal source impedance is ignored However as a low pass filter effect is obtained in this case it may not be possible to follow an an...

Page 519: ...and Vcc Vss Set AVss Vss for the relationship between AVcc AVss and Vcc Vss If the A D converter is not used the AVcc and AVss pins must not be left open 13 7 5 Notes on Board Design In board design digital circuitry and analog circuitry should be as mutually isolated as possible and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should...

Page 520: ...ged and so an error may arise Also when A D conversion is performed frequently as in scan mode if the current charged and discharged by the capacitance of the sample and hold circuit in the A D converter exceeds the current input via the input impedance Rin an error will arise in the analog input pin voltage Careful consideration is therefore required when deciding circuit constants AVcc 1 AN0 to ...

Page 521: ... independently for each channel Interrupt request on compare match Module standby mode can be set Figure 14 1 shows a block diagram of CMT Control circuit Clock selection CMSTR CMCSR_0 CMCOR_0 CMCNT_0 Channel 0 Channel 1 CMT Pφ 8 CMCSR_1 CMCOR_1 CMCNT_1 Pφ 32 Pφ 128 Pφ 512 Pφ 8 Pφ 32 Pφ 128 Pφ 512 Clock selection Control circuit Comparator Comparator Legend CMSTR Compare match timer start register...

Page 522: ...guration Register Name Abbrevia tion R W Initial Value Address Access Size Compare match timer start register CMSTR R W H 0000 H FFFFCE00 8 16 32 Compare match timer control status register_0 CMCSR_0 R W H 0000 H FFFFCE02 8 16 Compare match counter_0 CMCNT_0 R W H 0000 H FFFFCE04 8 16 32 Compare match constant register_0 CMCOR_0 R W H FFFF H FFFFCE06 8 16 Compare match timer control status registe...

Page 523: ...TR1 0 R W Count Start 1 Specifies whether compare match counter 1 operates or is stopped 0 CMCNT_1 count is stopped 1 CMCNT_1 count is started 0 STR0 0 R W Count Start 0 Specifies whether compare match counter 0 operates or is stopped 0 CMCNT_0 count is stopped 1 CMCNT_0 count is started 14 2 2 Compare Match Timer Control Status Register CMCSR CMCSR is a 16 bit register that indicates compare matc...

Page 524: ...COR values match CMF 1 0 Compare match interrupt CMI disabled 1 Compare match interrupt CMI enabled 5 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 CKS 1 0 00 R W Clock Select 1 and 0 Select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral operating clock Pφ When the STR bit in CMSTR is set to 1 CMCNT starts...

Page 525: ...gister CMCOR match CMCNT is cleared to H 0000 and the CMF flag in CMCSR is set to 1 The initial value of CMCNT is H 0000 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 14 2 4 Compare Match Constant Register CMCOR CMCOR is a 16 bit register that sets the interval up to a compare match with C...

Page 526: ...o 1 When the CMIE bit in CMCSR is set to 1 a compare match interrupt CMI is requested CMCNT then starts counting up again from H 0000 Figure 14 2 shows the operation of the compare match counter CMCOR H 0000 CMCNT value Time Counter cleared by compare match with CMCOR Figure 14 2 Counter Operation 14 3 2 CMCNT Count Timing One of four internal clocks Pφ 8 Pφ 32 Pφ 128 and Pφ 512 obtained by dividi...

Page 527: ...ection 6 Interrupt Controller INTC 14 4 2 Timing of Setting Compare Match Flag When CMCOR and CMCNT match a compare match signal is generated and the CMF bit in CMCSR is set to 1 The compare match signal is generated in the last cycle in which the values match when the CMCNT value is updated to H 0000 That is after a match between CMCOR and CMCNT the compare match signal is not generated until the...

Page 528: ...dby mode For details refer to section 19 Power Down Modes 14 5 2 Conflict between Write and Compare Match Processes of CMCNT When the compare match signal is generated in the T2 cycle while writing to CMCNT clearing CMCNT has priority over writing to it In this case CMCNT is not written to Figure 14 5 shows the timing to clear the CMCNT counter Peripheral operating clock Pφ Address Internal write ...

Page 529: ...the T2 cycle while writing to CMCNT in words the writing has priority over the count up In this case the count up is not performed Figure 14 6 shows the timing to write to CMCNT in words M CMCNT write data CMCNT count up enable Peripheral operating clock Pφ Address Internal write CMCNT T1 T2 N CMCSR write cycle CMCNT Figure 14 6 Conflict between Word Write and Count Up Processes of CMCNT ...

Page 530: ...ritten to is also not counted and the previous contents remain Figure 14 7 shows the timing when the count up occurs in the T2 cycle while writing to CMCNT in bytes M CMCNT write data X X CMCNTH CMCNT count up enable CMCNTH CMCNTL Peripheral operating clock Pφ Address Internal write T1 T2 N CMCSR write cycle Figure 14 7 Conflict between Byte Write and Count Up Processes of CMCNT 14 5 5 Compare Mat...

Page 531: ...POE TXD0 output SCI PA2 I O port IRQ0 input INTC SCK0 I O SCI PA3 I O port IRQ1 input INTC RXD1 input SCI TRST input H UDI PA4 I O port IRQ2 input INTC TXD1 output SCI TMS input H UDI PA5 I O port IRQ3 input INTC SCK1 I O SCI PA6 I O port TCLKA input MTU2 PA7 I O port TCLKB input MTU2 SCK2 I O SCI TCK input H UDI PA8 I O port TCLKC input MTU2 RXD2 input SCI TDI input H UDI PA9 I O port TCLKD input...

Page 532: ...MTU2 TXD1 output SCI PE6 I O port TIOC2A I O MTU2 SCK1 I O SCI PE7 I O port TIOC2B I O MTU2 PE8 I O port TIOC3A I O MTU2 PE9 I O port TIOC3B I O MTU2 PE10 I O port TIOC3C I O MTU2 PE11 I O port TIOC3D I O MTU2 PE12 I O port TIOC4A I O MTU2 PE13 I O port TIOC4B I O MTU2 MRES input INTC PE14 I O port TIOC4C I O MTU2 PE15 I O port TIOC4D I O MTU2 IRQOUT output INTC F PF0 input port AN0 input A D PF1 ...

Page 533: ...2 I O SCI TCK input H UDI PA8 I O port TCLKC input MTU2 RXD2 input SCI TDI input H UDI PA9 I O port TCLKD input MTU2 TXD2 output SCI POE8 input POE TDO output H UDI B PB1 I O port TIC5W input MTU2 PB3 I O port IRQ1 input INTC POE1 input POE TIC5V input MTU2 PB5 I O port IRQ3 input INTC TIC5U input MTU2 E PE0 I O port TIOC0A I O MTU2 PE1 I O port TIOC0B I O MTU2 RXD0 input SCI PE2 I O port TIOC0C I...

Page 534: ... Related Module Function 4 Related Module Function 5 Related Module F PF0 input port AN0 input A D PF1 input port AN1 input A D PF2 input port AN2 input A D PF3 input port AN3 input A D PF4 input port AN4 input A D PF5 input port AN5 input A D PF6 input port AN6 input A D PF7 input port AN7 input A D Note During A D conversion the AN input function is enabled ...

Page 535: ...CL VCL 61 AVcc AVcc 52 AVss AVss 47 PLLVss PLLVss 42 EXTAL EXTAL 41 XTAL XTAL 46 MD1 MD1 45 FWE ASEBRKAK ASEBRK FWE 39 RES RES 40 WDTOVF WDTOVF 44 NMI NMI 43 ASEMD0 ASEMD0 38 PA0 PA0 POE0 RXD0 36 PA1 PA1 POE1 TXD0 34 PA2 PA2 IRQ0 SCK0 32 PA3 TRST PA3 IRQ1 RXD1 31 PA4 TMS PA4 IRQ2 TXD1 30 PA5 PA5 IRQ3 SCK1 29 PA6 PA6 TCLKA 28 PA7 TCK PA7 TCLKB SCK2 27 PA8 TDI PA8 TCLKC RXD2 26 PA9 TDO PA9 TCLKD TXD...

Page 536: ... 48 PB5 PB5 IRQ3 TIC5U 62 POE3 PB16 POE3 17 PE0 PE0 TIOC0A 16 PE1 PE1 TIOC0B RXD0 15 PE2 PE2 TIOC0C TXD0 14 PE3 PE3 TIOC0D SCK0 13 PE4 PE4 TIOC1A RXD1 12 PE5 PE5 TIOC1B TXD1 11 PE6 PE6 TIOC2A SCK1 10 PE7 PE7 TIOC2B 9 PE8 PE8 TIOC3A 5 PE9 PE9 TIOC3B 7 PE10 PE10 TIOC3C 3 PE11 PE11 TIOC3D 2 PE12 PE12 TIOC4A 1 PE13 PE13 TIOC4B MRES 64 PE14 PE14 TIOC4C 63 PE15 PE15 TIOC4D IRQOUT 60 PF0 AN0 PF0 AN0 59 P...

Page 537: ...n ASEMD0 low Table 15 4 SH7124 Pin Functions in Each Operating Mode Pin Name Single Chip Mode MCU Mode 3 Pin No Initial Function PFC Selected Function Possibilities 4 17 Vcc Vcc 6 19 Vss Vss 8 25 VCL VCL 48 AVcc AVcc 39 AVss AVss 35 PLLVss PLLVss 30 EXTAL EXTAL 29 XTAL XTAL 34 MD1 MD1 33 FWE ASEBRKAK ASEBRK FWE 27 RES RES 28 WDTOVF WDTOVF 32 NMI NMI 31 ASEMD0 ASEMD0 26 PA0 PA0 POE0 RXD0 24 PA1 PA1...

Page 538: ... IRQ3 TIC5U 15 PE0 PE0 TIOC0A 14 PE1 PE1 TIOC0B RXD0 13 PE2 PE2 TIOC0C TXD0 12 PE3 PE3 TIOC0D SCK0 11 PE8 PE8 TIOC3A 9 PE9 PE9 TIOC3B 10 PE10 PE10 TIOC3C 7 PE11 PE11 TIOC3D 5 PE12 PE12 TIOC4A 3 PE13 PE13 TIOC4B MRES 2 PE14 PE14 TIOC4C 1 PE15 PE15 TIOC4D IRQOUT 47 PF0 AN0 PF0 AN0 46 PF1 AN1 PF1 AN1 45 PF2 AN2 PF2 AN2 44 PF3 AN3 PF3 AN3 43 PF4 AN4 PF4 AN4 42 PF5 AN5 PF5 AN5 41 PF6 AN6 PF6 AN6 40 PF7...

Page 539: ...er L2 PACRL2 R W H 0000 H FFFFD114 8 16 32 Port A control register L1 PACRL1 R W H 0000 H FFFFD116 8 16 Port B I O register H PBIORH R W H 0000 H FFFFD184 8 16 32 Port B I O register L PBIORL R W H 0000 H FFFFD186 8 16 Port B control register H1 PBCRH1 R W H 0000 H FFFFD18E 8 16 Port B control register L2 PBCRL2 R W H 0000 H FFFFD194 8 16 32 Port B control register L1 PBCRL1 R W H 0000 H FFFFD196 ...

Page 540: ...e of PAIORL is H 0000 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR 15 1 2 Port A Control Registers L1 to L4 PACRL1 to PACRL4 PACRL1 to PACRL4 are 16 bit re...

Page 541: ...W R W R W PA14 Mode Select the function of the PA14 RXD1 pin 000 PA14 I O port 110 RXD1 input SCI Other than above Setting prohibited 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 5 4 PA13MD2 PA13MD1 PA13MD0 0 0 0 R W R W R W PA13 Mode Select the function of the PA13 SCK1 pin 000 PA13 I O port 110 SCK1 I O SCI Other than above Setting prohibited 3 0 R Reserved Th...

Page 542: ...ion 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 13 12 PA11MD2 PA11MD1 PA11MD0 0 0 0 R W R W R W PA11 Mode Select the function of the PA11 TXD0 ADTRG pin 000 PA11 I O port 010 ADTRG input A D 110 TXD0 output SCI Other than above Setting prohibited 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 9 8 PA10MD2 PA10MD1 PA10MD0 0 0...

Page 543: ...ction is fixed to TDO output 000 PA9 I O port 001 TCLKD input MTU2 110 TXD2 output SCI 111 POE8 input POE Other than above Setting prohibited 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 1 0 PA8MD2 PA8MD1 PA8MD0 0 0 0 R W R W R W PA8 Mode Select the function of the PA8 TCLKC RXD2 TDI pin When the E10A is in use ASEMD0 low function is fixed to TDI input 000 PA8 I...

Page 544: ... R W PA7 Mode Select the function of the PA7 TCLKB SCK2 TCK pin When the E10A is in use ASEMD0 low function is fixed to TCK input 000 PA7 I O port 001 TCLKB input MTU2 110 SCK2 I O SCI Other than above Setting prohibited 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 9 8 PA6MD2 PA6MD1 PA6MD0 0 0 0 R W R W R W PA6 Mode Select the function of the PA6 TCLKA pin 000...

Page 545: ...Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R W R W R W R R W R W R W R R W R W R W PA3 MD2 PA3 MD1 PA3 MD0 PA2 MD2 PA2 MD1 PA2 MD0 PA1 MD2 PA1 MD1 PA1 MD0 PA0 MD2 PA0 MD1 PA0 MD0 Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 13 12 PA3MD2 PA3MD1 PA3MD0 0 0...

Page 546: ...Reserved This bit is always read as 0 The write value should always be 0 6 5 4 PA1MD2 PA1MD1 PA1MD0 0 0 0 R W R W R W PA1 Mode Select the function of the PA1 POE1 TXD0 pin 000 PA1 I O port 001 TXD0 output SCI 111 POE1 input POE Other than above Setting prohibited 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 1 0 PA0MD2 PA0MD1 PA0MD0 0 0 0 R W R W R W PA0 Mode Sel...

Page 547: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R W R W R W R R W R W R W PA9 MD2 PA9 MD1 PA9 MD0 PA8 MD2 PA8 MD1 PA8 MD0 Bit Bit Name Initial Value R W Description 15 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 5 4 PA9MD2 PA9MD1 PA9MD0 0 0 0 R W R W R W PA9 Mode Select the function of the PA9 TCLKD TXD2 TDO POE8 pin W...

Page 548: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R W R W R W R R R R R R W R W R W PA7 MD2 PA7 MD1 PA7 MD0 PA6 MD2 PA6 MD1 PA6 MD0 PA4 MD2 PA4 MD1 PA4 MD0 Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 13 12 PA7MD2 PA7MD1 PA7MD0 0 0 0 R W R W R W PA7 Mode Select the function of the PA...

Page 549: ...D1 PA4MD0 0 0 0 R W R W R W PA4 Mode Select the function of the PA4 IRQ2 TXD1 TMS pin When the E10A is in use ASEMD0 low function is fixed to TMS input 000 PA4 I O port 001 TXD1 output SCI 111 IRQ2 input INTC Other than above Setting prohibited Port A Control Register L1 PACRL1 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R R R R R W R...

Page 550: ...above Setting prohibited 11 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 5 4 PA1MD2 PA1MD1 PA1MD0 0 0 0 R W R W R W PA1 Mode Select the function of the PA1 POE1 TXD0 pin 000 PA1 I O port 001 TXD0 output SCI 111 POE1 input POE Other than above Setting prohibited 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 1 0 PA0MD2 ...

Page 551: ...t B pins are functioning as general purpose inputs outputs PB16 In other states PBIORH is disabled A given pin on port B will be an output pin if the corresponding bit in PBIORH or PBIORL is set to 1 and an input pin if the bit is cleared to 0 However bit 2 of PBIORL and bit 0 of PBIORH are disabled in SH7124 Bits 15 to 6 4 and 0 of PBIORL and bits 15 to 1 of PBIORH are reserved These bits are alw...

Page 552: ...R R R R R R R R R W Note After a power on reset write can be performed only once PB16 MD Bit Bit Name Initial Value R W Description 15 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 PB16MD 1 R W PB16 Mode Select the function of the PB16 POE3 pin 0 PB16 I O port 1 POE3 input POE Port B Control Register L2 PBCRL2 Bit Initial value R W 15 14 13 12 11 10 9 8...

Page 553: ...1 PBCRL1 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R W R W R W R R W R W R W R R R R PB3 MD2 PB3 MD1 PB3 MD0 PB2 MD2 PB2 MD1 PB2 MD0 PB1 MD2 PB1 MD1 PB1 MD0 Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 13 12 PB3MD2 PB3MD1 PB3MD0 0 0 0 R W R W R W PB3 Mo...

Page 554: ...alue should always be 0 6 5 4 PB1MD2 PB1MD1 PB1MD0 0 0 0 R W R W R W PB1 Mode Select the function of the PB1 TIC5W pin 000 PB1 I O port 011 TIC5W input MTU2 Other than above Setting prohibited 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 SH7124 Port B Control Register H1 PBCRH1 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0...

Page 555: ...4 PB5MD2 PB5MD1 PB5MD0 0 0 0 R W R W R W PB5 Mode Select the function of the PB5 IRQ3 TIC5U pin 000 PB5 I O port 001 IRQ3 input INTC 011 TIC5U input MTU2 Other than above Setting prohibited 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Port B Control Register L1 PBCRL1 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 556: ...O port 001 IRQ1 input INTC 010 POE1 input POE 011 TIC5V input MTU2 Other than above Setting prohibited 11 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 5 4 PB1MD2 PB1MD1 PB1MD0 0 0 0 R W R W R W PB1 Mode Select the function of the PB1 TIC5W pin 000 PB1 I O port 011 TIC5W input MTU2 Other than above Setting prohibited 3 to 0 All 0 R Reserved These bits a...

Page 557: ... in SH7124 The initial value of PEIORL is H 0000 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PE15 IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE8 IOR PE7 IOR PE6 IOR PE5 IOR PE4 IOR PE3 IOR PE2 IOR PE1 IOR PE0 IOR 15 1 6 Port E Control Registers L1 to L4 PECRL1 to PECRL4 PEC...

Page 558: ...R W R W R W PE14 Mode Select the function of the PE14 TIOC4C pin 000 PE14 I O port 001 TIOC4C I O MTU2 Other than above Setting prohibited 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 4 PE13MD1 PE13MD0 0 0 R W R W PE13 Mode Select the function of the PE13 TIOC4B MRES pin 00 PE13 I O port 01 TIOC4B I O MTU2 10 MRES input INTC Other than above Setting pro...

Page 559: ...D0 0 0 0 R W R W R W PE11 Mode Select the function of the PE11 TIOC3D pin 000 PE11 I O port 001 TIOC3D I O MTU2 Other than above Setting prohibited 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 9 8 PE10MD2 PE10MD1 PE10MD0 0 0 0 R W R W R W PE10 Mode Select the function of the PE10 TIOC3C pin 000 PE10 I O port 001 TIOC3C I O MTU2 Other than above Setting prohibi...

Page 560: ... R W R W R W PE7 MD2 PE7 MD1 PE7 MD0 PE6 MD2 PE6 MD1 PE6 MD0 PE5 MD2 PE5 MD1 PE5 MD0 PE4 MD2 PE4 MD1 PE4 MD0 Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 13 12 PE7MD2 PE7MD1 PE7MD0 0 0 0 R W R W R W PE7 Mode Select the function of the PE7 TIOC2B pin 000 PE7 I O port 001 TIOC2B I O MTU2 Other than above Setting prohibi...

Page 561: ... always read as 0 The write value should always be 0 2 1 0 PE4MD2 PE4MD1 PE4MD0 0 0 0 R W R W R W PE4 Mode Select the function of the PE4 TIOC1A RXD1 pin 000 PE4 I O port 001 TIOC1A I O MTU2 110 RXD1 input SCI Other than above Setting prohibited Port E Control Register L1 PECRL1 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R W R W R W ...

Page 562: ...2 Mode Select the function of the PE2 TIOC0C TXD0 pin 000 PE2 I O port 001 TIOC0C I O MTU2 110 TXD0 output SCI Other than above Setting prohibited 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 5 4 PE1MD2 PE1MD1 PE1MD0 0 0 0 R W R W R W PE1 Mode Select the function of the PE1 TIOC0B RXD0 pin 000 PE1 I O port 001 TIOC0B I O MTU2 110 RXD0 input SCI Other than above ...

Page 563: ...2 PE15MD1 PE15MD0 0 0 0 R W R W R W PE15 Mode Select the function of the PE15 TIOC4D IRQOUT pin 000 PE15 I O port 001 TIOC4D I O MTU2 011 IRQOUT output INTC Other than above Setting prohibited 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 9 8 PE14MD2 PE14MD1 PE14MD0 0 0 0 R W R W R W PE14 Mode Select the function of the PE14 TIOC4C pin 000 PE14 I O port 001 TIO...

Page 564: ... R R W R W R W R R W R W R W R R W R W R W R R W R W R W PE11 MD2 PE11 MD1 PE11 MD0 PE10 MD2 PE10 MD1 PE10 MD0 PE9 MD2 PE9 MD1 PE9 MD0 PE8 MD2 PE8 MD1 PE8 MD0 Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 13 12 PE11MD2 PE11MD1 PE11MD0 0 0 0 R W R W R W PE11 Mode Select the function of the PE11 TIOC3D pin 000 PE11 I O p...

Page 565: ...ve Setting prohibited 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 1 0 PE8MD2 PE8MD1 PE8MD0 0 0 0 R W R W R W PE8 Mode Select the function of the PE8 TIOC3A pin 000 PE8 I O port 001 TIOC3A I O MTU2 Other than above Setting prohibited Port E Control Register L2 PECRL2 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R ...

Page 566: ...0 0 0 0 R W R W R W PE3 Mode Select the function of the PE3 TIOC0D SCK0 pin 000 PE3 I O port 001 TIOC0D I O MTU2 110 SCK0 I O SCI Other than above Setting prohibited 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 9 8 PE2MD2 PE2MD1 PE2MD0 0 0 0 R W R W R W PE2 Mode Select the function of the PE2 TIOC0C TXD0 pin 000 PE2 I O port 001 TIOC0C I O MTU2 110 TXD0 output...

Page 567: ...output when it is selected as the multiplexed pin function by port E control register L4 PECRL4 When PECRL4 selects another function the IFCR setting does not affect the pin function Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W IRQ MD1 IRQ MD0 Bit Bit Name Initial Value R W Description 15 to 2 All 0 R Reserved These...

Page 568: ...unctions allocated to several pins When using one of the functions shown below in multiple pins use it with care of signal polarity considering the transmit forms Table 15 6 Transmit Forms of Input Functions Allocated to Multiple Pins OR Type AND Type SCK0 to SCK2 RXD0 to RXD2 POE0 POE1 POE3 POE8 IRQ0 to IRQ3 Note This pin is supported only by the SH7125 OR type Signals input to several pins are f...

Page 569: ...n 8 bit input only port The SH7124 has four ports A B E and F Port A is an 8 bit port port B is a 3 bit port and port E is a 12 bit port Port F is an 8 bit input only port All the port pins are multiplexed as general input output pins and special function pins The functions of the multiplex pins are selected by means of the pin function controller PFC Each port is provided with a data register for...

Page 570: ...put PA5 I O IRQ3 input SCK1 I O PA4 I O IRQ2 input TXD1 output TMS input PA3 I O IRQ1 input RXD1 input TRST input PA2 I O IRQ0 input SCK0 I O PA1 I O POE1 input TXD0 output PA0 I O POE0 input RXD0 input Port A Figure 16 1 Port A SH7125 Port A in the SH7124 is an input output port with the eight pins shown in figure 16 2 PA9 I O TCLKD input TXD2 output TDO output POE8 input PA8 I O TCLKC input RXD2...

Page 571: ...6 bit readable writable register that stores port A data Bits PA15DR to PA0DR correspond to pins PA15 to PA0 multiplexed functions omitted here in the SH7125 Bits PA9DR to PA6DR PA4DR PA3DR PA1DR and PA0DR correspond to pins PA9 to PA6 PA4 PA3 PA1 and PA0 respectively multiplexed functions omitted here in the SH7124 When a pin function is general output if a value is written to PADRL that value is...

Page 572: ... R W R W R W R W PA15 DR PA14 DR PA13 DR PA12 DR PA11 DR PA10 DR PA9 DR PA8 DR PA7 DR PA6 DR PA5 DR PA4 DR PA3 DR PA2 DR PA1 DR PA0 DR Bit Bit Name Initial Value R W Description 15 PA15DR 0 R W See table 16 2 14 PA14DR 0 R W 13 PA13DR 0 R W 12 PA12DR 0 R W 11 PA11DR 0 R W 10 PA10DR 0 R W 9 PA9DR 0 R W 8 PA8DR 0 R W 7 PA7DR 0 R W 6 PA6DR 0 R W 5 PA5DR 0 R W 4 PA4DR 0 R W 3 PA3DR 0 R W 2 PA2DR 0 R W...

Page 573: ...DR PA1 DR PA0 DR Bit Bit Name Initial Value R W Description 15 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 PA9DR 0 R W See table 16 2 8 PA8DR 0 R W 7 PA7DR 0 R W 6 PA6DR 0 R W 5 0 R Reserved This bit is always read as 0 The write value should always be 0 4 PA4DR 0 R W See table 16 2 3 PA3DR 0 R W 2 0 R Reserved This bit is always read as 0 The write ...

Page 574: ...PAIORH PAIORL Pin Function Read Write 0 General input Pin state Can write to PADRL but it has no effect on pin state Other than general input Pin state Can write to PADRL but it has no effect on pin state 1 General output PADRL value Value written is output from pin Other than general output PADRL value Can write to PADRL but it has no effect on pin state ...

Page 575: ...APRL SH7125 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R PA15 PR PA14 PR PA13 PR PA12 PR PA11 PR PA10 PR PA9 PR PA8 PR PA7 PR PA6 PR PA5 PR PA4 PR PA3 PR PA2 PR PA1 PR PA0 PR Bit Bit Name Initial Value R W Description 15 PA15PR Pin state R 14 PA14PR Pin state R The pin state is returned regardless of the PFC setting These bits cannot be modified 13 PA...

Page 576: ...s be 0 9 PA9PR Pin state R 8 PA8PR Pin state R 7 PA7PR Pin state R 6 PA6PR Pin state R The pin state is returned regardless of the PFC setting These bits cannot be modified 5 0 R Reserved This bit is always read as 0 The write value should always be 0 4 PA4PR Pin state R 3 PA3PR Pin state R The pin state is returned regardless of the PFC setting These bits cannot be modified 2 0 R Reserved This bi...

Page 577: ...O TIC5W input PB3 I O IRQ1 input POE1 input TIC5V input Port B Figure 16 4 Port B SH7124 16 2 1 Register Descriptions Port B is a 5 bit input output port in the SH7125 and a 3 bit input output port in the SH7124 Port B has the following register For details on register addresses and register states during each processing refer to section 20 List of Registers Table 16 3 Register Configuration Regis...

Page 578: ...alue is output directly from the pin and if PBDRH or PBDRL is read the register value is returned directly regardless of the pin state When a pin function is general input if PBDRH or PBDRL is read the pin state not the register value is returned directly If a value is written to PBDRH or PBDRL although that value is written into PBDRH or PBDRL it does not affect the pin state Table 16 4 summarize...

Page 579: ...DRL SH7125 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R W R R W R W R W R PB5 DR PB3 DR PB2 DR PB1 DR Bit Bit Name Initial Value R W Description 15 to 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 PB5DR 0 R W See table 16 4 4 0 R Reserved This bit is always read as 0 The write value shoul...

Page 580: ...ee table 16 4 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 PB1DR 0 R W See table 16 4 0 0 R Reserved This bit is always read as 0 The write value should always be 0 Table 16 4 Port B Data Register PBDR Read Write Operations PBDRH Bit 0 and PBDRL Bits 5 and 3 to 1 PBIOR Pin Function Read Write 0 General input Pin state Can write to PBDRH and PBDRL but it has no e...

Page 581: ...ns omitted here in the SH7124 PBPRH SH7125 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R PB16 PR Bit Bit Name Initial Value R W Description 15 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 PB16PR Pin state R The pin state is returned regardless of the PFC setting This bit cannot...

Page 582: ...0 R Reserved These bits are always read as 0 The write value should always be 0 5 PB5PR Pin state R The pin state is returned regardless of the PFC setting This bit cannot be modified 4 0 R Reserved This bit is always read as 0 The write value should always be 0 3 PB3PR Pin state R 2 PB2PR Pin state R The pin state is returned regardless of the PFC setting These bits cannot be modified 1 PB1PR Pin...

Page 583: ...s be 0 5 PB5PR Pin state R The pin state is returned regardless of the PFC setting This bit cannot be modified 4 0 R Reserved This bit is always read as 0 The write value should always be 0 3 PB3PR Pin state R The pin state is returned regardless of the PFC setting This bit cannot be modified 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 PB1PR Pin state R The pin...

Page 584: ...put PE14 I O TIOC4C I O PE13 I O TIOC4B I O MRES input PE12 I O TIOC4A I O PE11 I O TIOC3D I O PE10 I O TIOC3C I O PE9 I O TIOC3B I O PE8 I O TIOC3A I O PE7 I O TIOC2B I O PE6 I O TIOC2A I O SCK1 I O PE5 I O TIOC1B I O TXD1 output PE4 I O TIOC1A I O RXD1 input PE3 I O TIOC0D I O SCK0 I O PE2 I O TIOC0C I O TXD0 output PE1 I O TIOC0B I O RXD0 input PE0 I O TIOC0A I O Port E Figure 16 5 Port E SH712...

Page 585: ...wn in figure 16 6 PE15 I O TIOC4D I O IRQOUT output PE14 I O TIOC4C I O PE13 I O TIOC4B I O MRES input PE12 I O TIOC4A I O PE11 I O TIOC3D I O PE10 I O TIOC3C I O PE9 I O TIOC3B I O PE8 I O TIOC3A I O PE3 I O TIOC0D I O SCK0 I O PE2 I O TIOC0C I O TXD0 output PE1 I O TIOC0B I O RXD0 input PE0 I O TIOC0A I O Port E Figure 16 6 Port E SH7124 ...

Page 586: ...is a 16 bit readable writable register that stores port E data Bits PE15DR to PE0DR correspond to pins PE15 to PE0 multiplexed functions omitted here in the SH7125 Bits PE15DR to PE8DR and PE3DR to PE0DR correspond to pins PE15 to PE8 and PE3 to PE0 respectively multiplexed functions omitted here in the SH7124 When a pin function is general output if a value is written to PEDRL that value is outpu...

Page 587: ... R W R W R W R W PE15 DR PE14 DR PE13 DR PE12 DR PE11 DR PE10 DR PE9 DR PE8 DR PE7 DR PE6 DR PE5 DR PE4 DR PE3 DR PE2 DR PE1 DR PE0 DR Bit Bit Name Initial Value R W Description 15 PE15DR 0 R W See table 16 6 14 PE14DR 0 R W 13 PE13DR 0 R W 12 PE12DR 0 R W 11 PE11DR 0 R W 10 PE10DR 0 R W 9 PE9DR 0 R W 8 PE8DR 0 R W 7 PE7DR 0 R W 6 PE6DR 0 R W 5 PE5DR 0 R W 4 PE4DR 0 R W 3 PE3DR 0 R W 2 PE2DR 0 R W...

Page 588: ... PE11DR 0 R W 10 PE10DR 0 R W 9 PE9DR 0 R W 8 PE8DR 0 R W 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 PE3DR 0 R W See table 16 6 2 PE2DR 0 R W 1 PE1DR 0 R W 0 PE0DR 0 R W Table 16 6 Port E Data Register L PEDRL Read Write Operations PEDRL Bits 15 to 0 PEIOR Pin Function Read Write 0 General input Pin state Can write to PEDRL but it has no effect on ...

Page 589: ...SH7125 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R PE15 PR PE14 PR PE13 PR PE12 PR PE11 PR PE10 PR PE9 PR PE8 PR PE7 PR PE6 PR PE5 PR PE4 PR PE3 PR PE2 PR PE1 PR PE0 PR Bit Bit Name Initial Value R W Description 15 PE15PR Pin state R 14 PE14PR Pin state R The pin state is returned regardless of the PFC setting These bits cannot be modified 13 PE13PR ...

Page 590: ...ion 15 PE15PR Pin state R 14 PE14PR Pin state R The pin state is returned regardless of the PFC setting These bits cannot be modified 13 PE13PR Pin state R 12 PE12PR Pin state R 11 PE11PR Pin state R 10 PE10PR Pin state R 9 PE9PR Pin state R 8 PE8PR Pin state R 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 PE3PR Pin state R 2 PE2PR Pin state R The pin...

Page 591: ...F4 input AN4 input PF2 input AN2 input PF0 input AN0 input Port F Figure 16 7 Port F SH7125 SH7124 16 4 1 Register Descriptions Port F is an 8 bit input only port in the SH7125 and SH7124 Port F has the following register For details on register addresses and register states during each processing refer to section 20 List of Registers Table 16 7 Register Configuration Register Name Abbrevia tion R...

Page 592: ...ead Table 16 8 summarizes port F data register L read write operations PFDRL SH7125 SH7124 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 PF7 DR PF6 DR PF5 DR PF4 DR PF3 DR PF2 DR PF1 DR PF0 DR Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PF7DR Pi...

Page 593: ...mer The user MAT can be programmed Programming erasing interface by the download of on chip program This LSI has a dedicated programming erasing program After downloading this program to the on chip RAM programming erasing can be performed by setting the argument parameter The user branch is also supported User branch The program processing is performed in 128 byte units It consists the program pu...

Page 594: ...ramming time is tP ms Typ in 128 byte simultaneous programming and tP 128 ms per byte The erasing time is tE s Typ per block Number of programming The number of flash memory programming can be up to NWEC times Operating frequency at programming erasing The operating frequency at programming erasing is a maximum of 40 MHz Pφ ...

Page 595: ... User MAT 128 kbytes 64 kbytes 32 kbytes Operating mode Module bus FWE pin Mode pins Internal address bus Internal data bus 32 bits Legend FCCS Flash code control and status register FPCS Flash program code select register FECS Flash erase code select register FKEY Flash key code register FTDAR Flash transfer destination address register Figure 17 1 Block Diagram of Flash Memory ...

Page 596: ...ead in user mode but cannot be programmed or erased Flash memory can be read programmed or erased on the board only in user program mode and boot mode Reset state User mode User program mode Boot mode On board programming mode FWE 0 FWE 1 RES 0 User mode setting R E S 0 U s e r p r o g r a m m o d e s e t t i n g B o o t m o d e s e t t i n g R E S 0 Figure 17 2 Mode Transition of Flash Memory Tab...

Page 597: ...sure Possible Automatic Possible Possible Automatic Block division erasure Possible 1 Possible Impossible Program data transfer From host via SCI From optional device via RAM Via programmer User branch function Not possible Possible Impossible Reset initiation MAT Embedded program storage MAT User MAT Embedded program storage MAT Transition to user mode Mode setting change and reset FWE setting ch...

Page 598: ...53 SH71243 64KB SH71252 SH71242 32KB SH71241 Figure 17 3 Flash Memory Configuration 17 2 5 Block Division The user MAT is divided into 64 Kbytes 128 kbyte version one block 32 Kbytes one block and 4 Kbytes eight blocks as shown in figure 17 4 The user MAT can be erased in this divided block units and the erase block number of EB0 to EB9 is specified when erasing Address H 00000000 Last address of ...

Page 599: ...VBR FKEY and SCO bits Initialization execution on chip program execution Select on chip program to be downloaded and set download destination Programming in 128 byte units or erasing in one block units on chip program execution Start user procedure program for programming erasing End user procedure program Programming erasing completed No Yes Figure 17 5 Overview of User Procedure Program 1 Select...

Page 600: ... downloaded These settings are performed by using the programming erasing interface parameters 4 Programming Erasing Execution To program or erase the FWE pin must be brought high and user program mode must be entered The program data programming destination address is specified in 128 byte units when programming The block to be erased is specified in erase block units when erasing These specifica...

Page 601: ... 1 MD1 Input Sets operating mode of this LSI Transmit data TXD1 PA4 Output Serial transmit data output used in boot mode Receive data RXD1 PA3 Input Serial receive data input used in boot mode 17 4 Register Descriptions 17 4 1 Registers The registers parameters which control flash memory when the on chip flash memory is valid are shown in table 17 4 There are several operating modes for accessing ...

Page 602: ...nitial value of the FWE bit is 0 when the FWE pin goes low The initial value of the FWE bit is 1 when the FWE pin goes high 3 All registers can be accessed only in bytes Table 17 4 2 Parameter Configuration Name Abbreviation R W Initial Value Address Access Size Download pass fail result DPFR R W Undefined On chip RAM 8 16 32 Flash pass fail result FPFR R W Undefined R0 of CPU 8 16 32 Flash multip...

Page 603: ...8 REJ09B0243 0300 Table 17 5 Register Parameter and Target Mode Download Initiali zation Program ming Erasure Read FCCS FPCS PECS FKEY Programming erasing interface registers FTDAR DPFR FPFR FPEFEQ FUBRA FMPAR FMPDR Programming erasing interface parameters FEBS ...

Page 604: ...rogramming or erasing flash memory and the download of the on chip program Bit Initial value R W 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 R R R R R R R R W FWE FLER SCO Bit Bit Name Initial Value R W Description 7 FWE 1 0 R Flash Programming Enable Monitors the level which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing The initial value is 0 or 1 acco...

Page 605: ...To reduce the damage to flash memory the reset signal must be released after the reset period of 100 µs which is longer than normal 0 Flash memory operates normally Programming erasing protection for flash memory error protection is invalid Clearing condition At a power on reset 1 Indicates an error occurs during programming erasing flash memory Programming erasing protection for flash memory erro...

Page 606: ... 17 7 2 Other Notes Since this bit is cleared to 0 when download is completed this bit cannot be read as 1 Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank switching to the on chip program storage area Therefore before issuing a download request SCO 1 set VBR to H 84000000 Otherwise the CPU gets out of control Once download end is confirmed VBR can be...

Page 607: ...read as 0 The write value should always be 0 0 PPVS 0 R W Program Pulse Single Selects the programming program 0 On chip programming program is not selected Clearing condition When transfer is completed 1 On chip programming program is selected 3 Flash Erase Code Select Register FECS FECS selects download of the on chip erasing program Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R ...

Page 608: ...ed if the key code is not written Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W K 7 0 Bit Bit Name Initial Value R W Description 7 to 0 K 7 0 All 0 R W Key Code Only when H A5 is written writing to the SCO bit is valid When a value other than H A5 is written to FKEY 1 cannot be written to the SCO bit Therefore downloading to the on chip RAM cannot be execute...

Page 609: ...n the range of H 02 to H 04 after setting the SCO bit in FCCS to 1 and performing download Before setting the SCO bit to 1 be sure to set the FTDAR value between H 02 to H 04 as well as clearing this bit to 0 0 Setting of TDA6 to TDA0 is normal 1 Setting of TDER and TDA6 to TDA0 is H 00 to H 01 and H 05 to H FF and download has been aborted 6 to 0 TDA 6 0 All 0 R W Transfer Destination Address The...

Page 610: ... the on chip program is executed CPU registers except for R0 are stored The return value of the processing result is written in R0 Since the stack area is used for storing the registers or as a work area the stack area must be saved at the processing start The maximum size of a stack area to be used is 128 bytes The programming erasing interface parameters are used in the following four items 1 Do...

Page 611: ...ting the SCO bit to 1 The on chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR For the address map of the on chip RAM see figure 17 10 The download control is set by using the programming erasing interface registers The return value is given by the DPFR parameter a Download pass fail result parameter DPFR one byte of start address of ...

Page 612: ...m is not selected or the program is selected without mapping an error occurs 0 Download program can be selected normally 1 Download error occurs Multi selection or program which is not mapped is selected 1 FK Undefined R W Flash Key Register Error Detect Returns the check result whether the value of FKEY is set to H A5 0 FKEY setting is normal FKEY H A5 1 FKEY setting is abnormal FKEY value other ...

Page 613: ...anch destination address must be set The initial program is set as a parameter of the programming erasing program which has downloaded these settings 2 1 Flash programming erasing frequency parameter FPEFEQ general register R4 of CPU This parameter sets the operating frequency of the CPU For the range of the operating frequency of this LSI see section 21 3 1 Clock Timing Bit Initial value R W Bit ...

Page 614: ...llows The number to three decimal places of 28 882 is rounded and the value is thus 28 88 The formula that 28 88 100 2888 is converted to the binary digit and B 0000 B 1011 B 0100 B 1000 H 0B48 is set to R4 2 2 Flash user branch address setting parameter FUBRA general register R5 of CPU This parameter sets the user branch destination address The user program which has been set can be executed in s...

Page 615: ...itten the value of flash memory cannot be guaranteed The download of the on chip program initialization initiation of the programming erasing program must not be executed in the processing of the user branch destination Programming or erasing cannot be guaranteed when returning from the user branch destination The program data which has already been prepared must not be programmed Store general re...

Page 616: ...turn 0 2 BR Undefined R W User Branch Error Detect Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming erasing program which has been downloaded 0 User branch address setting is normal 1 User branch address setting is abnormal 1 FQ Undefined R W Frequency Error Detect Returns the check result whether the speci...

Page 617: ...address of the area in which the prepared program data is stored must be set in general register R4 This parameter is called FMPDR flash multipurpose data destination area parameter For details on the programming procedure see section 17 5 2 User Program Mode Only in On Chip 128 Kbyte and 64 Kbyte ROM Version 3 1 Flash multipurpose address area parameter FMPAR general register R5 of CPU This param...

Page 618: ...T When the storage destination of the program data is in flash memory an error occurs The error occurrence is indicated by the WD bit bit 2 in FPFR Bit Initial value R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R ...

Page 619: ...tial Value R W Description 31 to 7 Undefined R W Unused Return 0 6 MD Undefined R W Programming Mode Related Setting Error Detect Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered When a low level signal is input to the FWE pin or the error protection state is entered 1 is written to this bit The input level to the FWE...

Page 620: ... Detect Returns the check result of the value of FKEY before the start of the programming processing 0 FKEY setting is normal FKEY H 5A 1 FKEY setting is error FKEY value other than H 5A 3 Undefined R W Unused Return 0 2 WD Undefined R W Write Data Address Error Detect When an address in the flash memory area is specified as the start address of the storage destination of the program data an error...

Page 621: ...his is set to the FEBS parameter general register R4 One block is specified from the block number 0 to 15 For details on the erasing procedure see section 17 5 2 User Program Mode Only in On Chip 128 Kbyte and 64 Kbyte ROM Version 4 1 Flash erase block select parameter FEBS general register R4 of CPU This parameter specifies the erase block number Several block numbers cannot be specified Bit Init...

Page 622: ...in the range from 0 to 8 0 corresponds to the EB0 block and 8 corresponds to the EB8 block An error occurs when a number other than 0 to 8 H 00 to H 08 is set 4 2 Flash pass fail result parameter FPFR general register R0 of CPU This parameter returns the value of the erasing processing result Bit Initial value R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 623: ... be performed 5 EE Undefined R W Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash memory related register settings are partially changed on returning from the user branch processing If this bit is set to 1 there is a high possibility that the user MAT is partially erased In this case after removing the error factor erase the user MAT 0 Er...

Page 624: ...B0243 0300 Bit Bit Name Initial Value R W Description 2 1 Undefined R W Unused Return 0 0 SF Undefined R W Success Fail Indicates whether the erasing processing has ended normally or not 0 Erasure has ended normally no error 1 Erasure has ended abnormally error occurs ...

Page 625: ...on chip SCI The tool for transmitting the control command and program data must be prepared in the host The SCI communication mode is set to asynchronous mode When reset start is executed after this LSI s pin is set in boot mode the boot program in the microcomputer is initiated After the SCI bit rate is automatically adjusted the communication with the host is executed by means of the control com...

Page 626: ...host and this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI To operate the SCI normally the transfer bit rate of the host must be set to 9 600 bps or 19 200 bps The system clock frequency which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 17 7 Boot mode must be initiated in ...

Page 627: ...gramming selected state To terminate programming H FFFFFFFF should be transmitted as the first address of the area for programming This makes the chip return to the programming erasure command waiting state from the programming data waiting state On receiving the erasure select command the chip waits for the block number of a block to be erased To erase a block the host transmits the erasure comma...

Page 628: ...cessing in response to read check command Wait for erasure block number Wait for programming data Transmission of programming data by the host Erasure block specification Reception of inquiry selection command Response to inquiry selection command Reception of read check command Response to command Programming complete Reception of programming select command Erasure complete Reception of erasure s...

Page 629: ...al must be released after the reset input period which is longer than the normal 100 µs For details on the programming procedure see the description in section 17 5 2 2 Programming Procedure in User Program Mode For details on the erasing procedure see the description in section 17 5 2 3 Erasing Procedure in User Program Mode When programming program data is prepared FWE 1 Programming erasing proc...

Page 630: ...hip RAM must be controlled so that these parts do not overlap Figure 17 10 shows the program area to be downloaded System use area 15 bytes RAMTOP H FFFFA000 FTDAR setting Programming erasing entry DPFR Return value 1 byte Area that can be used by user FTDAR setting 16 On chip RAM Address Initialization process entry FTDAR setting 32 FTDAR setting 3072 Initialization programming program or Initial...

Page 631: ... 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 1 1 2 3 Download Initialization Programming Start programming procedure program Figure 17 11 Programming Procedure The details of the programming procedure are described below The procedure program must be executed in an area other than the flash memory to be programmed Especially the part where the SCO bit in FCCS is set to 1 for downloading must ...

Page 632: ...setting the SCO bit to 1 To write 1 to the SCO bit the following conditions must be satisfied H A5 is written to FKEY The SCO bit writing is executed in the on chip RAM When the SCO bit is set to 1 download is started automatically When execution returns to the user procedure program the SCO bit is cleared to 0 Therefore the SCO bit cannot be confirmed to be 1 in the user procedure program The dow...

Page 633: ...AR If the value is H 00 download has been performed normally If the value is not H 00 the source that caused download to fail can be investigated by the description below If the value of the DPFR parameter is the same as before downloading e g H FF the address setting of the download destination in FTDAR may be abnormal In this case confirm the setting of the TDER bit bit 7 in FTDAR If the value o...

Page 634: ...teps MOV L DLTOP 32 R1 Set entry address to R1 JSR R1 Call initialization routine NOP The general registers other than R0 are saved in the initialization program R0 is a return value of the FPFR parameter Since the stack area is used in the initialization program a stack area of maximum 128 bytes must be reserved in RAM Interrupts can be accepted during the execution of the initialization program ...

Page 635: ...he general registers other than R0 are saved in the programming program R0 is a return value of the FPFR parameter Since the stack area is used in the programming program a stack area of maximum 128 bytes must be reserved in RAM 2 12 The return value in the programming program FPFR general register R0 is checked 2 13 Determine whether programming of the necessary data has finished If more than 128...

Page 636: ...or processing Yes Required block erasing is completed No Set FKEY to H 5A Clear FKEY to 0 3 1 3 2 3 3 3 4 3 5 3 6 1 1 Download Initialization Erasing Figure 17 12 Erasing Procedure The details of the erasing procedure are described below The procedure program must be executed in an area other than the user MAT to be erased Especially the part where the SCO bit in FCCS is set to 1 for downloading m...

Page 637: ... an erase block number of the user MAT is set no block is erased even though the erasing program is executed and an error is returned to the return value parameter FPFR 3 3 Erasure Similar to as in programming there is an entry point of the erasing program in the area from download start address set by FTDAR 16 bytes of on chip RAM The subroutine is called and erasing is executed by using the foll...

Page 638: ... Download Programming Erasure FWE pin protection The input of a low level signal on the FWE pin clears the FWE bit of FCCS and the LSI enters a programming erasing protected state Reset standby protection A power on reset including a power on reset by the WDT and entry to standby mode initializes the programming erasing interface registers and the LSI enters a programming erasing protected state R...

Page 639: ... protection is a mechanism for aborting programming or erasure when an error occurs in the form of the microcomputer getting out of control during programming erasing of the flash memory or operations that are not in accordance with the established procedures for programming erasing Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or er...

Page 640: ...ate transition diagram in figure 17 13 shows transitions to and from the error protection state Reset or standby Hardware protection Program mode Erase mode Error protection mode Error protection mode Software standby Read disabled Programming erasing enabled FLER 0 Read enabled Programming erasing disabled FLER 0 Read enabled Programming erasing disabled FLER 1 Read disabled Programming erasing d...

Page 641: ...in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover Operation when the SCO download request and interrupt request conflicts is described below 1 Contention between SCO download request and interrupt request Figure 17 14 shows the timing of contention between execution of the instruction that sets the SCO bit in FCCS to 1 and interrupt acceptance n n 1 n 2 n 3 n 4...

Page 642: ...new program data is to provided by the interrupt processing temporarily save the new program data in another area After confirming the completion of programming save the new program data in the area specified by FMPDR or change the setting in FMPDR to indicated the other area in which the new program data was temporarily saved 3 Make sure the interrupt processing routine does not rewrite the conte...

Page 643: ...ng phase also differs Table 17 10 lists the maximum interval for initiating the user branch processing when the CPU clock frequency is 50 MHz Table 17 10 Initiation Intervals of User Branch Processing Processing Name Maximum Interval Programming Approximately 4 ms Erasing Approximately 25 ms However when operation is done with CPU clock of 50 MHz maximum value of the time until first user branch p...

Page 644: ...gram by a SCO transfer request cannot run in this LSI Be sure to download the on chip program to execute programming erasing of flash memory in this LSI 5 Monitoring Runaway by WDT Unlike the conventional F ZTAT SH microcomputer no countermeasures are available for a runaway by WDT during programming erasing by the downloaded on chip program Prepare countermeasures e g use of the user branch routi...

Page 645: ...ate accordingly After bit rate matching is complete the boot program proceeds to the inquiry and selection state 2 Inquiry and selection state In this state the boot program responds to inquiry commands from the host The device clock mode and bit rate are selected in this state After making these selections the boot program enters the programming erasure state in response to the transition to prog...

Page 646: ...ction Bit rate matching state Inquiry and selection state Programming erasure state Figure 17 15 Flow of Processing by the Boot Program Bit rate matching state In bit rate matching the boot program measures the low level intervals in a signal carrying H 00 data that is transmitted by the host and calculates the bit rate from this The bit rate can be changed by the new bit rate selection command On...

Page 647: ...gle character used for an inquiry or the ACK code indicating normal completion 2 n character command or n character response A command or response that requires n bytes of data which is used as a selection command or response to an inquiry The length of programming data is treated separately below 3 Error response Response to a command in case of an error two bytes consisting of the error response...

Page 648: ... erasure checking etc Response 1 byte Response to an inquiry Size one or two bytes The length of data for transfer excluding the command response code size and checksum Data n bytes Particular data for the command or response Checksum 1 byte Set so that the total sum of byte values from the command code to the checksum and change lower one byte to H 00 Error response 1 byte Error response to a com...

Page 649: ...multiplier and divisor settings for the respective clocks and the values of the multipliers and divisors H 23 Inquiry on operating frequency Requests the minimum and maximum values for operating frequency of the main clock and peripheral clock H 25 Inquiry on user MATs Requests the number of user MAT areas along with their start and end addresses H 26 Inquiry on erasure blocks Requests the number ...

Page 650: ...he product names of their respective boot programs Command H 20 Command H 20 1 byte Inquiry on supported devices Response H 30 Size No of devices Number of characters Device code Product name SUM Response H 30 1 byte Response to the inquiry on supported devices Size 1 byte The length of data for transfer excluding the command code this field size and the checksum Here it is the total number of byt...

Page 651: ...ytes A device code that was returned in response to an inquiry on supported devices ASCII encoded SUM 1 byte Checksum Response H 06 Response H 06 1 byte Response to device selection This is the ACK code and is returned when the specified device code matches one of the supported devices Error response H 90 ERROR Error response H 90 1 byte Error response to device selection ERROR 1 byte Error code H...

Page 652: ... information on the selected clock mode in response to subsequent inquiries Command H 11 Size Mode SUM Command H 11 1 byte Clock mode selection Size 1 byte Number of characters in the clock mode field fixed at 1 Mode 1 byte A clock mode returned in response to the inquiry on clock modes SUM 1 byte Checksum Response H 06 Response H 06 1 byte Response to clock mode selection This is the ACK code and...

Page 653: ... of frequency types 1 byte The number of operating clocks for which multipliers can be selected for example if frequency multiplier settings can be made for the frequencies of the main and peripheral operating clocks the value should be H 02 Number of multipliers 1 byte The number of multipliers selectable for the operating frequency of the main or peripheral modules Multiplier 1 byte Multiplier N...

Page 654: ...f operating frequency fields Number of frequency types 1 byte The number of operating clock frequencies required within the device For example the value two indicates main and peripheral operating clock frequencies Minimum value of operating frequency 2 bytes The minimum frequency of a frequency multiplied or divided clock signal The value in this field and in the maximum value field is the freque...

Page 655: ...ber of areas and first and last address fields Number of areas 1 byte The number of user MAT areas H 01 is returned if the entire user MAT area is continuous First address of the area 4 bytes Last address of the area 4 bytes As many pairs of first and last address field are included as there are areas SUM 1 byte Checksum 8 Inquiry on erasure blocks In response to the inquiry on erasure blocks the ...

Page 656: ... Command H 27 Command H 27 1 byte Inquiry on programming size Response H 37 Size Programming size SUM Response H 37 1 byte Response to the inquiry on programming size Size 1 byte The number of characters in the programming size field fixed at 2 Programming size 2 bytes The size of the unit for programming This is the unit for the reception of data to be programmed SUM 1 byte Checksum 10 New bit ra...

Page 657: ... frequency and the operating frequency of the peripheral modules Multiplier 1 1 byte Multiplier or divisor for the main operating frequency Multiplier Numerical value of the frequency multiplier e g H 04 for 4 Divisor Two s complement negative numerical value in the case of frequency division e g H FE 2 for 1 2 Multiplier 2 1 byte Multiplier or divisor for the peripheral operating frequency Multip...

Page 658: ...s calculated from the received input frequency and the frequency multiplier or divisor The input frequency is the frequency of the clock signal supplied to the LSI while the operating frequency is the frequency at which the LSI is actually driven The following formulae are used for this calculation Operating frequency input frequency multiplier or Operating frequency input frequency divisor The ca...

Page 659: ... the new bit rate Acknowledge H 06 Acknowledge H 06 1 byte The ACK code sent by the host to acknowledge the new bit rate Response H 06 Response H 06 1 byte The ACK code transferred in response to acknowledgement of the new bit rate The sequence of new bit rate selection is shown in figure 17 18 Host Boot program New bit rate setting H 06 ACK H 06 ACK at the new bit rate H 06 ACK at the new bit rat...

Page 660: ... rate for the LSI by issuing the device selection command clock mode selection command new bit rate selection command and then initiate the transition to the programming erasure state by sending the corresponding command to the boot program Command H 40 Command H 40 1 byte Transition to programming erasure state Response H 06 Response H 06 1 byte Response to the transition to programming erasure s...

Page 661: ...ommand H 10 to select that device 3 Send the inquiry on clock mode command H 21 to get the available clock modes 4 Select a clock mode from among the returned clock modes and send the clock mode selection command H 11 5 After selection of the device and clock mode send the commands to inquire about frequency multipliers H 22 and operating frequencies H 23 to get the information required to select ...

Page 662: ...y H 4B Sum checking of user MAT Executes sum checking of the user MAT H 4D Blank checking of user MAT Executes blank checking of the user MAT H 4F Inquiry on boot program state Requests information on the state of boot processing Programming Programming is performed by issuing a programming selection command and the 128 byte programming command Firstly the host issues the programming selection com...

Page 663: ... 17 19 Sequence of Programming 1 Selection of user MAT programming In response to the command for selecting programming of the user MAT the boot program transfers the corresponding flash writing program i e the program for writing to the user MAT Command H 43 Command H 43 1 byte Selects programming of the user MAT Response H 06 Response H 06 1 byte Response to selection of user MAT programming Thi...

Page 664: ...ess where programming starts Specify an address on a 128 byte boundary Example H 00 H01 H 00 H 00 H 00010000 Programming data n bytes Data for programming The length of the programming data is the size returned in response to the programming size inquiry command SUM 1 byte Checksum Response H 06 Response H 06 1 byte Response to 128 byte programming The ACK code is returned on completion of the req...

Page 665: ...ogramming command with the address field H FFFFFFFF This informs the boot program that all data for the selected MAT have been sent the boot program then waits for the next programming erasure selection command Command H 50 Address for programming SUM Command H 50 1 byte 128 byte programming Address for programming 4 bytes Terminating code H FF H FF H FF H FF SUM 1 byte Checksum Response H 06 Resp...

Page 666: ...ic block To erase multiple blocks send further block erasure commands To terminate erasure the host should send a block erasure command with the block number H FF After this the boot program waits for the next programming erasure selection command The sequence of erasure by the erasure selection command and block erasure command is shown in figure 17 20 ACK Erasure H FF Erasure selection H 48 Eras...

Page 667: ... response H C8 1 byte Error response to selection of erasure ERROR 1 byte Error code H 54 Error in selection processing processing was not completed because of a transfer error 2 Block erasure In response to the block erasure command the boot program erases the data in a specified block of the user MAT Command H 58 Size Block number SUM Command H 58 1 byte Erasure of a block Size 1 byte The number...

Page 668: ...8 1 byte Erasure of a block Size 1 byte The number of characters in the block number field fixed at 1 Block number 1 byte H FF erasure terminating code SUM 1 byte Checksum Response H 06 Response H 06 1 byte ACK code to indicate response to the request for termination of erasure To perform erasure again after having issued the command with the block number specified as H FF execute the process from...

Page 669: ... as specified in the memory read command Data n bytes The specified amount of data read out from the specified address SUM 1 byte Checksum Error response H D2 ERROR Error response H D2 1 byte Error response to memory read command ERROR 1 byte Error code H 11 Sum check error H 2A Address error the address specified for reading is beyond the range of the MAT H 2B Size error the specified amount is g...

Page 670: ...AT 4 bytes Result of checksum calculation for the user MAT the total of all data in the MAT in byte units SUM 1 byte Checksum for the transmitted data Blank checking of the user MAT In response to the command for blank checking of the user MAT the boot program checks to see if the whole of the user MAT is blank the value returned indicates the result Command H 4D Command H 4D 1 byte Blank checking...

Page 671: ...characters in STATUS and ERROR fixed at 2 STATUS 1 byte State of the standard boot program See table 17 14 Status Codes ERROR 1 byte Error state indicates whether the program is in normal operation or an error has occurred ERROR 0 Normal ERROR 0 Error See table 17 15 Error Codes SUM 1 byte Checksum Table 17 14 Status Codes Code Description H 11 Waiting for device selection H 12 Waiting for clock m...

Page 672: ... section storable areas for the programming erasing procedure programs and program data are assumed to be in on chip RAM However the procedure programs and data can be executed in other areas as long as the following conditions are satisfied 1 The on chip programming erasing program is downloaded from the address set by FTDAR in on chip RAM therefore this area is not available for use 2 The on chi...

Page 673: ...red A reset state RES 0 for more than at least 100 µs must be taken when the LSI mode is changed to reset on completion of a programming erasing operation Transitions to the reset state during programming erasing are inhibited When the reset signal is accidentally input to the LSI a longer period in the reset state than usual 100 µs is needed before the reset signal is released 7 When the program ...

Page 674: ...register Writing 1 to SCO in FCCS download X Key register clearing Deciding download result Download error processing Setting initialization parameters Initialization X Deciding initialization result Initialization error processing Pro gram ming proce dure Interrupt processing routine X Writing H 5A to key register Setting programming parameters X Programming X Deciding programming result X Progra...

Page 675: ... to be downloaded Writing H A5 to key register Writing 1 to SCO in FCCS download X Key register clearing Deciding download result Download error processing Setting initialization parameters Initialization X Deciding initialization result Initialization error processing Interrupt processing routine X Erasing proce dure Writing H 5A to key register Setting erasure parameters X Erasure X Deciding era...

Page 676: ...B0243 0300 17 9 Off Board Programming Mode A PROM programmer can be used to perform programming erasing via a socket adapter just as for a discrete flash memory Use a PROM programmer that supports the Renesas 128 Kbyte flash memory on chip MCU device type F ZTAT128DV5 ...

Page 677: ...as shown in figure 18 1 The on chip RAM can be accessed from the CPU via the L bus An access from the L bus CPU is a 1 cycle access In addition the contents of the on chip RAM are retained in sleep mode or software standby mode and at a power on reset or manual reset The on chip RAM can be enabled or disabled by means of the RAME bit in the RAM control register RAMCR For details on the RAM control...

Page 678: ...itial value enables RAM operation RAM access is disabled by setting the module standby mode For details see section 19 Power Down Modes 18 1 2 Address Error When an address error in write access to the on chip RAM occurs the contents of the on chip RAM may be corrupted 18 1 3 Initial Values in RAM After power has been supplied initial values in RAM remain undefined until RAM is written ...

Page 679: ...ndby mode 19 1 Features Supports sleep mode software standby mode and module standby mode 19 1 1 Types of Power Down Modes This LSI has the following power down modes Sleep mode Software standby mode Module standby mode Table 19 1 shows the methods to make a transition from the program execution state as well as the CPU and peripheral module states in each mode and the procedures for canceling eac...

Page 680: ...bit in STBCR1 and STBYMD bit in STBCR6 set to 1 Halts Halts Held Halts contents retained Halt Interrupt by NMI or IRQ Power on reset by the RES pin Module standby Set MSTP bits in STBCR2 to STBCR5 to 1 Runs Runs Held Specified module halts contents retained Specified module halts Clear MSTP bit to 0 Power on reset for modules whose MSTP bit has an initial value of 0 Note For details on the states ...

Page 681: ...he power down modes For details on the addresses of these registers and the states of these registers in each processing state see section 20 List of Registers Table 19 3 Register Configuration Register Name Abbrevia tion R W Initial Value Address Access Size Standby control register 1 STBCR1 R W H 00 H FFFFE802 8 Standby control register 2 STBCR2 R W H 38 H FFFFE804 8 Standby control register 3 S...

Page 682: ...own mode Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R R R R R R R STBY Bit Bit Name Initial Value R W Description 7 STBY 0 R W Standby Specifies transition to software standby mode 0 Executing SLEEP instruction makes this LSI sleep mode 1 Executing SLEEP instruction makes this LSI software standby mode 6 to 0 All 0 R Reserved These bits are always read as 0 The write value should al...

Page 683: ...W R W R W R W R R R MSTP 7 Bit Bit Name Initial Value R W Description 7 MSTP7 0 R W Module Stop Bit 7 When this bit is set to 1 the supply of the clock to the RAM is halted 0 RAM operates 1 Clock supply to RAM halted 6 0 R W Reserved This bit is always read as 0 The write value should always be 0 5 to 3 All 1 R W Reserved These bits are always read as 1 The write value should always be 1 2 to 0 Al...

Page 684: ... are always read as 1 The write value should always be 1 5 MSTP13 1 R W Module Stop Bit 13 When this bit is set to 1 the supply of the clock to the SCI_2 is halted 0 SCI_2 operates 1 Clock supply to SCI_2 halted 4 MSTP12 1 R W Module Stop Bit 12 When this bit is set to 1 the supply of the clock to the SCI_1 is halted 0 SCI_1 operates 1 Clock supply to SCI_1 halted 3 MSTP11 1 R W Module Stop Bit 11...

Page 685: ...e should always be 1 6 MSTP22 1 R W Module Stop Bit 22 When this bit is set to 1 the supply of the clock to the MTU2 is halted 0 MTU2 operates 1 Clock supply to MTU2 halted 5 MSTP21 1 R W Module Stop Bit 21 When this bit is set to 1 the supply of the clock to the CMT is halted 0 CMT operates 1 Clock supply to CMT halted 4 3 All 1 R Reserved These bits are always read as 1 The write value should al...

Page 686: ...bit readable writable register that controls the operation of modules in power down mode Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 R R R R R R R W R W MSTP 25 24 Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 MSTP 25 24 11 R W Module Stop Bit 25 and 24 When either or both of these bits are set to...

Page 687: ... PC trace unit of UBC into the reset state 1 Releases reset in the PC trace unit of UBC 6 HIZ 0 R W Port High Impedance In software standby mode this bit selects whether the pin state is retained or changed to high impedance 0 In software standby mode the pin state is retained 1 In software standby mode the pin state is changed to high impedance 5 to 2 All 0 R Reserved These bits are always read a...

Page 688: ... 0 the access to the on chip RAM is disabled In this case an undefined value is returned when reading or fetching the data or instruction from the on chip RAM and writing to the on chip RAM is ignored When RAME is cleared to 0 to disable the on chip RAM an instruction to access the on chip RAM should not be set next to the instruction to write RAMCR If such an instruction is set normal access is n...

Page 689: ...eep mode Although the CPU halts immediately after executing the SLEEP instruction the contents of its internal registers remain unchanged The on chip peripheral modules continue to operate 19 4 2 Canceling Sleep Mode Sleep mode is canceled by a reset 1 Canceling with Reset Sleep mode is canceled by a power on reset with the RES pin a manual reset with the MRES pin or an internal power on manual re...

Page 690: ...dules are however initialized For details on the states of on chip peripheral module registers in software standby mode refer to section 20 3 Register States in Each Operating Mode For details on the pin states in software standby mode refer to appendix A Pin States The procedure for switching to software standby mode is as follows 1 Clear the TME bit in the timer control register WTCSR of the WDT...

Page 691: ...not accepted preventing software standby mode from being canceled When falling edge detection is selected for the NMI pin drive the NMI pin high before making a transition to software standby mode When rising edge detection is selected for the NMI pin drive the NMI pin low before making a transition to software standby mode Similarly when falling edge detection is selected for the IRQ pin drive th...

Page 692: ...andby function can be canceled by clearing the MSTP bits in STBCR2 to STBCR5 to 0 The module standby function can be canceled by a power on reset for modules whose MSTP bit has an initial value of 0 19 7 Usage Note 19 7 1 Current Consumption while Waiting for Oscillation to be Stabilized The current consumption while waiting for oscillation to be stabilized is higher than that while oscillation is...

Page 693: ...addresses are shown The list is classified according to module names The numbers of access cycles are given 2 Register Bit Table Bit configurations are shown in the order of the register address table As for reserved bits the bit name column is indicated with As for the blank column of the bit names the whole register is allocated to the counter or data As for 16 or 32 bit registers bits are indic...

Page 694: ..._0 SCSSR_0 8 H FFFFC008 8 Receive data register_0 SCRDR_0 8 H FFFFC00A 8 Serial direction control register_0 SCSDCR_0 8 H FFFFC00C 8 Serial port register_0 SCSPTR_0 8 H FFFFC00E 8 Serial mode register_1 SCSMR_1 8 H FFFFC080 SCI 8 Pφ reference Bit rate register_1 SCBRR_1 8 H FFFFC082 Channel 1 8 B 2 Serial control register_1 SCSCR_1 8 H FFFFC084 8 Transmit data register_1 SCTDR_1 8 H FFFFC086 8 Ser...

Page 695: ...e control register TGCR 8 H FFFFC20D 8 Timer output control register 1 TOCR1 8 H FFFFC20E 8 16 Timer output control register 2 TOCR2 8 H FFFFC20F 8 Timer counter_3 TCNT_3 16 H FFFFC210 16 32 Timer counter_4 TCNT_4 16 H FFFFC212 16 Timer cycle data register TCDR 16 H FFFFC214 16 32 Timer dead time data register TDDR 16 H FFFFC216 16 Timer general register A_3 TGRA_3 16 H FFFFC218 16 32 Timer genera...

Page 696: ...est cycle set register B_4 TADCORB_4 16 H FFFFC246 16 Timer A D converter start request cycle set buffer register A_4 TADCOBRA_4 16 H FFFFC248 16 32 Timer A D converter start request cycle set buffer register B_4 TADCOBRB_4 16 H FFFFC24A 16 Timer waveform control register TWCR 8 H FFFFC260 8 Timer start register TSTR 8 H FFFFC280 8 16 Timer synchronous register TSYR 8 H FFFFC281 8 Timer counter sy...

Page 697: ...r_1 TIER_1 8 H FFFFC384 8 16 32 Timer status register_1 TSR_1 8 H FFFFC385 8 Timer counter_1 TCNT_1 16 H FFFFC386 16 Timer general register A_1 TGRA_1 16 H FFFFC388 16 32 Timer general register B_1 TGRB_1 16 H FFFFC38A 16 Timer input capture control register TICCR 8 H FFFFC390 8 Timer control register_2 TCR_2 8 H FFFFC400 8 16 Timer mode register_2 TMDR_2 8 H FFFFC401 8 Timer I O control register_...

Page 698: ... 8 A D data register 0 ADDR0 16 H FFFFC900 A D 16 Pφ reference A D data register 1 ADDR1 16 H FFFFC902 Channel 0 16 B 2 W 2 A D data register 2 ADDR2 16 H FFFFC904 16 A D data register 3 ADDR3 16 H FFFFC906 16 A D control status register_0 ADCSR_0 16 H FFFFC910 16 A D control register_0 ADCR_0 16 H FFFFC912 16 A D data register 4 ADDR4 16 H FFFFC980 A D 16 Pφ reference A D data register 5 ADDR5 16...

Page 699: ... output enable register SPOER 8 H FFFFD00A 8 Port output enable control register 1 POECR1 8 H FFFFD00B 8 Port output enable control register 2 POECR2 16 H FFFFD00C 8 16 Port A data register L PADRL 16 H FFFFD102 I O 8 16 Port A I O register L PAIORL 16 H FFFFD106 PFC 8 16 Pφ reference B 2 W 2 L 4 Port A control register L4 PACRL4 16 H FFFFD110 8 16 32 Port A control register L3 PACRL3 16 H FFFFD11...

Page 700: ...register 2 STBCR2 8 H FFFFE804 Power down modes 8 B 2 Standby control register 3 STBCR3 8 H FFFFE806 8 Standby control register 4 STBCR4 8 H FFFFE808 8 Standby control register 5 STBCR5 8 H FFFFE80A 8 Standby control register 6 STBCR6 8 H FFFFE80C 8 Watchdog timer counter WTCNT 8 H FFFFE810 8 1 16 2 Watchdog timer control status register WTCSR 8 H FFFFE812 WDT 1 Read 2 Write 8 1 16 2 Pφ reference ...

Page 701: ...ister L IPRL 16 H FFFFE992 16 Interrupt priority register M IPRM 16 H FFFFE994 16 Break address register A BARA 32 H FFFFF300 UBC 32 Bφ reference Break address mask register A BAMRA 32 H FFFFF304 32 B 2 W 2 L 2 Break bus cycle register A BBRA 16 H FFFFF308 16 Break data register A BDRA 32 H FFFFF310 32 Break data mask register A BDMRA 32 H FFFFF314 32 Break address register B BARB 32 H FFFFF320 32...

Page 702: ...OP MP CKS 1 0 SCBRR_0 SCSCR_0 TIE RIE TE RE MPIE TEIE CKE 1 0 SCTDR_0 SCSSR_0 TDRE RDRF ORER FER PER TEND MPB MPBT SCI Channel 0 SCRDR_0 SCSDCR_0 DIR SCSPTR_0 EIO SPB1IO SPB1DT SPB0IO SPB0DT SCSMR_1 C A CHR PE O E STOP MP CKS 1 0 SCBRR_1 SCSCR_1 TIE RIE TE RE MPIE TEIE CKE 1 0 SCTDR_1 SCSSR_1 TDRE RDRF ORER FER PER TEND MPB MPBT SCI Channel 1 SCRDR_1 SCSDCR_1 DIR SCSPTR_1 EIO SPB1IO SPB1DT SPB0IO ...

Page 703: ...0 TCR_4 CCLR 2 0 CKEG 1 0 TPSC 2 0 TMDR_3 BFB BFA MD 3 0 TMDR_4 BFB BFA MD 3 0 MTU2 TIORH_3 IOB 3 0 IOA 3 0 TIORL_3 IOD 3 0 IOC 3 0 TIORH_4 IOB 3 0 IOA 3 0 TIORL_4 IOD 3 0 IOC 3 0 TIER_3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TIER_4 TTGE TTGE2 TCIEV TGIED TGIEC TGIEB TGIEA TOER OE4D OE4C OE3D OE4B OE4A OE3B TGCR BDC N P FB WF VF UF TOCR1 PSYE TOCL TOCS OLSN OLSP TOCR2 BF 1 0 OLS3N OLS3P OLS2N OLS2P OL...

Page 704: ... Bit 24 16 8 0 Module MTU2 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TCFD TCFV TGFD TGFC TGFB TGFA TSR_4 TCFD TCFV TGFD TGFC TGFB TGFA TITCR T3AEN 3ACOR 2 0 T4VEN 4VCOR 2 0 TITCNT 3ACNT 2 0 4VCNT 2 0 TBTER BTE 1 0 TDER TDER TOLBR OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P TBTM_3 TTSB TTSA TBTM_4 TTSB TTSA BF 1 0 TADCR UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE TADCORA_4 TADCORB_4 TADCOBRA_4 T...

Page 705: ...ST2 CST1 CST0 TSYR SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCSYSTR SCH0 SCH1 SCH2 SCH3 SCH4 TRWER RWE MTU2 TCR_0 CCLR 2 0 CKEG 1 0 TPSC 2 0 TMDR_0 BFE BFB BFA MD 3 0 TIORH_0 IOB 3 0 IOA 3 0 TIORL_0 IOD 3 0 IOC 3 0 TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFV TGFD TGFC TGFB TGFA TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TTGE2 TGIEF TGIEE TSR2_0 TGFF TGFE TBTM_0 TTSE TTSB TTSA TCR_1 CCL...

Page 706: ... 2 Bit 25 17 9 1 Bit 24 16 8 0 Module TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA TSR_1 TCFD TCFU TCFV TGFB TGFA TCNT_1 TGRA_1 TGRB_1 MTU2 TICCR I2BE I2AE I1BE I1AE TCR_2 CCLR 1 0 CKEG 1 0 TPSC 2 0 TMDR_2 MD 3 0 TIOR_2 IOB 3 0 IOA 3 0 TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA TSR_2 TCFD TCFU TCFV TGFB TGFA TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TPSC 1 0 TIORU_5 IOC 4 0 TCNTV_5 TGRV_5 TCRV_5 TPSC 1 0 ...

Page 707: ...V TGIE5W TSTR_5 CSTU5 CSTV5 CSTW5 TCNTCMPCLR CMPCLR5U CMPCLR5V CMPCLR5W AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR0 AD1 AD0 A D Channel 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR1 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR2 AD1 AD0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR3 AD1 AD0 ADF ADIE TRGE CONADF STC ADCSR_0 CKSL 1 0 ADM 1 0 ADCS CH 2 0 ADST ADCR_0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDR4 AD1 AD0 A D Channe...

Page 708: ...8 0 Module ADF ADIE TRGE CONADF STC ADCSR_1 CKSL 1 0 ADM 1 0 ADCS CH 2 0 A D Channel 1 ADST ADCR_1 FCCS FWE FLER SCO FLASH FPCS PPVS FECS EPVB FKEY K 7 0 FTDAR TDER TDA 6 0 CMT CMSTR STR1 STR0 CMCSR_0 CMF CMIE CKS 1 0 CMCNT_0 CMCOR_0 CMCSR_1 CMF CMIE CKS 1 0 CMCNT_1 CMCOR_1 POE3F POE1F POE0F PIE1 POE ICSR1 POE3M 1 0 POE1M 1 0 POE0M 1 0 OSF1 OCE1 OIE1 OCSR1 POE8F POE8E PIE3 ICSR3 POE8M 1 0 SPOER MT...

Page 709: ...124 PA7IOR PA6IOR PA4IOR PA3IOR PA1IOR PA0IOR PA15MD2 PA15MD1 PA15MD0 PA14MD2 PA14MD1 PA14MD0 PACRL4 SH7125 PA13MD2 PA13MD1 PA13MD0 PA12MD2 PA12MD1 PA12MD0 PACRL4 SH7124 PA11MD2 PA11MD1 PA11MD0 PA10MD2 PA10MD1 PA10MD0 PACRL3 SH7125 PA9MD2 PA9MD1 PA9MD0 PA8MD2 PA8MD1 PA8MD0 PACRL3 SH7124 PA9MD2 PA9MD1 PA9MD0 PA8MD2 PA8MD1 PA8MD0 PA7MD2 PA7MD1 PA7MD0 PA6MD2 PA6MD1 PA6MD0 PACRL2 SH7125 PA5MD2 PA5MD1 ...

Page 710: ...25 PB16DR PBDRH SH7124 PBDRL SH7125 PB5DR PB3DR PB2DR PB1DR PBDRL SH7124 PB5DR PB3DR PB1DR PFC PBIORH SH7125 PB16IOR PBIORH SH7124 PBIORL SH7125 PB5IOR PB3IOR PB2IOR PB1IOR PBIORL SH7124 PB5IOR PB3IOR PB1IOR PBCRH1 SH7125 PB16MD PBCRH1 SH7124 PBCRL2 SH7125 PB5MD2 PB5MD1 PB5MD0 PBCRL2 SH7124 PB5MD2 PB5MD1 PB5MD0 PB3MD2 PB3MD1 PB3MD0 PB2MD2 PB2MD1 PB2MD0 PBCRL1 SH7125 PB1MD2 PB1MD1 PB1MD0 PB3MD2 PB3...

Page 711: ...PE9IOR PE8IOR PFC PEIORL SH7125 PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR PEIORL SH7124 PE3IOR PE2IOR PE1IOR PE0IOR PE15MD2 PE15MD1 PE15MD0 PE14MD2 PE14MD1 PE14MD0 PECRL4 PE13MD1 PE13MD0 PE12MD2 PE12MD1 PE12MD0 PE11MD2 PE11MD1 PE11MD0 PE10MD2 PE10MD1 PE10MD0 PECRL3 PE9MD2 PE9MD1 PE9MD0 PE8MD2 PE8MD1 PE8MD0 PE7MD2 PE7MD1 PE...

Page 712: ...1 0 MPFC 2 0 STBCR1 STBY STBCR2 MSTP7 Power down modes STBCR3 MSTP13 MSTP12 MSTP11 STBCR4 MSTP22 MSTP21 MSTP17 MSTP16 STBCR5 MSTP 25 24 STBCR6 UBCRST HIZ STBYMD WTCNT WDT WTCSR TME WT IT RSTS WOVF IOVF CKS 2 0 OSCCR OSCSTOP OSCERS CPG RAMCR RAME Power down modes TRG11S 3 0 TRG01S 3 0 A D ADTSR_0 TRG1S 3 0 TRG0S 3 0 NMIL NMIE INTC ICR0 IRQCR IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S I...

Page 713: ...4 IPRF MTU2_5 MTU2_5 MTU2_5 MTU2_5 POE MTU2 POE MTU2 POE MTU2 POE MTU2 IPRH IPRI CMT_0 CMT_0 CMT_0 CMT_0 CMT_1 CMT_1 CMT_1 CMT_1 IPRJ WDT WDT WDT WDT A D_0 1 A D_0 1 A D_0 1 A D_0 1 IPRK SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 IPRL SCI_2 SCI_2 SCI_2 SCI_2 IPRM BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 UBC BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 B...

Page 714: ...BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BARB BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 BAMRB BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 CPB 2 0 BBRB CDB 1 0 IDB 1 0 RWB 1 0 SZB ...

Page 715: ... Bit 25 17 9 1 Bit 24 16 8 0 Module SVF BSA27 BSA26 BSA25 BSA24 UBC BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BRSR BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 DVF BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BRDR BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 BET 11 8 BETR BET 7 0 ...

Page 716: ...alized Retained Initialized Initialized Retained SCSSR_1 Initialized Retained Initialized Initialized Retained SCRDR_1 Initialized Retained Initialized Initialized Retained SCSDCR_1 Initialized Retained Initialized Initialized Retained SCSPTR_1 Initialized Retained Initialized Initialized Retained SCI Channel 1 SCSMR_2 Initialized Retained Initialized Initialized Retained SCBRR_2 Initialized Retai...

Page 717: ...etained Initialized Initialized Retained TGRA_3 Initialized Retained Initialized Initialized Retained TGRB_3 Initialized Retained Initialized Initialized Retained TGRA_4 Initialized Retained Initialized Initialized Retained TGRB_4 Initialized Retained Initialized Initialized Retained TCNTS Initialized Retained Initialized Initialized Retained TCBR Initialized Retained Initialized Initialized Retai...

Page 718: ...Retained Initialized Initialized Retained TIORH_0 Initialized Retained Initialized Initialized Retained TIORL_0 Initialized Retained Initialized Initialized Retained TIER_0 Initialized Retained Initialized Initialized Retained TSR_0 Initialized Retained Initialized Initialized Retained TCNT_0 Initialized Retained Initialized Initialized Retained TGRA_0 Initialized Retained Initialized Initialized ...

Page 719: ... Initialized Initialized Retained TGRB_2 Initialized Retained Initialized Initialized Retained TCNTU_5 Initialized Retained Initialized Initialized Retained TGRU_5 Initialized Retained Initialized Initialized Retained TCRU_5 Initialized Retained Initialized Initialized Retained TIORU_5 Initialized Retained Initialized Initialized Retained TCNTV_5 Initialized Retained Initialized Initialized Retain...

Page 720: ...DCR_1 Initialized Retained Initialized Initialized Retained FCCS Initialized Retained Initialized Initialized Retained FLASH FPCS Initialized Retained Initialized Initialized Retained FECS Initialized Retained Initialized Initialized Retained FKEY Initialized Retained Initialized Initialized Retained FTDAR Initialized Retained Initialized Initialized Retained CMSTR Initialized Retained Initialized...

Page 721: ... Initialized Retained Retained Retained PBCRL2 Initialized Retained Retained Retained PBCRL1 Initialized Retained Retained Retained PBPRH Initialized Retained Retained Retained I O PBPRL Initialized Retained Retained Retained PEDRL Initialized Retained Retained Retained PEIORL Initialized Retained Retained Retained PFC PECRL4 Initialized Retained Retained Retained PECRL3 Initialized Retained Retai...

Page 722: ...tialized Initialized Retained Retained IPRC Initialized Initialized Retained Retained IPRD Initialized Initialized Retained Retained IPRE Initialized Initialized Retained Retained IPRF Initialized Initialized Retained Retained IPRH Initialized Initialized Retained Retained IPRI Initialized Initialized Retained Retained IPRJ Initialized Initialized Retained Retained IPRK Initialized Initialized Ret...

Page 723: ...ned UBC BDMRB Initialized Retained Retained Initialized Retained BRCR Initialized Retained Retained Initialized Retained BRSR Initialized Retained Retained Initialized Retained BRDR Initialized Retained Retained Initialized Retained BETR Initialized Retained Retained Initialized Retained Notes 1 Not initialized by a WDT power on reset 2 The OSCSTOP bit is not initialized by a WDT power on reset 3 ...

Page 724: ...Section 20 List of Registers Rev 3 00 Sep 27 2007 Page 704 of 758 REJ09B0243 0300 ...

Page 725: ...ings Table 21 1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC 0 3 to 7 0 V Input voltage except analog input Vin 0 3 to VCC 0 3 V Analog power supply voltage AVCC 0 3 to 7 0 V Analog reference voltage AVref 0 3 to AVCC 0 3 V Analog input voltage Van 0 3 to AVCC 0 3 V Operating temperature Consumer specifications Topr 20 to 85 C Industrial specifications 40 to 85 C Storag...

Page 726: ...igh level voltage other than Schmitt trigger input voltage Other input pins 2 2 VCC 0 3 V RES MRES NMI FWE MD1 ASEMD0 EXTAL 0 3 0 5 V Input low level voltage other than Schmitt trigger input voltage Other input pins VIL 0 3 0 8 V VT VCC 0 5 V VT 1 0 V Schmitt trigger input voltage IRQ3 to IRQ0 POE8 POE3 POE1 POE0 TCLKA to TCLKD TIOC0A to TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A to TIOC3D TIOC4A t...

Page 727: ...other output pins VOL 0 4 V IOL 1 6 mA Input capacitance All input pins Cin 20 pF Vin 0 V f 1 MHz Ta 25 C Normal operation 52 70 mA Iφ 50 MHz Sleep 33 50 mA Iφ 50 MHz 5 mA Ta 50 C Supply current Software standby ICC 15 mA 50 C Ta During A D conversion 3 5 mA The value per module Waiting for A D conversion 2 mA The value per module Analog power supply current Standby AICC 15 µA Operating Precaution...

Page 728: ... Permissible current in low level output per pin IOL 2 0 mA Permissible current in low level output total Σ IOL 80 mA Permissible current in high level output per pin IOH 2 0 mA Permissible current in high level output total Σ IOH 25 mA Operating Precautions To assure LSI reliability do not exceed the output values listed in table 21 3 Note IOL 15 mA Max IOH 5 mA Max for pins PE9 and PE11 to PE15 ...

Page 729: ...gnals in synchronization with a clock The setup and hold times for input pins must be followed Table 21 4 Maximum Operating Frequency Conditions VCC AVCC 4 0 V to 5 5 V VSS PLLVSS AVSS 0 V Ta 20 to 85 C consumer specifications Ta 40 to 85 C industrial specifications Item Symbol Min Typ Max Unit Remarks CPU Iφ 10 50 Operating frequency Peripheral module Pφ f 10 40 MHz ...

Page 730: ... EXTAL clock input high pulse width tEXH 20 ns EXTAL clock input rising time tEXr 5 ns EXTAL clock input falling time tEXf 5 ns Figure 21 1 CK Bφ clock frequency reference values fOP 10 40 MHz CK Bφ clock cycle time reference values tcyc 25 100 ns Power on oscillation stabilization time tOSC1 10 ms Figure 21 2 Oscillation stabilization time on return from standby 1 tOSC2 10 ms Figure 21 3 Oscillat...

Page 731: ...zation Time Standby period tOSC2 tRESW tMRESW RES MRES CK internal clock Oscillation stabilized Note Oscillation stabilization time when the on chip oscillator is in use Figure 21 3 Oscillation Stabilization Time on Return from Standby Return by Reset Standby period CK internal clock Oscillation stabilized Note Oscillation stabilization time when the on chip oscillator is in use tOSC3 NMI IRQ Figu...

Page 732: ...time reference values tMRESH 15 ns Figures 21 2 21 3 21 5 21 6 MD1 FWE setup time tMDS 20 tBcyc 4 Figure 21 5 NMI setup time 1 reference values tNMIS 60 ns Figure 21 6 NMI hold time reference values tNMIH 10 ns IRQ3 to IRQ0 setup time 1 reference values tIRQS 35 ns IRQ3 to IRQ0 hold time reference values tIRQH 35 ns IRQOUT output delay time reference values tIRQOD 100 ns Figure 21 7 Notes 1 The RE...

Page 733: ...of 758 REJ09B0243 0300 tRESS tMDS tRESS tRESW CK MD1 FWE RES MRES tMRESW tMRESS tMRESS Figure 21 5 Reset Input Timing CK RES tRESH tRESS VIH VIL MRES tMRESH tMRESS VIH VIL NMI tNMIH tNMIS VIH VIL IRQ3 to IRQ0 tIRQH tIRQS VIH VIL Figure 21 6 Interrupt Signal Input Timing ...

Page 734: ...Section 21 Electrical Characteristics Rev 3 00 Sep 27 2007 Page 714 of 758 REJ09B0243 0300 tIRQOD tIRQOD CK IRQOUT Figure 21 7 Interrupt Signal Output Timing ...

Page 735: ...erence values tTOCD 50 ns Figure 21 8 Input capture input setup time reference values tTICS 20 ns Input capture input pulse width single edge tTICWH L 1 5 tMPcyc Input capture input pulse width both edges tTICWH L 2 5 tMPcyc Timer input setup time reference values tTCKS 20 ns Figure 21 9 Timer clock pulse width single edge tTCKWH L 1 5 tMPcyc Timer clock pulse width both edges tTCKWH L 2 5 tMPcyc ...

Page 736: ...Section 21 Electrical Characteristics Rev 3 00 Sep 27 2007 Page 716 of 758 REJ09B0243 0300 CK TCLKA to TCLKD tTCKS tTCKS tTCKWH tTCKWL Figure 21 9 MTU2 Clock Input Timing ...

Page 737: ...5 V VSS PLLVSS AVSS 0 V Ta 20 to 85 C consumer specifications Ta 40 to 85 C industrial specifications Item Symbol Min Max Unit Reference Figure Port output data delay time reference values tPWD 50 ns Figure 21 10 Port input low pulse width tPRWL 2 tPcyc Port input high pulse width tPRWH 2 tPcyc tPRWH L tPWD CK Port read Port write Figure 21 10 I O Port Input Output Timing ...

Page 738: ...ing Table 21 9 Watchdog Timer WDT Timing Conditions VCC AVCC 4 0 V to 5 5 V VSS PLLVSS AVSS 0 V Ta 20 to 85 C consumer specifications Ta 40 to 85 C industrial specifications Item Symbol Min Max Unit Reference Figure WDTOVF delay time reference values tWOVD 50 ns Figure 21 11 tWOVD tWOVD CK WDTOVF Figure 21 11 WDT Timing ...

Page 739: ...clock cycle clock synchronous tscyc 6 tpcyc Figure 21 12 Input clock pulse width tsckw 0 4 0 6 tscyc Input clock rising time tsckr 1 5 tpcyc Input clock falling time tsckf 1 5 tpcyc Transmit data delay time tTXD 4 tpcyc 10 ns Receive data setup time tRXS 4 tpcyc ns Receive data hold time Asynchronous tRXH 4 tpcyc ns Transmit data delay time tTXD 3 tpcyc 10 ns Receive data setup time tRXS 2 tpcyc 5...

Page 740: ... SCK0 to SCK2 input output TXD0 to TXD2 transmit data RXD0 to RXD2 receive data SCI input output timing clock synchronous mode tTXD tRXS tRXH T1 CK TXD0 to TXD2 transmit data RXD0 to RXD2 receive data SCI input output timing asynchronous mode Tn tTXD tRXS tRXH Figure 21 13 SCI Input Output Timing ...

Page 741: ...tions VCC AVCC 4 0 V to 5 5 V VSS PLLVSS AVSS 0 V Ta 20 to 85 C consumer specifications Ta 40 to 85 C industrial specifications Item Symbol Min Max Unit Reference Figure POE input setup time reference values tPOES 50 ns Figure 21 14 POE input pulse width tPOEW 1 5 tpcyc Note tpcyc indicates the peripheral clock Pφ cycle CK POEn input tPOES tPOEW Figure 21 14 POE Input Timing ...

Page 742: ...nverter Timing Conditions VCC AVCC 4 0 V to 5 5 V VSS PLLVSS AVSS 0 V Ta 20 to 85 C consumer specifications Ta 40 to 85 C industrial specifications Item Symbol Min Typ Max Unit Reference Figure External trigger input start delay time reference values tTRGS 25 ns Figure 21 15 CK ADTRG input tTRGS Figure 21 15 External Trigger Input Timing ...

Page 743: ... Max VIH Min Output signal reference level 2 0 V high level 0 8 V low level IOL IOH CL VREF LSI output pin DUT output Notes CL is the total value that includes the capacitance of the measurement instrument and is set as follows for the respective pins 30pF All other output pins IOL 1 6 mA and IOH 200 mA in the test conditions 1 2 Figure 21 16 Output Load Circuit ...

Page 744: ...tions Ta 40 to 85 C industrial specifications Item Min Typ Max Unit Resolution 10 10 10 bit A D conversion time 2 0 µs Analog input capacitance 20 pF Permitted analog signal source impedance 1 2 3 1 kΩ Non linear error 3 0 1 5 0 2 LSB Offset error 3 0 1 5 0 2 LSB Full scale error 3 0 1 5 0 2 LSB Quantization error 0 5 LSB Absolute error 4 0 1 6 0 2 LSB Notes 1 It is assumed that A D conversion tim...

Page 745: ... 4 tE 600 1500 ms 64 Kbytes block 1 2 3 s 128 Kbytes Programming time total 1 2 4 Σ tP 0 6 1 5 s 64 Kbytes 1 3 3 5 s 128 Kbytes Erase time total 1 2 4 Σ tE 0 7 2 s 64 Kbytes 2 5 6 5 s 128 Kbytes Programming and erase time total 1 2 4 Σ tPE 1 3 3 5 s 64 Kbytes Reprogramming count NWEC 100 3 Times Notes 1 Programming erasure time is data dependent 2 Programming erasure time does not include data tra...

Page 746: ...stabilizing the internal voltage needs to be connected Connection of the external capacitor is shown in figure 21 17 The external capacitor should be located near the pin Do not apply any power supply voltage to the VCL pin One capacitor ranging from 0 1 to 0 47 µF One capacitor ranging from 0 1 to 0 47 µF External power supply stabilizing capacitor Do not apply any power supply voltage to the VCL...

Page 747: ...O O O Clock EXTAL I I I I I I RES I I I I I I MRES Z I Z I Z I System control WDTOVF O 2 O O O O O MD1 I I I I I I ASEMD0 I 3 I 3 I 3 I 3 I 3 I 3 Operating mode control FWE I I I I I I NMI I I I I I I IRQ0 to IRQ3 Z I I I I I Interrupt IRQOUT Z O Z O Z O MTU2 TCLKA to TCLKD Z I Z I I I TIOC0A to TIOC0D Z I O K 1 I O I O Z TIOC1A TIOC1B Z I O K 1 I O I O I O TIOC2A TIOC2B Z I O K 1 I O I O I O TIOC...

Page 748: ...o PB3 PB5 PB16 Z I O K 1 I O I O I O PE0 to PE3 Z I O K 1 I O I O Z PE4 to PE8 PE10 Z I O K 1 I O I O I O PE9 PE11 to PE15 Z I O Z I O Z Z PF0 to PF7 Z I Z I I I Legend I Input O Output H High level output L Low level output Z High impedance K Input pins become high impedance and output pins retain their state Notes 1 Output pins become high impedance when the HIZ bit in standby control register 6...

Page 749: ... WDTOVF O 2 O O O O O MD1 I I I I I I ASEMD0 I 3 I 3 I 3 I 3 I 3 I 3 Operating mode control FWE I I I I I I NMI I I I I I I IRQ1 to IRQ3 Z I I I I I Interrupt IRQOUT Z O Z O Z O MTU2 TCLKA to TCLKD Z I Z I I I TIOC0A to TIOC0D Z I O K 1 I O I O Z TIOC3A TIOC3C Z I O K 1 I O I O I O TIOC3B TIOC3D Z I O Z I O Z Z TIOC4A to TIOC4D Z I O Z I O Z Z TIC5U TIC5V TIC5W Z I Z I I I POE POE0 POE1 POE8 Z I Z...

Page 750: ... Z PE8 PE10 Z I O K 1 I O I O I O PE9 PE11 to PE15 Z I O Z I O Z Z PF0 to PF7 Z I Z I I I Legend I Input O Output H High level output L Low level output Z High impedance K Input pins become high impedance and output pins retain their state Notes 1 Output pins become high impedance when the HIZ bit in standby control register 6 STBCR6 is set to 1 2 Becomes input during a power on reset Pull up to p...

Page 751: ...l product R5F71252D50FP LQFP 64 FP 64K Consumer product R5F71252N50FA SH7125 Flash memory version on chip 64 kbyte Industrial product R5F71252D50FA QFP 64 FP 64H Consumer product R5F71243N50FP Flash memory version on chip 128 kbyte Industrial product R5F71243D50FP LQFP 48 FP 48F Consumer product R5F71242N50FP Industrial product R5F71242D50FP Consumer product R5F71242N50NP VQFN 52 Flash memory vers...

Page 752: ... p H E E H D D Z D Z E Detail F A c A 2 A 1 L 1 L P LQFP64 10x10 0 50 0 3g MASS Typ 64P6Q A FP 64K FP 64KV PLQP0064KB A RENESAS Code JEITA Package Code Previous Code 1 0 0 125 0 18 1 25 1 25 0 08 0 20 0 145 0 09 0 25 0 20 0 15 Max Nom Min Dimension in Millimeters Symbol Reference 10 1 10 0 9 9 D 10 1 10 0 9 9 E 1 4 A 2 12 2 12 0 11 8 12 2 12 0 11 8 1 7 A 0 15 0 1 0 05 0 65 0 5 0 35 L x 8 0 c 0 5 e...

Page 753: ... c A A L A L Terminal cross section p 1 1 c b c b PRQP0064GB A P QFP64 14x14 0 80 0 8 1 0 1 0 0 15 0 10 8 0 0 25 0 10 0 15 0 35 0 00 0 45 0 37 0 29 0 22 0 17 0 12 3 05 16 9 17 2 17 5 D 1 E D 1 1 p 1 E D 2 L Z Z y x c b b A H A E A c e e L H 1 2g MASS Typ FP 64H FP 64HV RENESAS Code JEITA Package Code Previous Code 1 1 0 8 0 5 Max Nom Min Dimension in Millimeters Symbol Reference 14 2 70 17 5 17 2 ...

Page 754: ...5 FP 48F FP 48FV RENESAS Code JEITA Package Code Previous Code Max Nom Min Dimension in Millimeters Symbol Reference 0 4g MASS Typ 1 E D 1 1 p 1 E D 2 L Z Z y x c b b A H A E D A c e e L H Index mark 1 2 3 y M x F 48 1 12 13 37 36 24 25 D E D E p b Z Z H H D E Detail F 1 1 2 c A L A L A 1 1 p Terminal cross section b c c b θ θ NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES ...

Page 755: ... 0 20 0 4 1 0 1 0 8 0 8 0 0 05 0 23 0 18 0 13 t y 1 L p y x b 1 b A A 2 E D A 1 e c 1 H D c H E 0 89 0 005 0 02 0 04 0 50 0 70 0 17 0 25 Z D Z E 2 1 64 49 32 17 48 33 16 x n b 1 p 1 c E D D E 1 y x4 t y 1 b L e c A A A Z Z H E H D P VQFN64 8x8 0 40 0 12g MASS Typ TNP 64B TNP 64BV PVQN0064LB A RENESAS Code JEITA Package Code Previous Code Figure C 4 VQFN 64 ...

Page 756: ...0 18 0 23 0 05 7 0 7 0 1 1 1 1 0 4 0 20 7 2 7 2 Max Nom Min Dimension in Millimeters Symbol Reference 0 22 0 20 0 20 0 05 0 16 0 60 0 95 0 89 0 005 0 02 0 04 0 50 0 70 0 17 0 25 1 2 26 14 40 39 27 13 p 1 c E D D E 1 52 1 b y n x x4 t y 1 1 2 A A A Z Z b e H D H E L c P VQFN52 7x7 0 40 0 095g MASS Typ PVQN0052LE A RENESAS Code JEITA Package Code Previous Code Figure C 5 VQFN 52 ...

Page 757: ...on T Bit SUBV Rm Rn Underflow Table 2 12 Arithmetic Operation Instructions 40 4 1 Features 55 Deleted Five clocks generated independently An internal clock If for the CPU and cache a peripheral clock Pf for the on chip peripheral modules a bus clock Bf CK for the external bus interface and a MTU2 clock MPf for the on chip MTU2 module Table 4 4 Frequency Division Ratios Specifiable with FRQCR 60 De...

Page 758: ...fied subsequent operation is not guaranteed 8 to 6 PFC 2 0 Peripheral Clock Pφ Frequency Division Ratio If a prohibited value is specified subsequent operation is not guaranteed 2 to 0 MPFC 2 0 MTU2 Clock MPφ Frequency Division Ratio If a prohibited value is specified subsequent operation is not guaranteed 4 4 1 Frequency Control Register FRQCR 62 63 4 5 Changing Frequency 65 Added Deleted 4 The c...

Page 759: ...32 Amended This flag bit is cleared to 0 by a power on reset or manual reset when BRSR is read or the setting to enable PC trace is made or BRSR is initialized by a power on reset 7 2 14 Branch Destination Register BRDR 133 Amended This flag bit is cleared to 0 by a power on reset or manual reset when BRDR is read or the setting to enable PC trace is made or BRSR is initialized by a power on reset...

Page 760: ...al I O Register 149 Amended In the case shown in figure 8 2 where Bclk Pclk 1 1 the timeperiod required for access by the CPU is 13 n Iclk 1 Bclk 2 Pclk Figure 8 2 Timing of Write Access to the Peripheral Bus Iclk Bclk Pclk 4 4 1 149 Amended L bus Bclk I bus 8 4 Access to on chip Peripheral I O Register 149 150 Added Figure 8 3 shows an example of timing of read access to the peripheral bus when I...

Page 761: ...Description Bit 4 IOC4 TGRU_5 TGRV_5 and TGRW_5 Function TIC5U TIC5V and TIC5W Pin Function 1 Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Capture at trough in complementary PWM mode Input capture register Capture at trough in complementary PWM mode Table 9 28 TIORU_5 ...

Page 762: ...trigger This function allows reading of the 32 bit counter such that TCNT_1 and TCNT_2 are captured at the same time 10 6 1 Pin State when a Power On Reset is Issued from the Watchdog Timer 400 Added When a power on reset is issued from the watchdog timer WDT initialization of the pin function controller PFC sets initial values that select the general input function for the I O ports However when ...

Page 763: ...en WTCNT Count Clock is Specified to Pφ 32 by CKS2 to CKS0 409 Added Internal reset signal power on reset selected Internal reset signal manual reset selected 18 Pφ clock 35 Pφ one cycle of count clock 12 3 2 Receive Data Register SCRDR 415 Amended Bit Initial value R W 7 6 5 4 3 2 1 0 R R R R R R R R 12 3 4 Transmit Data Register SCTDR 416 Amended Bit Initial value R W 7 6 5 4 3 2 1 0 R W R W R W...

Page 764: ...t for details refer to the SPB1IO bit description When output is enabled the SPB1DT bit value is output through the SCK pin 0 Low level is output 1 High level is output 1 SPB0IO 0 R Serial Port Break Output Controls the TxD pins together with the TE bit in SCSCR and the SPB0DT bit Reserved This bit is always read as 0 The write value should always be 0 0 SPB0DT Undefined 1 W SC SCR SP B0IO bit SP ...

Page 765: ...eleted In 2 channel scan mode since the channels are divided into group 0 and group 1 even though group 0 is operating in continuous scan mode the contents of the A D data registers for group 1 are retained Similarly even though group 1 is operating in continuous scan mode the contents of the A D data registers for group 0 are retained Note that a group 1 conversion request issued during group 0 A...

Page 766: ...ion is to be started by triggering regardless of the setting of the CH2 to CH0 bits in ADCSR_0 to ADCSR_1 A D conversion for group 0 is started by the trigger source set by the TRG0S3 to TRG0S0 and TRG1S3 to TRG1S0 bits in ADTSR and A D conversion for group 1 is started by the trigger source set by the TRG01S3 to TRG01S0 and TRG11S3 to TRG11S0 bits in ADTSR 13 4 7 2 Channel Scanning 493 Added In 2...

Page 767: ...igure 13 513 6 Figure 13 5 Definitions of A D Conversion Accuracy 496 Figure 13 413 5 Figure 13 6 Definitions of A D Conversion Accuracy 497 Figure 13 513 6 13 7 2 Permissible Signal Source Impedance 498 see figure 13 613 7 13 7 4 Range of Analog Power Supply and Other Pin Settings 499 AVss VAN AVccAVref 13 7 6 Notes on Noise Countermeasures 500 A protection circuit should be connected in order to...

Page 768: ...Parameters 597 Amended Since the program data is always in 128 byte units the lower eight bits MOA7 to MOA0 must be H 00 or H 80 as the boundary of the programming start address on the user MAT 17 5 2 User Program Mode Only in On Chip 128 Kbyte and 64 Kbyte ROM Version 611 Added After the programming erasing program has been downloaded and the SCO bit is cleared to 0 the setting of the frequency c...

Page 769: ...ower has been supplied initial values in RAM remain undefined until RAM is written Amended Bit Bit Name Description 4 3 This bit is always read as 1 The write value should always be 1 19 3 4 Standby Control Register 4 STBCR4 665 Amended Bit Bit Name Description 1 0 MSTP 25 24 00 UBC operates 01 Setting prohibited 10 Setting prohibited 11 Clock supply to UBC halted 19 3 5 Standby Control Register 5...

Page 770: ...Measure A Stop the generation of interrupts from on chip peripheral modules IRQ interrupts and the NMI interrupt before executing the SLEEP instruction Measure B Change the value in FRQCR to the initial value H 36DB and then dummy read FRQCR twice before executing the SLEEP instruction Amended Item MD1 FWE setup time 21 3 2 Control Signal Timing 712 Figure 21 5 Reset Input Timing 713 Amended MD1 F...

Page 771: ...Communication Interface SCI Timing 719 Amended Product Type Product Code Package Package Code R5F71253N50FP R5F71253D50FP LQFP 64 FP 64K R5F71253N50FA Flash memory version on chip 128 kbyte R5F71253D50FA QFP 64 FP 64H R5F71252N50FP R5F71252D50FP LQFP 64 FP 64K R5F71252N50FA SH7125 Flash memory version on chip 64 kbyte R5F71252D50FA QFP 64 FP 64H R5F71243N50FP Flash memory version on chip 128 kbyte...

Page 772: ...Rev 3 00 Sep 27 2007 Page 752 of 758 REJ09B0243 0300 ...

Page 773: ...eption handling vector table addresses 74 Changing frequency 65 Clock MPφ for the MTU2 module 55 Clock frequency control circuit 57 Clock operating mode 59 Clock pulse generator CPG 55 Clock synchronous mode 411 454 Clock timing 710 CMT interrupt sources 507 Compare match timer CMT 501 Complementary PWM mode 269 Connecting crystal resonator 66 Continuous scan mode 488 Control signal timing 712 CPU...

Page 774: ...79 IRQ interrupts 102 L List of registers 673 Logic operation instructions 41 M Manual reset 76 MCU operating modes 49 Module standby mode 672 Module standby mode setting 474 498 508 658 MTU2 functions 152 MTU2 interrupts 317 MTU2 output pin initialization 348 Multi function timer pulse unit 2 MTU2 151 Multiply and accumulate registers MACH and MACL 21 Multiprocessor communication function 463 N N...

Page 775: ...nge of analog power supply and other pin settings 499 Register ADCR 482 ADCSR 479 ADDR0 to ADDR7 479 ADTSR 484 BAMRA 116 BAMRB 122 BARA 116 BARB 121 BBRA 117 BBRB 125 BDMRA 120 BDMRB 124 BDRA 119 BDRB 123 BETR 131 BRCR 127 BRDR 133 BRSR 132 CMCNT 505 CMCOR 505 CMCSR 503 CMSTR 503 DPFR 591 FCCS 584 FEBS 601 FECS 587 FKEY 588 FMPAR 597 FMPDR 598 FPCS 587 FPEFEQ 593 FPFR 596 599 602 FRQCR 61 FTDAR 58...

Page 776: ... 666 STBCR6 667 TADCOBRA_4 208 TADCOBRB_4 208 TADCORA_4 208 TADCORB_4 208 TADCR 205 TBTER 232 TBTM 202 TCBR 229 TCDR 228 TCNT 209 TCNTCMPCLR 188 TCNTS 227 TCR 162 TCSYSTR 214 TDDR 228 TDER 234 TGCR 225 TGR 209 TICCR 203 TIER 189 TIOR 169 TITCNT 231 TITCR 229 TMDR 166 TOCR1 218 TOCR2 221 TOER 217 TOLBR 224 TRWER 216 TSR 194 TSTR 210 TSYR 212 TWCR 235 WTCNT 404 WTCSR 405 Register address table in th...

Page 777: ... after interrupt exception handling 110 Stack states after exception handling ends 84 Status register SR 19 System control instructions 44 T Target pins and conditions for high impedance control 396 The address map for the operating modes 51 Trap instructions 81 U User break controller UBC 113 User break interrupt 103 User MAT 578 User program mode 609 Using interval timer mode 409 Using watchdog ...

Page 778: ...Rev 3 00 Sep 27 2007 Page 758 of 758 REJ09B0243 0300 ...

Page 779: ...ication Date Rev 1 00 Mar 25 2005 Rev 3 00 Sep 27 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2007 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 780: ...8 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65...

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