Renesas SH7124 R5F7124, Hardware Manual

Page: 139 / 782

Section 7 User Break Controller (UBC)
Rev. 3.00 Sep. 27, 2007 Page 119 of 758
REJ09B0243-0300
7.2.4 Break Data Register A (BDRA)
BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select
one of two data buses for break condition A.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0
Bit Bit Name
Initial
Value
R/W Description
31 to 0 BDA31 to
BDA0
All 0 R/W Break Data Bit A
Stores data, which specifies a break condition in
channel A.
If the I bus is selected in BBRA, the break data on IDB is
set in BDA31 to BDA0.
If the L bus is selected in BBRA, the break data on LDB
is set in BDA31 to BDA0.
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRA as the break data.