Renesas SH7124 R5F7124, Hardware Manual

Page: 407 / 782

Section 10 Port Output Enable (POE)
Rev. 3.00 Sep. 27, 2007 Page 387 of 758
REJ09B0243-0300
Bit Bit Name
Initial
value R/W Description
8 PIE1 0 R/W Port Interrupt Enable 1
This bit enables/disables interrupt requests when any one
of the POE0F to POE3F bits of the ICSR1 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7, 6 POE3M[1:0] 00 R/W *
2
POE3 mode 1, 0
(Supported only by the SH7125. Write 00 to these bits in
the SH7124.)
These bits select the input mode of the
POE3
pin.
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
for 16 P
φ
/8 clock pulses and all are low level.
10: Accept request when POE3 input has been sampled
for 16 P
φ
/16 clock pulses and all are low level.
11: Accept request when POE3 input has been sampled
for 16 P
φ
/128 clock pulses and all are low level.
5, 4

All 0 R/W
*
2
Reserved
These bits are always read as 0. The write value should
always be 0.
3, 2 POE1M[1:0] 00 R/W *
2
POE1 mode 1, 0
These bits select the input mode of the
POE1
pin.
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 P
φ
/8 clock pulses and all are low level.
10: Accept request when POE1 input has been sampled
for 16 P
φ
/16 clock pulses and all are low level.
11: Accept request when POE1 input has been sampled
for 16 P
φ
/128 clock pulses and all are low level.