Renesas SH7124 R5F7124, Hardware Manual

Page: 136 / 782

Section 7 User Break Controller (UBC)
Rev. 3.00 Sep. 27, 2007 Page 116 of 758
REJ09B0243-0300
7.2.1 Break Address Register A (BARA)
BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition
in channel A.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16
BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0
Bit Bit Name
Initial
Value
R/W Description
31 to 0 BAA31 to
BAA 0
All 0 R/W Break Address A
Store the address on the LAB or IAB specifying break
conditions of channel A.
7.2.2 Break Address Mask Register A (BAMRA)
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address
specified by BARA.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16
BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0