Rev. 3.00 Sep. 27, 2007 Page 753 of 758
REJ09B0243-0300
Index
A
A/D conversion time............................... 491
A/D converter (ADC) ............................. 475
A/D converter activation......................... 319
A/D converter characteristics.................. 724
A/D converter interrupt source ............... 494
A/D converter start request
delaying function .................................... 308
Absolute accuracy................................... 495
Absolute maximum ratings..................... 705
AC characteristics................................... 709
AC characteristics measurement
conditions................................................ 723
Address error .............................. 77, 86, 658
Addressing modes..................................... 26
Arithmetic operation instructions ............. 39
Asynchronous mode ....................... 411, 444
B
Boot mode............................................... 605
Branch instructions ................................... 43
Break comparison conditions.................. 113
Break detection and processing .............. 472
Break on data access cycle...................... 135
Break on instruction fetch cycle ............. 135
Bus state controller (BSC) ...................... 147
C
Calculating exception handling vector
table addresses .......................................... 74
Changing frequency.................................. 65
Clock (MP
φ
) for the MTU2 module ......... 55
Clock frequency control circuit ................ 57
Clock operating mode............................... 59
Clock pulse generator (CPG).................... 55
Clock synchronous mode ................ 411, 454
Clock timing ........................................... 710
CMT interrupt sources ............................ 507
Compare match timer (CMT) ................. 501
Complementary PWM mode .................. 269
Connecting crystal resonator..................... 66
Continuous scan mode ............................ 488
Control signal timing .............................. 712
CPU........................................................... 17
Crystal oscillator ....................................... 57
D
Data transfer instructions .......................... 37
DC Characteristics .................................. 706
Dead time compensation......................... 313
Divider ...................................................... 57
E
Error protection....................................... 619
Exception handling ................................... 71
Exception handling state ........................... 47
External clock input method ..................... 67
External pulse width measurement ......... 312
External trigger input timing................... 492
F
Features of instructions ............................. 23
Flash Memory ......................................... 573
Flash memory characteristics.................. 725
Flash memory configuration ................... 578
Flow of the user break operation............. 134
Full-scale error ........................................ 495
Function for detecting oscillator stop........ 68
Summary of Contents for SH7124 R5F7124
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Page 36: ...Section 1 Overview Rev 3 00 Sep 27 2007 Page 16 of 758 REJ09B0243 0300 ...
Page 68: ...Section 2 CPU Rev 3 00 Sep 27 2007 Page 48 of 758 REJ09B0243 0300 ...
Page 108: ...Section 5 Exception Handling Rev 3 00 Sep 27 2007 Page 88 of 758 REJ09B0243 0300 ...
Page 166: ...Section 7 User Break Controller UBC Rev 3 00 Sep 27 2007 Page 146 of 758 REJ09B0243 0300 ...
Page 724: ...Section 20 List of Registers Rev 3 00 Sep 27 2007 Page 704 of 758 REJ09B0243 0300 ...
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