Renesas SH7124 R5F7124, Hardware Manual

Page: 551 / 782

Section 15 Pin Function Controller (PFC)
Rev. 3.00 Sep. 27, 2007 Page 531 of 758
REJ09B0243-0300
15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH)
PBIORL and PBIORH are 16-bit readable/writable registers that are used to set the pins on port B
as inputs or outputs. Bits PB16IOR, PB5IOR, and PB3IOR to PB1IOR correspond to pins PB16,
PB5, and PB3 to PB1, respectively (names of multiplexed pins are here given as port names and
pin numbers alone). PBIORL is enabled when the port B pins are functioning as general-purpose
inputs/outputs (PB5 and PB3 to PB1), and the SCK pin is functioning as inputs/outputs of SCI. In
other states, PBIORL is disabled. PBIORH is enabled when the port B pins are functioning as
general-purpose inputs/outputs (PB16). In other states, PBIORH is disabled.
A given pin on port B will be an output pin if the corresponding bit in PBIORH or PBIORL is set
to 1, and an input pin if the bit is cleared to 0.
However, bit 2 of PBIORL and bit 0 of PBIORH are disabled in SH7124.
Bits 15 to 6, 4, and 0 of PBIORL and bits 15 to 1 of PBIORH are reserved. These bits are always
read as 0. The write value should always be 0.
The initial value of PBIORL and PBIORH are H'0000, respectively.
•
Port B I/O Register H (PBIORH)
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R/W
- - - - - - - - - - - - - - -
PB16
IOR
•
Port B I/O Register L (PBIORL)
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R/W R R/W R/W R/W R
- - - - - - - - - -
PB5
IOR
-
PB3
IOR
PB2
IOR
PB1
IOR
-