Section 13 A/D Converter (ADC)
Rev. 3.00 Sep. 27, 2007 Page 478 of 758
REJ09B0243-0300
13.3 Register
Descriptions
The A/D converter has the following registers. For details on register addresses and register states
in each processing state, refer to section 20, List of Registers.
Table 13.2 Register Configuration
Register Name
Abbrevia-
tion
R/W
Initial Value Address
Access Size
A/D data register 0
ADDR0
R
H'0000
H'FFFFC900
16
A/D data register 1
ADDR1
R
H'0000
H'FFFFC902
16
A/D data register 2
ADDR2
R
H'0000
H'FFFFC904
16
A/D data register 3
ADDR3
R
H'0000
H'FFFFC906
16
A/D control/status register_0
ADCSR_0
R/W
H'0000
H'FFFFC910
16
A/D control register_0
ADCR_0
R/W
H'0000
H'FFFFC912
16
A/D data register 4
ADDR4
R
H'0000
H'FFFFC980
16
A/D data register 5
ADDR5
R
H'0000
H'FFFFC982
16
A/D data register 6
ADDR6
R
H'0000
H'FFFFC984
16
A/D data register 7
ADDR7
R
H'0000
H'FFFFC986
16
A/D control/status register_1
ADCSR_1
R/W
H'0000
H'FFFFC990
16
A/D control register_1
ADCR_1
R/W
H'0000
H'FFFFC992
16
A/D trigger select register_0
ADTSR_0
R/W
H'0000
H'FFFFE890
8, 16
Summary of Contents for SH7124 R5F7124
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Page 8: ...Rev 3 00 Sep 27 2007 Page viii of xx ...
Page 36: ...Section 1 Overview Rev 3 00 Sep 27 2007 Page 16 of 758 REJ09B0243 0300 ...
Page 68: ...Section 2 CPU Rev 3 00 Sep 27 2007 Page 48 of 758 REJ09B0243 0300 ...
Page 108: ...Section 5 Exception Handling Rev 3 00 Sep 27 2007 Page 88 of 758 REJ09B0243 0300 ...
Page 166: ...Section 7 User Break Controller UBC Rev 3 00 Sep 27 2007 Page 146 of 758 REJ09B0243 0300 ...
Page 724: ...Section 20 List of Registers Rev 3 00 Sep 27 2007 Page 704 of 758 REJ09B0243 0300 ...
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