Section 15 Pin Function Controller (PFC)
Rev. 3.00 Sep. 27, 2007 Page 540 of 758
REJ09B0243-0300
Bit Bit
Name
Initial
Value
R/W Description
2
1
0
PE8MD2
PE8MD1
PE8MD0
0
0
0
R/W
R/W
R/W
PE8 Mode
Select the function of the PE8/TIOC3A pin.
000: PE8 I/O (port)
001: TIOC3A I/O (MTU2)
Other than above: Setting prohibited
•
Port E Control Register L2 (PECRL2)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
-
PE7
MD2
PE7
MD1
PE7
MD0
-
PE6
MD2
PE6
MD1
PE6
MD0
-
PE5
MD2
PE5
MD1
PE5
MD0
-
PE4
MD2
PE4
MD1
PE4
MD0
Bit Bit
Name
Initial
Value
R/W Description
15
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
13
12
PE7MD2
PE7MD1
PE7MD0
0
0
0
R/W
R/W
R/W
PE7 Mode
Select the function of the PE7/TIOC2B pin.
000: PE7 I/O (port)
001: TIOC2B I/O (MTU2)
Other than above: Setting prohibited
11
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
9
8
PE6MD2
PE6MD1
PE6MD0
0
0
0
R/W
R/W
R/W
PE6 Mode
Select the function of the PE6/TIOC2A/SCK1 pin.
000: PE6 I/O (port)
001: TIOC2A I/O (MTU2)
110: SCK1 I/O (SCI)
Other than above: Setting prohibited
Summary of Contents for SH7124 R5F7124
Page 2: ...Rev 3 00 Sep 27 2007 Page ii of xx ...
Page 8: ...Rev 3 00 Sep 27 2007 Page viii of xx ...
Page 36: ...Section 1 Overview Rev 3 00 Sep 27 2007 Page 16 of 758 REJ09B0243 0300 ...
Page 68: ...Section 2 CPU Rev 3 00 Sep 27 2007 Page 48 of 758 REJ09B0243 0300 ...
Page 108: ...Section 5 Exception Handling Rev 3 00 Sep 27 2007 Page 88 of 758 REJ09B0243 0300 ...
Page 166: ...Section 7 User Break Controller UBC Rev 3 00 Sep 27 2007 Page 146 of 758 REJ09B0243 0300 ...
Page 724: ...Section 20 List of Registers Rev 3 00 Sep 27 2007 Page 704 of 758 REJ09B0243 0300 ...
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