Renesas SH7124 R5F7124, Hardware Manual

Page: 732 / 782

Section 21 Electrical Characteristics
Rev. 3.00 Sep. 27, 2007 Page 712 of 758
REJ09B0243-0300
21.3.2 Control Signal Timing
Table 21.6 Control Signal Timing
Conditions: V
CC
= AV
CC
= 4.0 V to 5.5 V, V
SS
= PLLV
SS
= AV
SS
= 0 V,
T
a
= –20 to +85
°
C (consumer specifications),
T
a
= –40 to +85
°
C (industrial specifications)
Item Symbol Min. Max. Unit Reference Figure
RES
pulse width t
RESW
20 *
2
— t
Bcyc
*
4
RES
setup time *
1
(reference values) t
RESS
65 — ns
RES
hold time (reference values) t
RESH
15 — ns
MRES
pulse width t
MRESW
20 *
3
— t
Bcyc
*
4
MRES
setup time *
1
(reference values) t
MRESS
25 — ns
MRES
hold time (reference values) t
MRESH
15 — ns
Figures 21.2, 21.3,
21.5, 21.6
MD1, FWE setup time t
MDS
20 — t
Bcyc
*
4
Figure 21.5
NMI setup time
*
1
(reference values) t
NMIS
60 — ns Figure 21.6
NMI hold time (reference values) t
NMIH
10 — ns
IRQ3 to IRQ0 setup time *
1
(reference values)
t
IRQS
35 — ns
IRQ3 to IRQ0 hold time
(reference values) t
IRQH
35 — ns
IRQOUT
output delay time
(reference values)
t
IRQOD
— 100 ns Figure 21.7
Notes: 1. The
RES
,
MRES
, NMI, and IRQ3 to IRQ0 signals are asynchronous signals. When the
setup time is satisfied, change of signal level is detected at the rising edge of the clock.
If not, the detection is delayed until the rising edge of the clock.
2. In standby mode, t
RESW
= t
OSC2
(10 ms).
3. In standby mode, t
MRESW
= t
OSC2
(10 ms).
4. t
Bcyc
indicates the bus clock cycle time (B
φ
= CK).