Renesas SH7124 R5F7124, Hardware Manual

Page: 408 / 782

Section 10 Port Output Enable (POE)
Rev. 3.00 Sep. 27, 2007 Page 388 of 758
REJ09B0243-0300
Bit Bit Name
Initial
value R/W Description
1, 0 POE0M[1:0] 00 R/W *
2
POE0 mode 1, 0
These bits select the input mode of the
POE0
pin.
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
for 16 P
φ
/8 clock pulses and all are low level.
10: Accept request when POE0 input has been sampled
for 16 P
φ
/16 clock pulses and all are low level.
11: Accept request when POE0 input has been sampled
for 16 P
φ
/128 clock pulses and all are low level.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
10.3.2 Output Level Control/Status Register 1 (OCSR1)
OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R/W R R R R R R R R
Bit:
Initial value:
R/W:R/(W)
*
1
R/W *
2
OSF1 - - - - - OCE1 OIE1 - - - - - - - -
Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Can be modified only once after a power-on reset.
1.
2.
Bit Bit Name
Initial
value
R/W Description
15 OSF1 0 R/(W)
*
1
Output Short Flag 1
This flag indicates that any one of the three pairs of
MTU2 2-phase outputs to be compared has
simultaneously become an active level.
[Clearing condition]
•
By writing 0 to OSF1 after reading OSF1 = 1
[Setting condition]
•
When any one of the three pairs of 2-phase outputs
has simultaneously become an active level