Renesas SH7124 R5F7124, Hardware Manual

Page: 760 / 782

Rev. 3.00 Sep. 27, 2007 Page 740 of 758
REJ09B0243-0300
Item Page Revision (See Manual for Details)
8.4 Access to on-chip Peripheral
I/O Register 148 Added
The L bus access takes one Iclk cycle, I bus access
takes one Bclk cycle, and peripheral bus access takes
two Pclk cycles. When the on-chip peripheral I/O
register is accessed by the CPU, the period required for
preparation for data transfer to the I bus is a period of 3
Iclk cycles.
8.4 Access to on-chip Peripheral
I/O Register 148 Amended
In the case shown in figure 8.1, where Bclk = Pclk =
1:1, the timeperiod required for access by the CPU is
(13 + n)
×
Iclk + 1
×
Bclk + 2
×
Pclk.
8.4 Access to on-chip Peripheral
I/O Register 149 Amended
When Iclk:Bclk = 1:1, a period of 3 Iclk + Bclk is
required.
8.4 Access to on-chip Peripheral
I/O Register 149 Amended
In the case shown in figure 8.2, where Bclk = Pclk =
1:1, the timeperiod required for access by the CPU is
(13 + n)
×
Iclk + 1
×
Bclk + 2
×
Pclk.
Figure 8.2 Timing of Write Access
to the Peripheral Bus
(Iclk:Bclk:Pclk = 4:4:1) 149 Amended
L bus
Bclk
I bus
8.4 Access to on-chip Peripheral
I/O Register 149,
150 Added
Figure 8.3 shows an example of timing of read access
to the peripheral bus when Iclk:Bclk:Pclk = 4:2:1.
Transfer from the L bus to the peripheral bus is
performed in the same way as for write access. In the
case of reading, however, values output onto the
peripheral bus must be transferred to the CPU.
Transfers from the external bus to the I bus and from
the I bus to the L bus are again performed in
synchronization with rising edges of the respective bus
clocks. 2
×
Iclk cycles of period is required because Iclk
≥
Bclk
≥
Pclk. In the case shown in figure 8.3, where n
= 0 and m = 1, the period required for access by the
CPU is 3
×
Iclk + 2
×
Bclk + 2
×
Pclk + 2
×
Iclk.