CHAPTER 16 ELECTRICAL SPECIFICATIONS
652
User’s Manual U15195EJ5V0UD
(7) Timer input timing
(T
A
= –40 to +85
°
C, REGIN = 3.0 to 3.6 V, V
DD
= RV
DD
= 5.0 V
±
0.5 V, V
SS3
= V
SS
= CV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
TIUD10, TCUD10 high-/low-level
width
t
WUDH
,
t
WUDL
<53>
5T + 10
ns
TIUD10, TCUD10 input time
difference
t
PHUD
<54>
5T + 10
ns
n = 10, 2 (other than for through input), 3
5T + 10
ns
TCLRn high-/low-level width
t
WTCH
,
t
WTCL
<55>
n = 2 (for through input
Note
)
2T + 10
ns
m = 2 (other than for through input), 3
5T + 10
ns
TIm high-/low-level width
t
WTIH
,
t
WTIL
<56>
m = 2 (for through input
Note
)
2T + 10
ns
Note
When setting the CESE1 and CESE0 bits of timer 2 count clock/control edge selection register 0 (CSE0) to 1
and 0, respectively.
Remarks
1.
T: Digital filter sampling clock
T
can be selected by setting the following registers.
•
TIUD10, TCUD10, TCLR10:
Can be selected from f
XX
/2, f
XX
/4, f
XX
/8, and f
XX
/16 by setting the NRC101 and NRC100 bits of the
timer 10 noise elimination time select register (NRC10).
•
TCLR2, TI2:
Fixed to f
XX
/2.
•
TCLR3, TI3:
Can be selected from f
XXTM3
/2, f
XXTM3
/4, f
XXTM3
/8, and f
XXTM3
/16 by setting the NRC31 and NRC30
bits of the timer 3 noise elimination time selection register (NRC3) (f
XXTM3
: Clock selected with the
timer 3 clock selection register (PRM03)).
2.
f
X
: Internal system clock frequency
<53>
TIUD10 (input)
TCUD10 (input)
TCLRn (input)
TIm (input)
<53>
<53>
<53>
<54>
<54>
<54>
<54>
<55>
<55>
<56>
<56>
Remark
n = 10, 2, 3
m = 2, 3
