CHAPTER 9 TIMER/COUNTER FUNCTION
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User’s Manual U15195EJ5V0UD
(1) Timer 4 (TM4)
TM4 is a 16-bit timer. It is mainly used as an interval timer for software.
Starting and stopping TM4 is controlled by the TM4CE0 bit of timer control register 4 (TMC4).
Division by the prescaler can be selected for the count clock from among f
XX
/4, f
XX
/8, f
XX
/16, f
XX
/32, f
XX
/64,
f
XX
/128, f
XX
/256, and f
XX
/512 by the CS2 to CS0 bits of the TMC4 register (f
XX
: Internal system clock).
TM4 is read-only, in 16-bit units.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TM4
FFFFF540H
0000H
Address
After reset
0
The conditions under which the TM4 register becomes 0000H are shown below.
•
Reset input
•
TM4CAE0 bit = 0
•
TM4CE0 bit = 0
•
Match of TM4 register and CM4 register
•
Overflow
Cautions 1. If the TM4CAE0 bit of the TMC4 register is cleared (0), a reset is performed
asynchronously.
2. If the TM4CE0 bit of the TMC4 register is cleared (0), a reset is performed, synchronized
with the internal clock. Similarly, a synchronized reset is performed after a match with
the CM4 register and after an overflow.
3. The count clock must not be changed during a timer operation. If it is to be overwritten,
it should be overwritten after the TM4CE0 bit is cleared (0).
4. Up to 4 internal system clocks are required after a value is set in the TM4CE0 bit until
the set value is transferred to internal units. When a count operation begins, the count
cycle from 0000H to 0001H differs from subsequent count cycles.
5. After a compare match is generated, the timer is cleared at the next count clock.
Therefore, if the division ratio is large, the timer value may not be zero even if the timer
value is read immediately after a match interrupt is generated.
