CHAPTER 16 ELECTRICAL SPECIFICATIONS
655
User’s Manual U15195EJ5V0UD
(11) UART1 timing (1/2)
(a) Clocked master mode
(T
A
= –40 to +85
°
C, REGIN = 3.0 to 3.6 V, V
DD
= RV
DD
= 5.0 V
±
0.5 V, V
SS3
= V
SS
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
ASCK1 cycle
t
CYSK0
<64> Output
1000
ns
ASCK1 high-level width
t
WSK0H
<65> Output
kT
–
20
ns
ASCK1 low-level width
t
WSK0L
<66> Output
kT
–
20
ns
RXD1 setup time (to ASCK1
↑
) t
SRXSK
<67>
1.5T + 35
ns
RXD1 hold time (from ASCK1
↑
) t
HSKRX
<68>
0
ns
TXD1 output delay time (from ASCK1
↓
) t
DSKTX
<69>
T + 10
ns
TXD1 output hold time (from ASCK1
↑
) t
HSKTX
<70>
(k + 1)T – 20
ns
Remarks 1.
T = 2t
CYK
2.
k: Setting value of prescaler compare register 1 (PRSCM1) of UART1
(b) Clocked slave mode
(T
A
= –40 to +85
°
C, REGIN = 3.0 to 3.6 V, V
DD
= RV
DD
= 5.0 V
±
0.5 V, V
SS3
= V
SS
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
ASCK1 cycle
t
CYSK0
<64> Input
1000
ns
ASCK1 high-level width
t
WSK0H
<65>
Input
4T + 80
ns
ASCK1 low-level width
t
WSK0L
<66>
Input
4T + 80
ns
RXD1 setup time (to ASCK1
↑
) t
SRXSK
<67>
T + 10
ns
RXD1 hold time (from ASCK1
↑
) t
HSKRX
<68>
T + 10
ns
TXD1 output delay time (from ASCK1
↓
) t
DSKTX
<69>
2.5T + 45
ns
TXD1 output hold time (from ASCK1
↑
) t
HSKTX
<70>
(k + 1.5)T
ns
Remarks 1.
T = 2t
CYK
2.
k: Setting value of prescaler compare register 1 (PRSCM1) of UART1
