NEC PD703114 User Manual Download Page 244

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CHAPTER 9 TIMER/COUNTER FUNCTION

244

User’s Manual U15195EJ5V0UD

[Operation]

In PWM mode 1, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an

underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt

(INTCM0n3) is generated (n = 0, 1).

Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and

switching from down counting to up counting is performed by INTTM0n.

The PWM cycle in this mode is (BFCMn3 value

TM0n count clock). Note that the next PWM cycle width

is set to BFCMn3.

The data of BFCMn3 is automatically transferred by hardware to CM0n3 upon generation of the INTTM0n

interrupt. Furthermore, calculation is performed by software processing started by INTTM0n, and the data for

the next cycle is set to BFCMn3.

Data setting to CM0n0 to CM0n2, which control the PWM duty, is explained next.

Setting of data to CM0n0 to CM0n2 consists of setting the duty output from BFCMn0 to BFCMn2.

The values of BFCMn0 to BFCMn2 are automatically transferred by hardware to CM0n0 to CM0n2 upon

generation of INTTM0n and INTCM0n3 (TM0n and CM0n3 match interrupts). Furthermore, software

processing is started up and calculation performed, and the set/reset timing of the F/F after a half cycle is set

in BFCMn0 to BFCMn2.

The PWM cycle and the PWM duty are set in the above procedure.

The F/F set/reset conditions upon match of CM0n0 to CM0n2 are as follows.

•

Set:

CM0n0 to CM0n2 match detection during TM0n up count operation

•

Reset: CM0n0 to CM0n2 match detection during TM0n down count operation

The values of DTRRn are transferred to the corresponding dead-time timers (DTMn0 to DTMn2) in

synchronization with the set/reset timing of the F/F, and down counting is started. DTMn0 to DTMn2 count

down to 000H, and stop when they count down further to FFFH.

DTMn0 to DTMn2 can automatically generate a width at which the active levels of the positive phase (TO0n0,

TO0n2, TO0n4) and negative phase (TO0n1, TO0n3, TO0n5) do not overlap (dead time).

In this way, software processing is started by two interrupts (INTTM0n and INTCM0n3) that occur during

every PWM cycle after initial setting has been performed, and by setting the PWM cycle and PWM duty to be

used after a half cycle, it is possible to automatically output a PWM waveform to pins TO0n0 to TO0n5 taking

into consideration the dead-time width (in the case of an interrupt culling ratio of 1/1).

The difference between right-left symmetric waveform control and control in this mode (right-left asymmetric

waveform control) is that BFCMn0 to BFCMn2 are transferred to CM0n0 to CM0n2, and that the interrupt

signals that start software processing consist just of INTTM0n (generated once per PWM cycle) in the case of

right-left symmetric waveform control, and INTTM0n and INTCM0n3 (generated twice per PWM cycle, or

once per half cycle) in the case of right-left asymmetric waveform control.

Summary of Contents for PD703114

Page 1: ...ted in Japan Document No U15195EJ5V0UD00 5th edition Date Published August 2005 N CP K V850E IA2 32 Bit Single Chip Microcontrollers Hardware User s Manual µPD703114 µPD703114 A µPD70F3114 µPD70F3114 A 2001 ...

Page 2: ...2 User s Manual U15195EJ5V0UD MEMO ...

Page 3: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 4: ...ety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Elec...

Page 5: ...anch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J05 6 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 00 Succur...

Page 6: ...Pipeline operation How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering logic circuits and microcontrollers Cautions 1 The application examples in this manual apply to standard quality grade products for general electronic systems When using an example in this manual for an application that requires a special quality g...

Page 7: ...vised points Conventions Data significance Higher digits on the left and lower digits on the right Active low representation xxx overscore over pin or signal name Memory map address Top higher bottom lower Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx or xxxxB Decimal xxxx H...

Page 8: ...ocument Name Document No IE V850E MC IE V850E MC A In circuit emulator U14487E IE 703114 MC EM1 In circuit emulator option board U16533E Operation U17293E C Language U17291E Assembly Language U17292E CA850 Ver 3 00 C compiler package Link Directives U17294E PM Ver 6 00 Project manager U17178E ID850 Ver 3 00 Integrated debugger Operation U17358E TW850 Ver 2 00 Performance analysis tuning tool U1724...

Page 9: ...46 3 2 CPU Register Set 47 3 2 1 Program register set 48 3 2 2 System register set 49 3 3 Operation Modes 55 3 3 1 Operation modes 55 3 3 2 Operation mode specification 56 3 4 Address Space 57 3 4 1 CPU address space 57 3 4 2 Image 58 3 4 3 Wrap around of CPU address space 59 3 4 4 Memory map 60 3 4 5 Area 61 3 4 6 External memory expansion 65 3 4 7 Recommended use of address space 66 3 4 8 On chi...

Page 10: ...106 6 3 Control Registers 107 6 3 1 DMA source address registers 0 to 3 DSA0 to DSA3 107 6 3 2 DMA destination address registers 0 to 3 DDA0 to DDA3 109 6 3 3 DMA transfer count registers 0 to 3 DBC0 to DBC3 111 6 3 4 DMA addressing control registers 0 to 3 DADC0 to DADC3 112 6 3 5 DMA channel control registers 0 to 3 DCHC0 to DCHC3 114 6 3 6 DMA disable status register DDIS 116 6 3 7 DMA restart ...

Page 11: ...iority register ISPR 154 7 3 7 Maskable interrupt status flag ID 155 7 3 8 Interrupt trigger mode selection 155 7 4 Software Exception 163 7 4 1 Operation 163 7 4 2 Restore 164 7 4 3 Exception status flag EP 165 7 5 Exception Trap 166 7 5 1 Illegal opcode definition 166 7 5 2 Debug trap 168 7 6 Multiple Interrupt Servicing Control 170 7 7 Interrupt Response Time 172 7 8 Periods in Which CPU Does N...

Page 12: ...eration 310 9 2 6 Supplementary description of internal operation 319 9 3 Timer 2 322 9 3 1 Features timer 2 322 9 3 2 Function overview timer 2 322 9 3 3 Basic configuration 324 9 3 4 Control registers 330 9 3 5 Operation 347 9 3 6 PWM output operation in timer 2 compare mode 365 9 4 Timer 3 368 9 4 1 Features timer 3 368 9 4 2 Function overview timer 3 368 9 4 3 Function added to V850E IA2 369 9...

Page 13: ... 10 4 1 Features 474 10 4 2 Configuration 475 10 4 3 Control registers 478 10 4 4 Operation 492 10 4 5 Output pins 507 10 4 6 Dedicated baud rate generator 3 BRG3 508 CHAPTER 11 A D CONVERTER 512 11 1 Features 512 11 2 Configuration 512 11 3 Functions Added to V850E IA2 516 11 4 Control Registers 517 11 5 Interrupt Requests 528 11 6 A D Converter Operation 529 11 6 1 A D converter basic operation ...

Page 14: ...3 Pin Functions of Each Port 563 12 3 1 Port 0 563 12 3 2 Port 1 564 12 3 3 Port 2 566 12 3 4 Port 3 568 12 3 5 Port 4 570 12 3 6 Port DH 572 12 3 7 Port DL 574 12 3 8 Port CT 576 12 3 9 Port CM 578 12 4 Operation of Port Function 580 12 4 1 Writing to I O port 580 12 4 2 Reading from I O port 580 12 4 3 Output status of alternate function in control mode 580 12 5 Noise Eliminator 581 12 5 1 Inter...

Page 15: ...ogramming 614 15 7 2 Self programming function 615 15 7 3 Outline of self programming interface 615 15 7 4 Hardware environment 616 15 7 5 Software environment 618 15 7 6 Self programming function number 619 15 7 7 Calling parameters 620 15 7 8 Contents of RAM parameters 621 15 7 9 Errors during self programming 622 15 7 10 Flash information 622 15 7 11 Area number 623 15 7 12 Flash programming mo...

Page 16: ...IX A NOTES ON TARGET SYSTEM DESIGN 664 APPENDIX B REGISTER INDEX 666 APPENDIX C INSTRUCTION SET LIST 675 C 1 Conventions 675 C 2 Instruction Set Alphabetical Order 678 APPENDIX D REVISION HISTORY 684 D 1 Major Revisions in This Edition 684 D 2 Revision History up to Previous Edition 686 ...

Page 17: ...ssing by the on chip interrupt controller is also fast this CPU is ideal for advanced real time control 2 External bus interface function A bus configuration consisting of a multiplexed address bus 22 bits and data bus 8 bits or 16 bits selectable suitable for compact system design is used as the external bus interface SRAM and ROM memories can be connected In the DMA controller transfer is starte...

Page 18: ... Provided UART0 Provided Provided UART1 Provided Provided pins multiplexed with CSI1 UART2 Provided Not provided CSI0 Provided Provided CSI1 Provided Provided pins multiplexed with UART1 Serial interface FCAN Provided Not provided Debug support function NBD Provided Not provided Analog input Total of two circuits 16 ch A D converter 0 8 ch A D converter 1 8 ch Total of two circuits 14 ch A D conve...

Page 19: ...4 bits 1 or 2 clocks Saturated operation instructions with overflow underflow detection function 32 bit shift instruction 1 clock Bit manipulation instructions Long short format load store instructions Signed load instructions Memory space 4 MB linear address space shared by program and data Memory block division function 2 MB block Programmable wait function Idle state insertion function External...

Page 20: ...onous serial interface UART 2 channels Clocked serial interface CSI 2 channels Of the four channels two channels are used for both CSI and UART and therefore one or the other function must be selected A D converter 10 bit resolution A D converter 6 channels 8 channels 2 units Regulator Two power supplies one for the internal CPU and one for the peripheral interface are not necessary A 5 V single p...

Page 21: ...03114GF 3BA 100 pin plastic QFP 14 20 Standard µPD703114GF 3BA A 100 pin plastic QFP 14 20 Standard µPD70F3114GC 8EU 100 pin plastic LQFP fine pitch 14 14 Standard µPD70F3114GC 8EU A 100 pin plastic LQFP fine pitch 14 14 Standard µPD70F3114GC A 8EU 100 pin plastic LQFP fine pitch 14 14 Special µPD70F3114GC A 8EU A 100 pin plastic LQFP fine pitch 14 14 Special µPD70F3114GF 3BA 100 pin plastic QFP 1...

Page 22: ... ANI04 ANI03 ANI02 ANI01 ANI00 AV SS0 AV DD0 TO015 TO014 TO013 TO012 TO011 TO010 V SS V DD TO005 TO004 TO003 TO002 TO001 TO000 INTP4 TO3OFF P05 ADTRG1 INTP3 P04 ADTRG0 INTP2 P03 ESO1 INTP1 P02 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ANI05 AVDD1 AVSS1 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ANI...

Page 23: ... CLKOUT PCM0 WAIT PCT6 ASTB PCT4 RD PCT1 UWR PCT0 LWR VDD VSS3 MODE1 VPP Note 1 PDH5 A21 PDH4 A20 PDH3 A19 PDH2 A18 PDH1 A17 PDH0 A16 PDL15 AD15 PDL14 AD14 PDL13 AD13 PDL12 AD12 PDL11 AD11 PDL10 AD10 PDL9 AD9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ANI03 ANI04 ANI05 AV...

Page 24: ...output Clock generator ground Emergency shut off External interrupt input Lower write strobe Mode Non maskable interrupt request Port 0 Port 1 Port 2 Port 3 Port 4 Port CM Port CT PDH0 to PDH5 PDL0 to PLD15 RD RESET REGIN REGOUT RVDD RXD0 RXD1 SCK0 SCK1 SI0 SI1 SO0 SO1 TCLR10 TCLR2 TCLR3 TCUD10 TI2 TI3 TIUD10 TO000 to TO005 TO010 to TO015 TO10 TO21 to TO24 TO3 TO3OFF TXD0 TXD1 UWR VDD VPP VSS VSS3...

Page 25: ...ifter Multiplier 32 32 64 CPU ROM RAM BCU ALU CKSEL CLKOUT X1 X2 CVSS MODE0 MODE1 VPPNote 2 RESET VDD VSS VSS3 PDL0 to PDL15 PDH0 to PDH5 PCT0 PCT1 PCT4 PCT6 PCM0 PCM1 P40 to P42 P30 to P34 P20 to P27 P10 to P12 P00 to P05 ADTRG0 ANI00 to ANI05 AV SS0 AV DD0 ADTRG1 ANI10 to ANI17 AV SS1 AV DD1 System registers General purpose registers 32 bits 32 Ports ADC0 ADC1 CG REGIN REGOUT RVDD VSS3 Regulator...

Page 26: ...transfer The three bus modes are single transfer single step transfer and block transfer 5 ROM The µPD703114 includes mask ROM 128 KB and the µPD70F3114 includes flash memory 128 KB On an instruction fetch the ROM can be accessed by the CPU in one clock When single chip mode or flash memory programming mode is set ROM is mapped starting from address 00000000H ROM cannot be accessed if ROMless mode...

Page 27: ...g pins TXDn and RXDn n 0 1 The CSI performs data transfer using pins SOn SIn and SCKn n 0 1 11 A D converter ADC Two circuits of high speed high resolution 10 bit A D converters with a total of 14 pins A D converter 0 6 pins A D converter 1 8 pins are available The ADC converts using a successive approximation method 12 Ports As shown in the table below ports function as general purpose ports and ...

Page 28: ...dge is input the port functions as an NMI input INTP4 TO3OFF P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 I O Port 1 3 bit I O port Input or output can be specified in 1 bit units TCLR10 INTP101 P20 TI2 INTP20 P21 TO21 INTP21 P22 TO22 INTP22 P23 TO23 INTP23 P24 TO24 INTP24 P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 P27 I O Port 2 8 bit I O port Input or output can be specified in 1 bit units TO3 INTP31 P30 R...

Page 29: ...ified in 1 bit units ASTB PDH0 A16 PDH1 A17 PDH2 A18 PDH3 A19 PDH4 A20 PDH5 I O Port DH 6 bit I O port Input or output can be specified in 1 bit units A21 PDL0 AD0 PDL1 AD1 PDL2 AD2 PDL3 AD3 PDL4 AD4 PDL5 AD5 PDL6 AD6 PDL7 AD7 PDL8 AD8 PDL9 AD9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL13 AD13 PDL14 AD14 PDL15 I O Port DL 16 bit I O port Input or output can be specified in 1 bit units AD15 ...

Page 30: ...00 or 01 output stop signal input P02 INTP1 TIUD10 Input External count clock input to up down counter timer 10 P10 TO10 TCUD10 Input Count operation switching signal to up down counter timer 10 P11 INTP100 TCLR10 Input Clear signal input to up down counter timer 10 P12 INTP101 TI2 P20 INTP20 TI3 Input Timer 2 or 3 external count clock input P26 INTP30 TCLR3 TCLR2 P25 INTP25 TCLR3 Input Timer 2 or...

Page 31: ... and UART1 P32 SI1 ASCK1 I O UART1 serial clock I O P34 SCK1 ANI00 to ANI05 ANI10 to ANI17 Input Analog input to A D converter ADTRG0 P03 INTP2 ADTRG1 Input External trigger input to A D converter P04 INTP3 NMI Input Non maskable interrupt request input P00 MODE0 MODE1 Input Specifies V850E IA2 operation mode VPP Note VPP Note Power application for flash memory write MODE1 WAIT Input Control signa...

Page 32: ...D converter AVSS0 AVSS1 Ground potential for A D converter CVSS Ground potential for oscillator PLL and regulator VDD 5 V system positive power supply for peripheral interface VSS 5 V system ground potential for peripheral interface RVDD Positive power supply pin for regulator 5 V system power supply pin VSS3 Internal 3 3 V system ground pin REGOUT Output Regulator output pin REGIN Input Regulator...

Page 33: ...e HALT Mode During DMA Transfer A16 to A21 PDH0 to PDH5 Hi Z Hi Z Hi Z Operating AD0 to AD15 PDL0 to PDL15 Hi Z Hi Z Hi Z Operating LWR UWR PCT0 PCT1 Hi Z Hi Z H Operating RD PCT4 Hi Z Hi Z H Operating ASTB PCT6 Hi Z Hi Z H Operating WAIT PCM0 Hi Z Hi Z Operating CLKOUT PCM1 Hi Z Operating L Operating Caution When controlling the external bus using an ASIC or the like in standby mode provide a sep...

Page 34: ... input pin timer counter output stop signal input pin external interrupt request input pin A D converter ADC external trigger input pin and timer 3 output stop signal input pin Read the status of each pin by reading the port a Port mode P00 to P05 are input only b Control mode P00 to P05 also serve as the NMI ESO0 ESO1 ADTRG0 ADTRG1 INTP0 to INTP4 and TO3OFF pins but they cannot be switched i NMI ...

Page 35: ... bit units using the port 1 mode register PM1 b Control mode P10 to P12 can be set to port or control mode in 1 bit units using PMC1 i TO10 Timer output Output This pin outputs the timer 10 pulse signal ii TIUD10 Timer count pulse input Input This is an external count clock input pin to the up down counter timer 10 iii TCUD10 Timer control pulse input Input This pin inputs count operation switchin...

Page 36: ... register PM2 b Control mode P20 to P27 can be set to port or control mode in 1 bit units using PMC2 i TO21 to TO24 Timer output Output These pins output a timer 2 pulse signal ii TO3 Timer output Output This pin outputs a timer 3 pulse signal iii TI2 TI3 Timer input Input These are timer 2 and timer 3 external count clock input pins iv TCLR2 TCLR3 Timer clear Input These are timer 2 and timer 3 c...

Page 37: ...ontrol register PFC3 a Port mode P30 to P34 can be set to input or output in 1 bit units using the port 3 mode register PM3 b Control mode P30 to P34 can be set to port or control mode in 1 bit units using PMC3 i TXD0 TXD1 Transmit data Output These pins output serial transmit data of UART0 and UART1 ii RXD0 RXD1 Receive data Input These pins input serial receive data of UART0 and UART1 iii ASCK1 ...

Page 38: ...as a port in control mode PCM0 and PCM1 operate as wait insertion signal input and internal system clock output Port or control mode can be selected as the operation mode for each bit specified by the port CM mode control register PMCCM a Port mode PCM0 and PCM1 can be set to input or output in 1 bit units using the port CM mode register PMCM b Control mode PCM0 and PCM1 can be set to port or cont...

Page 39: ...e bus cycle is a lower memory write it becomes active at the falling edge of the CLKOUT signal in the T1 state and becomes inactive at the falling edge of the CLKOUT signal in the T2 state ii UWR Higher byte write strobe Output This is a strobe signal that shows that the bus cycle being executed is a write cycle for SRAM external ROM or an external peripheral I O area In the data bus the higher by...

Page 40: ...l expansion mode these pins operate as the address data bus AD0 to AD15 for when memory is expanded externally Port or control mode can be selected as the operation mode for each bit specified by the port DL mode control register PMCDL a Port mode PDL0 to PDL15 can be set to input or output in 1 bit units using the port DL mode register PMDL b Control mode PDL0 to PDL15 can be specified as AD0 to ...

Page 41: ... mode Single chip mode 7 8 V H Flash memory programming mode Other than above Setting prohibited Remark L Low level input H High level input 15 RESET Reset Input RESET input is asynchronous input When a signal having a certain low level width is input in asynchronous with the operation clock a system reset that takes precedence over all operations occurs Besides a normal initialize or start this s...

Page 42: ...This is the internal 3 3 V system ground pin 22 REGOUT Regulator output Output This is the regulator output pin 23 REGIN Regulator input Input This is the regulator input pin Supply 3 3 V system power to this pin 24 AVDD0 AVDD1 Analog power supply These are the analog positive power supply pins for the A D converter 25 AVSS0 AVSS1 Analog ground These are the ground pins for the A D converter ...

Page 43: ...ectly to VSS P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P20 TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 P27 TO3 INTP31 P30 RXD0 5 AC P31 TXD0 5 P32 RXD1 SI1 5 AC P33 TXD1 SO1 5 P34 ASCK1 SCK1 P40 SI0 5 AC P41 SO0 5 P42 SCK0 5 AC PCM0 WAIT PCM1 CLKOUT PCT0 LWR PCT1 UWR PCT4 RD PCT6 ASTB PDH0 A16 to PDH5 A21 PDL0 AD0 to PDL15 AD15 5 Input Independen...

Page 44: ...NS 44 User s Manual U15195EJ5V0UD 2 2 Pin I O Circuit Type Recommended Connection MODE0 VPP Note MODE1 RESET CKSEL 2 X2 Leave open AVSS0 AVSS1 Connect to VSS AVDD0 AVDD1 Connect to VDD REGOUT Leave open Note µPD70F3114 only ...

Page 45: ...sis characteristics IN Type 4 Push pull output with possible high impedance output P ch N ch both off Data Output disable P ch OUT VDD N ch Type 5 Data Output disable P ch IN OUT VDD N ch Input enable Type 5 AC Type 7 IN Comparator _ VREF threshold voltage P ch N ch P ch N ch VDD IN OUT Data Output disable Input enable ...

Page 46: ...on execution time 25 ns internal 40 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction Load store instructions in long short format Four types of bit manipulation instr...

Page 47: ...r25 r26 r27 r28 r29 r30 r31 Zero register Assembler reserved register Stack pointer SP Global pointer GP Text pointer TP Element pointer EP Link pointer LP PC Program counter PSW Program status word ECR Interrupt source register FEPC FEPSW Status saving register during NMI Status saving register during NMI EIPC EIPSW Status saving register during interrupt Status saving register during interrupt 3...

Page 48: ...ers Name Usage Operation r0 Zero register Always holds 0 r1 Assembler reserved register Working register for generating address r2 Address data variable register when not being used by the real time OS r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text area wh...

Page 49: ...anteed 16 Status saving register during CALLT execution CTPC 17 Status saving register during CALLT execution CTPSW 18 Status saving register during exception debug trap DBPC Note 2 Note 2 19 Status saving register during exception debug trap DBPSW Note 2 Note 2 20 CALLT base pointer CTBP 21 to 31 Reserved number for future function expansion operations that access these register numbers cannot be...

Page 50: ...n or maskable interrupt occurs is saved to EIPC except for some instructions refer to 7 8 Periods in Which CPU Does Not Acknowledge Interrupts The current PSW contents are saved to EIPSW Since there is only one set of interrupt status saving registers the contents of these registers must be saved by the program when multiple interrupt servicing is enabled Bits 31 to 26 of EIPC and bits 31 to 8 of ...

Page 51: ...ETI instruction has been executed the values of FEPC and FEPSW are restored to the PC and PSW respectively 31 0 FEPC PC contents saved 0 0 After reset 0xxxxxxxH x Undefined 2625 0 0 0 0 31 0 FEPSW PSW contents saved 0 0 After reset 000000xxH x Undefined 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 3 Interrupt source register ECR Upon occurrence of an interrupt or an exception the interrupt sour...

Page 52: ...t requests can be acknowledged even when this bit is set 0 Exception processing not in progress 1 Exception processing in progress 5 ID Indicates whether maskable interrupt request acknowledgment is enabled 0 Interrupt enabled EI 1 Interrupt disabled DI 4 SAT Note Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated Si...

Page 53: ...ctual operation result 5 CALLT execution status saving registers CTPC CTPSW There are two CALLT execution status saving registers CTPC and CTPSW When the CALLT instruction is executed the contents of the program counter PC are saved to CTPC and the program status word PSW contents are saved to CTPSW The contents saved to CTPC consist of the address of the next instruction after the CALLT instructi...

Page 54: ... only in the period between DBTRAP instruction execution and DBRET instruction execution Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved fixed to 0 for future function expansion When the DBRET instruction has been executed the values of DBPC and DBPSW are restored to the PC and PSW respectively 31 0 DBPC PC contents saved 0 0 After reset 0xxxxxxxH x Undefined 2625 0 0 0 0 31 0 DBPSW P...

Page 55: ...on an external device can be connected to the external memory area b ROMless mode After the system reset is cleared each pin related to the bus interface enters the control mode program execution branches to the external device s memory reset entry address and instruction processing starts Fetching of instructions and data access for internal ROM becomes impossible In ROMless mode the data bus is ...

Page 56: ...ed during operation a µPD703114 MODE1 MODE0 Operation Mode Remark L L ROMless mode 16 bit data bus L H Normal operation mode Single chip mode Internal ROM area is allocated from address 000000H Other than above Setting prohibited b µPD70F3114 MODE1 VPP MODE0 Operation Mode Remark L L ROMless mode 16 bit data bus L H Normal operation mode Single chip mode Internal ROM area is allocated from address...

Page 57: ... up to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 1 shows the CPU address space Figure 3 1 CPU Address Space FFFFFFFFH 04000000H 03FFFFFFH 00000000H Data area 4 GB linear Program area 64 MB linear CPU address space ...

Page 58: ...ows the image of the virtual addressing space Physical address x0000000H can be seen as CPU address 00000000H and in addition can be seen as address 10000000H address 20000000H address E0000000H or address F0000000H Figure 3 2 Image on Address Space FFFFFFFFH F0000000H EFFFFFFFH 00000000H Internal ROM Image Image Image Internal RAM On chip peripheral I O External memory Physical address space FFFF...

Page 59: ...ecome contiguous Caution The 4 KB area of 03FFF000H to 03FFFFFFH can be seen as an image of 0FFFF000H to 0FFFFFFFH No instruction can be fetched from this area because this area is defined as on chip peripheral I O area Therefore do not execute any branch address calculation in which the result will reside in any part of this area 03FFFFFEH 03FFFFFFH 00000000H 00000001H Program space Program space...

Page 60: ...l RAM area On chip peripheral I O area Internal RAM area Access prohibitedNote Internal ROM area External memory area of V850E IA2 Single chip mode ROMless mode 256 MB 1 MB 1 MB 4 KB xFFFF000H xFFFEFFFH x0200000H x01FFFFFH x0100000H x00FFFFFH x0000000H xFFFD800H xFFFD7FFH xFFFC000H xFFFBFFFH 6 KB 4 MB x0400000H x03FFFFFH Note By setting the PMCDH PMCDL PMCCT and PMCCM registers to control mode thi...

Page 61: ...OM internal flash memory area addresses 00000H to FFFFFH is reserved Actually internal ROM internal flash memory of 128 KB is mapped to addresses 000000H to 01FFFFH Addresses 020000H to 0FFFFFH are undefined Figure 3 4 Internal ROM Internal Flash Memory Area Undefined Internal ROM internal flash memory area 0FFFFFH 020000H 01FFFFH 000000H ...

Page 62: ...Exception Table Interrupt Exception Source 00000000H RESET 00000230H INTP24 INTCC24 00000010H NMI0 00000240H INTP25 INTCC25 00000040H TRAP0n n 0 to F 00000250H INTTM3 00000050H TRAP1n n 0 to F 00000260H INTP30 INTCC30 00000060H ILGOP DBG0 00000270H INTP31 INTCC31 00000080H INTP0 00000280H INTCM4 00000090H INTP1 00000290H INTDMA0 000000A0H INTP2 000002A0H INTDMA1 000000B0H INTP3 000002B0H INTDMA2 0...

Page 63: ...ernal RAM area The 12 KB area of 3FFC000H to 3FFEFFFH can be seen as an image of FFFC000H to FFFEFFFH In the V850E IA2 6 KB of memory addresses FFFC000H to FFFD7FFH are provided as physical internal RAM Access to the area of addresses FFFD800H to FFFEFFFH is prohibited Internal RAM area 6 KB FFFEFFFH FFFD800H FFFD7FFH FFFC000H Access prohibited ...

Page 64: ...d because of the hardware specification 2 In the V850E IA2 no registers exist that are capable of word access but if a register is word accessed halfword access is performed twice in the order of lower address then higher address of the word area ignoring the lower 2 bits of the address 3 For registers in which byte access is possible if halfword access is executed the higher 8 bits become undefin...

Page 65: ...he operating mode specification set by the MODE0 and MODE1 pins refer to 3 3 Operation Modes for details of the operation modes a In the case of ROMless mode Because each pin of ports DH DL CT and CM enters control mode following a reset external memory can be used without making changes to the port n mode control register PMCn the external data bus width is 16 bits b In the case of single chip mo...

Page 66: ...us 64 MB space starting from address 00000000H corresponds to the memory map of the program space 2 Data space For the efficient use of resources that make use of the wrap around feature of the data space the continuous 16 MB address spaces 00000000H to 00FFFFFFH and FF000000H to FFFFFFFFH of the 4 GB CPU are used as the data space With the V850E IA2 a 256 MB physical address space is seen as 16 i...

Page 67: ...H xFFFFA78H xFFFFA77H Data space Program space On chip peripheral I O On chip peripheral I O Internal RAM Internal RAM Internal ROM External memory of V850E IA2 External memory of V850E IA2 Internal RAM On chip peripheral I ONote Program space 64 MB Internal ROM Internal ROM x0400000H x03FFFFFH 00400000H 003FFFFFH External memory of V850E IA2 Note Access to this area is prohibited To access the on...

Page 68: ... control register PMCCM R W 00H 03H FFFFF060H Chip area selection control register 0 CSC0 R W 2C11H FFFFF062H Chip area selection control register 1 CSC1 R W 2C11H FFFFF066H Bus size configuration register BSC R W 5555H FFFFF06EH System wait control register VSWC R W 77H FFFFF080H DMA source address register 0L DSA0L R W Undefined FFFFF082H DMA source address register 0H DSA0H R W Undefined FFFFF0...

Page 69: ...ister DRST R W 00H FFFFF100H Interrupt mask register 0 IMR0 R W FFFFH FFFFF100H Interrupt mask register 0L IMR0L R W FFH FFFFF101H Interrupt mask register 0H IMR0H R W FFH FFFFF102H Interrupt mask register 1 IMR1 R W FFFFH FFFFF102H Interrupt mask register 1L IMR1L R W FFH FFFFF103H Interrupt mask register 1H IMR1H R W FFH FFFFF104H Interrupt mask register 2 IMR2 R W FFFFH FFFFF104H Interrupt mask...

Page 70: ...control register CM4IC0 R W 47H FFFFF152H Interrupt control register DMAIC0 R W 47H FFFFF154H Interrupt control register DMAIC1 R W 47H FFFFF156H Interrupt control register DMAIC2 R W 47H FFFFF158H Interrupt control register DMAIC3 R W 47H FFFFF162H Interrupt control register CSIIC0 R W 47H FFFFF164H Interrupt control register CSIIC1 R W 47H FFFFF166H Interrupt control register SRIC0 R W 47H FFFFF...

Page 71: ...register 05 ADCR05 R 0000H FFFFF240H A D scan mode register 10 ADSCM10 R W 0000H FFFFF240H A D scan mode register 10L ADSCM10L R W 00H FFFFF241H A D scan mode register 10H ADSCM10H R W 00H FFFFF242H A D scan mode register 11 ADSCM11 R W 0000H FFFFF242H A D scan mode register 11L ADSCM11L R 00H FFFFF243H A D scan mode register 11H ADSCM11H R W 00H FFFFF244H A D voltage detection mode register 1 ADE...

Page 72: ...nfiguration register 1 BCT1 R W CCCCH FFFFF484H Data wait control register 0 DWC0 R W 3333H FFFFF486H Data wait control register 1 DWC1 R W 3333H FFFFF488H Address wait control register AWC R W 0000H FFFFF48AH Bus cycle control register BCC R W AAAAH FFFFF540H Timer 4 TM4 R 0000H FFFFF542H Compare register 4 CM4 R W 0000H FFFFF544H Timer control register 4 TMC4 R W 00H FFFFF570H Dead time timer re...

Page 73: ...lock selection register PRM02 R W 00H FFFFF5DCH Buffer register CM14 BFCM14 R W FFFFH FFFFF5DEH Buffer register CM15 BFCM15 R W FFFFH FFFFF5E0H Timer 10 TM10 R W 0000H FFFFF5E2H Compare register 100 CM100 R W 0000H FFFFF5E4H Compare register 101 CM101 R W 0000H FFFFF5E6H Capture compare register 100 CC100 R W 0000H FFFFF5E8H Capture compare register 101 CC101 R W 0000H FFFFF5EAH Capture compare co...

Page 74: ...ister 0 TCRE0 R W 0000H FFFFF646H Timer 2 time base control register 0L TCRE0L R W 00H FFFFF647H Timer 2 time base control register 0H TCRE0H R W 00H FFFFF648H Timer 2 output control register 0 OCTLE0 R W 0000H FFFFF648H Timer 2 output control register 0L OCTLE0L R W 00H FFFFF649H Timer 2 output control register 0H OCTLE0H R W 00H FFFFF64AH Timer 2 subchannel 0 5 capture compare control register C...

Page 75: ... R W 00H FFFFF669H Timer 2 output delay register 0H ODELE0H R W 00H FFFFF66AH Timer 2 software event capture register CSCE0 R W 0000H FFFFF680H Timer 3 TM3 R 0000H FFFFF682H Capture compare register 30 CC30 R W 0000H FFFFF684H Capture compare register 31 CC31 R W 0000H FFFFF686H Timer control register 30 TMC30 R W 00H FFFFF688H Timer control register 31 TMC31 R W 20H FFFFF689H Valid edge selection...

Page 76: ...r register 0 SOTBF0 R W 0000H FFFFF908H Clocked serial interface initial transmit buffer register L0 SOTBFL0 R W 00H FFFFF90AH Serial I O shift register 0 SIO0 R 0000H FFFFF90AH Serial I O shift register L0 SIOL0 R 0000H FFFFF910H Clocked serial interface mode register 1 CSIM1 R W 00H FFFFF911H Clocked serial interface clock selection register 1 CSIC1 R W 00H FFFFF912H Clocked serial interface rec...

Page 77: ...nterface transmit status register 0 ASIF0 R 00H FFFFFA06H Clock select register 0 CKSR0 R W 00H FFFFFA07H Baud rate generator control register 0 BRGC0 R W FFH FFFFFA20H 2 frame continuous reception buffer register 1 RXB1 R Undefined FFFFFA22H Receive buffer register L1 RXBL1 R Undefined FFFFFA24H 2 frame continuous transmission shift register 1 TXS1 W Undefined FFFFFA26H Transmit shift register L1...

Page 78: ...o this register Set value of VSWC 02H when two wait clocks are set with operating frequency fXX 40 MHz This register can be read written in 8 bit units address FFFFF06EH after reset 77H Remark If the timing at which the flag or count value changes overlaps the register access timing when a register that includes a status flag indicating the status of on chip peripheral functions ASIF0 etc or a reg...

Page 79: ...eg1 reg2 subr reg1 reg2 cmp reg1 reg2 sar imm5 reg2 satsub reg1 reg2 xor reg1 reg2 sub reg1 reg2 cmp imm5 reg2 shl imm5 reg2 Example i ld w r11 r10 If the decode operation of the mov instruction ii immediately before the sld instruction iii and an interrupt request conflict before execution of the ld instruction i is complete the execution result of instruction i may not be stored in a register ii...

Page 80: ...trol Mode Switching Address data bus AD0 to AD15 PDL0 to PDL15 port DL PMCDL Address bus A16 to A21 PDH0 to PDH5 port DH PMCDH Read write control LWR UWR RD ASTB PCT0 PCT1 PCT4 PCT6 port CT PMCCT External wait control WAIT PCM0 port CM Internal system clock CLKOUT PCM1 port CM PMCCM Remark In the case of ROMless mode when the system is reset each bus control pin becomes valid unconditionally 4 2 1...

Page 81: ...ernal memory area External memory area FFFC000H FE00000H FDFFFFFH FFFF000H FFFEFFFH FC00000H FBFFFFFH FA00000H F9FFFFFH F800000H F7FFFFFH C000000H BFFFFFFH 8000000H 7FFFFFFH 4000000H 3FFFFFFH 0800000H 07FFFFFH 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 1 2 MB Block 0 2 MB Block 2 2 MB Block 3 2 MB 64 MB 64 MB Block 5 2 MB Block 6 2 MB Block 4 2 MB Block 7 2 MB 3FFFFFFH On...

Page 82: ...itten in 16 bit units and become valid by setting each bit to 1 Only the CS01 and CS00 bits of the CSC0 register are valid in the V850E IA2 These registers are not affected by other bit settings In the V850E IA2 set the CS01 and CS00 bits to 11B so that CS0 is output to both block 0 and 1 If different chip select signal outputs are set to the same block the priority order is controlled as follows ...

Page 83: ...put during block 3 access CS30 to CS33 Note 2 CS40 to CS43 Note 3 CS50 CS5 output during block 7 access CS51 CS5 output during block 6 access CS52 CS5 output during block 5 access CS53 CS5 output during block 4 access CS60 to CS63 Note 4 CS70 CS7 output during block 7 access CS71 CS7 output during block 6 access CS72 CS7 output during block 5 access CS73 CS7 output during block 4 access 15 to 0 CS...

Page 84: ...ince CS0 has priority over CS2 CS0 is output if the addresses of block 0 and block 1 are accessed If the address of block 3 is accessed both the CS03 and CS23 bits of the CSC0 register are 0 and CS1 is output Figure 4 1 Example When CSC0 Register Is Set to 0703H 3FFFFFFH 0600000H 05FFFFFH 0800000H 07FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 2 2 MB Block 3 2 MB Block 1 2 MB Block 0 ...

Page 85: ... then do not change the set values Also do not access an external memory area other than the one for this initialization routine until the initial setting of the BCT0 and BCT1 registers is complete However it is possible to access external memory areas whose initial settings are complete 15 ME3 BCT0 CSn signal Address FFFFF480H After reset CCCCH 14 1 1 0 0 13 12 11 ME2 10 9 0 0 0 0 8 7 ME1 6 1 5 4...

Page 86: ... below Bus Cycle Status Resource Bus Width Instruction Fetch Operand Data Access Internal ROM 32 bits 1 Note 1 5 Internal RAM 32 bits 1 Note 2 1 On chip peripheral I O 16 bits 5 Note 3 External memory 16 bits 3 Note 3 3 Note 3 Notes 1 This value is 2 in the case of instruction branch 2 This value is 2 if there is conflict with data access 3 MIN value Remark Unit Clock access ...

Page 87: ...ot access an external memory area other than the one for this initialization routine until the initial setting of the BSC register is complete However it is possible to access external memory areas whose initial settings are complete 2 When the data bus width is specified as 8 bits only the signals shown below become active LWR When accessing SRAM external ROM or external I O write cycle 15 0 BSC ...

Page 88: ...rting from the lower side 1 Byte access 8 bits a When the data bus width is 16 bits little endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7 0 Byte data 15 8 External data bus 2n 1 Address b When the data bus width is 8 bits little endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data External data ...

Page 89: ...ord data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address b When the data bus width is 8 bits little endian 1 Access to even address 2n 2 Access to odd address 2n 1 1st access 2nd access 1st access 2nd access 7 0 7 0 Halfword data 15 8 External data bus Address 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 2n 7 0 7 0 Halfword data ...

Page 90: ... External data bus 4n Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 2 Access to address 4n 1 1st access 2nd access 3rd access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 23 16 31...

Page 91: ...ata bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 4 Access to address 4n 3 1st access 2nd access 3rd access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 6 Address 15 8 23 16 31 24 ...

Page 92: ...Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 2 Access to address 4n 1 1st access 2nd access 3rd access 4th access 7 0 7 0 Word data External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 A...

Page 93: ...3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 4 Access to address 4n 3 1st access 2nd access 3rd access 4th access 7 0 7 0 Word data External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5...

Page 94: ...ogrammable wait states with wait control performed by each peripheral function only 2 Write to the DWC0 and DWC1 registers after reset and then do not change the set values Also do not access an external memory area other than the one for this initialization routine until the initial setting of the DWC0 and DWC1 registers is complete However it is possible to access external memory areas whose ini...

Page 95: ...ister after reset and then do not change the set values CS4 CS0 AWC CSn signal 15 AHW7 14 ASW7 13 AHW6 12 ASW6 11 AHW5 10 ASW5 9 AHW4 8 ASW4 7 AHW3 6 ASW3 5 AHW2 4 ASW2 3 AHW1 2 ASW1 1 AHW0 0 ASW0 Address FFFFF488H After reset 0000H CS7 CS6 CS5 CS3 CS2 CS1 Bit position Bit name Function 15 13 11 9 7 5 3 1 AHWn n 0 to 7 Sets the insertion of an address hold wait state in each CSn space after the T1...

Page 96: ...the T2 and TW states of the bus cycle If the setup hold time is not satisfied within the sampling timing a wait state may or may not be inserted in the next state 4 6 3 Relationship between programmable wait and external wait A wait cycle is inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WA...

Page 97: ...ol register BCC This register can be read written in 16 bit units Only the BC01 bit is valid in the V850E IA2 This register is not affected by other bit settings Cautions 1 Idle states cannot be inserted in internal ROM internal RAM or on chip peripheral I O areas 2 Write to the BCC register after reset and then do not change the set values Also do not access an external memory area other than the...

Page 98: ...followed by operand data access and instruction fetch in that order An instruction fetch may be inserted between a read access and write access during a read modify write access Also an instruction fetch may be inserted between bus accesses when the CPU bus is locked Table 4 1 Bus Priority Order Priority Order External Bus Cycle Bus Master DMA cycle DMA controller Operand data access CPU High Low ...

Page 99: ...pace The V850E IA2 is provided with an address misalign function Through this function regardless of the data format word data halfword data or byte data data can be allocated to all addresses However in the case of word data and halfword data if the data is not subject to boundary alignment the bus cycle will be generated at least 2 times and bus efficiency will drop 1 In the case of halfword len...

Page 100: ...imum of 3 states A maximum of 7 programmable data wait states can be inserted according to DWC0 and DWC1 register settings Data waits can be controlled by WAIT pin input An idle state 1 state can be inserted after a read write cycle by setting the BCC register An address hold wait state or address setup wait state can be inserted by setting the AWC register ...

Page 101: ...ess Figure 5 1 SRAM External ROM External I O Access Timing 1 4 a When reading 1 wait inserted T1 T2 TW T3 Address Data H CLKOUT output A16 to A21 output AD0 to AD15 I O ASTB output RD output UWR LWR output WAIT input Address Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance ...

Page 102: ...ess Timing 2 4 b When reading 0 waits address setup waits address hold wait states inserted TASW T1 TAHW Address Address T2 T3 Data H CLKOUT output A16 to A21 output AD0 to AD15 I O ASTB output RD output UWR LWR output WAIT input Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance ...

Page 103: ...Address DataNote H CLKOUT output A16 to A21 output AD0 to AD15 I O ASTB output RD output UWR LWR output WAIT input Address Note AD0 to AD7 output invalid data when odd numbered address byte data is accessed AD8 to AD15 output invalid data when even numbered address byte data is accessed Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance ...

Page 104: ... inserted for 8 bit data bus T1 T2 T3 Address Address Address H CLKOUT output A16 to A21 output AD8 to AD15 I O AD0 to AD7 I O ASTB output RD output UWR LWR output WAIT input DataNote Note AD0 to AD7 output invalid data when odd numbered address byte data is accessed Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance ...

Page 105: ...timer counter and A D converter or software triggers memory refers to internal RAM or external memory 6 1 Features Four independent DMA channels Transfer unit 8 16 bits Maximum transfer count 65 536 216 Two cycle transfer Three transfer modes Single transfer mode Single step transfer mode Block transfer mode Transfer requests Request by interrupts from on chip peripheral I O serial interface timer...

Page 106: ... control Channel control DMAC V850E IA2 Bus interface External bus External RAM External ROM External I O DMA source address register DSAnH DSAnL DMA transfer count register DBCn DMA channel control register DCHCn DMA destination address register DDAnH DDAnL DMA addressing control register DADCn DMA disable status register DDIS DMA trigger factor register DTFRn DMA restart register DRST Remark n 0...

Page 107: ...autions 1 When setting an address of an on chip peripheral I O register for the source address be sure to specify an address between FFFF000H and FFFFFFFH An address of the on chip peripheral I O register image 3FFF000H to 3FFFFFFH must not be specified 2 Do not set the DSAnH register while DMA is suspended 15 IR DSA0H Address FFFFF082H After reset Undefined 14 0 13 0 12 0 11 SA27 10 SA26 9 SA25 8...

Page 108: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SA0 SA15 DSA1L Address FFFFF088H After reset Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA15 DSA2L Address FFFFF090H After reset Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA15 DSA3L Address FFFFF098H After reset Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 ...

Page 109: ...en setting an address of an on chip peripheral I O register for the destination address be sure to specify an address between FFFF000H and FFFFFFFH An address of the on chip peripheral I O register image 3FFF000H to 3FFFFFFH must not be specified 2 Do not set the DDAnH register while DMA is suspended 15 IR DDA0H Address FFFFF086H After reset Undefined 14 0 13 0 12 0 11 DA27 10 DA26 9 DA25 8 DA24 7...

Page 110: ...2 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DA0 DA15 DDA1L Address FFFFF08CH After reset Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA15 DDA2L Address FFFFF094H After reset Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA15 DDA3L Address FFFFF09CH After reset Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA...

Page 111: ... count set to one the set value of the DBCn register is 0000H twice 2 Do not set the DBCn register while DMA is suspended Remark If the DBCn register is read after a terminal count has occurred during DMA transfer without the value of the DBCn register rewritten the value set immediately before DMA transfer is read 0000H is not read even after completion of transfer 15 BC15 DBC0 Address FFFFF0C0H ...

Page 112: ... system reset to the generation of the first DMA transfer Time from DMA transfer end after terminal count to the generation of the next DMA transfer request Time from the forcible termination of DMA transfer after the INITn bit of DMA channel control register n DCHCn has been set to 1 to the generation of the next DMA transfer request 1 2 15 DS1 DADC0 Address FFFFF0D0H After reset 0000H 14 DS0 13 ...

Page 113: ... 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited 7 6 SAD1 SAD0 Sets the count direction of the destination address for DMA channel n n 0 to 3 DAD1 DAD0 Count direction 0 0 Increment 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited 5 4 DAD1 DAD0 Sets the transfer mode during DMA transfer TM1 TM0 Transfer mode 0 0 Single transfer mode 0 1 Single step transfer mode 1 0 Setting prohibited 1 1 Block trans...

Page 114: ...nsfer request Time from DMA transfer end after terminal count to the generation of the next DMA transfer request Time from the forcible termination of DMA transfer after the INITn bit has been set to 1 to the generation of the next DMA transfer request 3 If DMA transfer is forcibly terminated in the last transfer cycle with the MLEn bit set to 1 the same operations as transfer completion setting o...

Page 115: ...t DMA transfer start factor is the setting of the STGn bit to 1 software DMA the DMA transfer start factor can be acknowledged by reading and clearing the TCn bit to 0 When this bit is cleared to 0 when DMA transfer is complete at terminal count output the Enn bit is cleared to 0 and the DMA transfer disable state is entered At the next DMA transfer request the setting of the Enn bit to 1 and the ...

Page 116: ...t of the DRST register and the Enn bit of the DCHCn register are linked to each other the Enn bit can also be used to set the enabling or disabling of DMA transfer independently for four channels and the DRST register can be used to set the enabling or disabling of DMA transfer for four channels at the same time n 0 to 3 This register can be read written in 8 bit units Be sure to set bits 7 to 4 t...

Page 117: ...g the IFCn5 to IFCn0 bits be sure to clear 0 the DFn bit with the instruction immediately after the change 1 3 7 DTFR0 6 5 4 3 2 1 0 DF0 0 IFC05 IFC04 IFC03 IFC02 IFC01 IFC00 Address FFFFF810H After reset 00H 7 DTFR1 6 5 4 3 2 1 0 DF1 0 IFC15 IFC14 IFC13 IFC12 IFC11 IFC10 Address FFFFF812H After reset 00H 7 DTFR2 6 5 4 3 2 1 0 DF2 0 IFC25 IFC24 IFC23 IFC22 IFC21 IFC20 Address FFFFF814H After reset...

Page 118: ...DET0 0 0 1 0 0 1 INTDET1 0 0 1 0 1 0 INTTM00 0 0 1 0 1 1 INTCM003 0 0 1 1 0 0 INTTM01 0 0 1 1 0 1 INTCM013 0 0 1 1 1 0 INTP100 INTCC100 0 0 1 1 1 1 INTP101 INTCC101 0 1 0 0 0 0 INTCM100 0 1 0 0 0 1 INTCM101 0 1 0 1 1 0 INTTM20 0 1 0 1 1 1 INTTM21 0 1 1 0 0 0 INTP20 INTCC20 0 1 1 0 0 1 INTP21 INTCC21 0 1 1 0 1 0 INTP22 INTCC22 0 1 1 0 1 1 INTP23 INTCC23 0 1 1 1 0 0 INTP24 INTCC24 0 1 1 1 0 1 INTP25...

Page 119: ...TCM010 1 1 1 0 1 1 INTCM011 1 1 1 1 0 0 INTCM012 1 1 1 1 0 1 INTCM014 1 1 1 1 1 0 INTCM015 Other than above Setting prohibited 5 to 0 IFCn5 to IFCn0 Remark n 0 to 3 The relationship between the interrupt source and the DMA transfer trigger is as follows n 0 to 3 IFCn0 to IFCn5 Internal DMA request signal Interrupt source Selector Caution An interrupt request will be generated when DMA transfer sta...

Page 120: ...released for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figures 6 1 to 6 4 show examples of single transfer Figure 6 1 Single Transfer Example 1 CPU DMA3 CPU CPU DMA3 CPU CPU CPU CPU CPU DMA3 CPU DMA3 DMA3 CPU CPU CPU DMARQ3 Internal signal CPU CPU DMA channel 3 terminal count Note Note Note Note Note The bus is always released Figure 6 2 shows a single ...

Page 121: ...ote Note Note Internal signal Internal signal Note The bus is always released Figure 6 4 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within one clock after the end of a single transfer DMA channels 0 2 and 3 are used for a single transfer When three or more DMA transfer request signals are activated at the same time the two highest p...

Page 122: ... transfer Figure 6 6 shows a single step transfer mode example in which a higher priority DMA transfer request is generated and DMA channels 0 and 1 are set to the single step transfer mode Figure 6 5 Single Step Transfer Example 1 DMA1 CPU CPU CPU CPU CPU CPU CPU CPU DMA1 CPU CPU DMA1 DMA1 CPU DMARQ1 CPU CPU DMA channel 1 terminal count Note Note Note Internal signal Note The bus is always releas...

Page 123: ...e in the block transfer mode Figure 6 7 Block Transfer Example CPU CPU CPU DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 CPU DMA2 DMA2 DMA2 DMA2 DMA2 DMA channel 3 terminal count The bus is always released DMARQ3 internal signal DMARQ2 internal signal 6 5 Transfer Types 6 5 1 Two cycle transfer In two cycle transfer data transfer is performed in two cycles a read cycle source to DMAC and a write cycle D...

Page 124: ... I O register transfer source transfer destination be sure to specify the same transfer size as the register size For example in the case of DMA transfer to an 8 bit register be sure to specify byte 8 bit transfer 16 bit transfer Transfer from a 16 bit bus to an 8 bit bus A read cycle 16 bits is generated and then a write cycle 8 bits is generated twice successively Transfer from an 8 bit bus to a...

Page 125: ...MA channels using the same start factor If multiple channels are activated in this way a lower priority DMA channel may be acknowledged prior to a higher priority DMA channel 6 8 Next Address Setting Function The DMA source address registers DSAnH DSAnL DMA destination address registers DDAnH DDAnL and DMA transfer count register DBCn are 2 stage FIFO buffer registers configured with a master regi...

Page 126: ...ster register and not in the slave register the slave register maintains the value set for the next DMA transfer However the contents of the master register are automatically overwritten in the slave register after DMA transfer ends If the value of each register is read during this period the value of the slave register is read To check that DMA transfer has been started confirm that the first tra...

Page 127: ...f the STGn bit is manipulated next the second time without checking by software whether the single transfer has actually been executed the next second DMA transfer is not always executed This is because the STGn bit may be manipulated the second time before the first DMA transfer is started or completed because for example DMA transfer with a higher priority had already been started when the STGn ...

Page 128: ...fer disabled state is entered An NMI request can then be acknowledged after the DMA transfer executed during NMI input is terminated n 0 to 3 Initialize the DMA transfer that has been forcibly suspended by setting the INITn bit of the DCHCn register to 1 to forcibly terminate DMA transfer 6 11 DMA Transfer End When DMA transfer ends and the TCn bit of the DCHCn register is set to 1 a DMA transfer ...

Page 129: ...it 0 E33 bit 0 TC3 bit 1 b When transfer is suspended during DMA channel 1 block transfer and transfer under another condition is executed CPU CPU CPU CPU DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 CPU DMARQ1 internal signal Forcible termination of DMA channel 1 transfer bus released DMA channel 1 terminal count DSA1 DDA1 DBC1 DADC1 DCHC1 Register set DADC1 DCHC1 Register set DCH...

Page 130: ...en preventive processing routine ii in step 5 of the preventive processing is executed 1 Disable interrupts DI 2 Read the DMA restart register DRST and transfer the value in the ENn bit of each channel to general purpose registers value A 3 Write 00H to the DRST register write twiceNote Writing twice ensures that DMA transfer is stopped before the processing in step 4 4 Set the INITn bit of the DC...

Page 131: ...MA channels other than those subject to forcible termination are frequently performed Remark n 0 to 3 6 13 Time Required for DMA Transfer The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below Table 6 3 Minimum Number of Execution Clocks in DMA Cycle DMA Cycle Minimum Number of Execution Clocks 1 Response time to DMA request 4 clocks Note 1 Internal...

Page 132: ...e DMA channels are started with the same factor the DMA channel with a lower priority may be acknowledged before the DMA channel with a higher priority Operation is not guaranteed in this case 5 Program execution and DMA transfer with internal RAM Do not execute DMA transfer to from the internal RAM and an instruction in the internal RAM simultaneously 6 Restrictions related to automatic clearing ...

Page 133: ...FFH and the counting direction is incremental when the SADn1 and SADn0 bits of the DADCn register 00 the value of the DSAnL register differs as follows depending on whether DMA transfer is executed immediately after the DSAnH register has been read a If DMA transfer does not occur while the DSAn register is being read 1 Reading DSAnH register DSAnH 0000H 2 Reading DSAnL register DSAnL FFFFH b If D...

Page 134: ...ast 4 system clocks 100 ns 40 MHz following the generation of an interrupt request 7 1 Features Interrupts Non maskable interrupts 1 source Caution P00 alternately functions as NMI and is fixed to input P00 and NMI cannot be switched If the P00 bit of the P0 register is read the level of the P00 NMI pin is read Set the valid edge of the NMI pin using the ESN0 bit of the INTM0 register default valu...

Page 135: ...M00 8 0120H 00000120H nextPC Interrupt INTTM01 TM0IC1 TM01 underflow TM01 9 0130H 00000130H nextPC Interrupt INTCM013 CM03IC1 CM013 match TM01 10 0140H 00000140H nextPC Interrupt INTP100 INTCC100 CC10IC0 INTP100 pin CC100 match Pin TM10 11 0150H 00000150H nextPC Interrupt INTP101 INTCC101 CC10IC1 INTP101 INTP100 pinNote 3 CC101 match Pin TM10 12 0160H 00000160H nextPC Interrupt INTCM100 CM10IC0 CM...

Page 136: ...complete CSI1 32 0320H 00000320H nextPC Interrupt INTSR0 SRIC0 UART0 reception complete UART0 33 0330H 00000330H nextPC Interrupt INTST0 STIC0 UART0 transmission complete UART0 34 0340H 00000340H nextPC Interrupt INTSER0 SEIC0 UART0 receiver error UART0 35 0350H 00000350H nextPC Interrupt INTSR1 SRIC1 UART1 reception complete UART1 36 0360H 00000360H nextPC Interrupt INTST1 STIC1 UART1 transmissio...

Page 137: ...g instructions is being executed does not become the nextPC If an interrupt is acknowledged during instruction execution execution stops and then resumes after the interrupt servicing has finished In this case the address of the aborted instruction is the restore PC Load instructions SLD B SLD BU SLD H SLD HU SLD W Division instructions DIV DIVH DIVU DIVHU PREPARE DISPOSE instructions only if an i...

Page 138: ... bit 0 ESN0 of the external interrupt mode register 0 INTM0 is detected on the NMI pin the interrupt occurs While the service program of the non maskable interrupt is being executed the acknowledgment of another non maskable interrupt request is held pending The pending NMI is acknowledged after the original service program of the non maskable interrupt under execution has been terminated by the R...

Page 139: ...d FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address 00000010H corresponding to the non maskable interrupt to the PC and transfers control The servicing configuration of a non maskable interrupt is shown in Figure 7 1 Figure 7 1 Servicing Configuration of Non Maskable Interrupt PSW NP FEPC FEPSW ECR FECC PSW NP PSW EP PSW ID PC Restored PC PSW 0010H 1...

Page 140: ...uest PSW NP 1 NMI request held pending regardless of the value of the NP bit of the PSW Pending NMI request processed b If a new NMI request is generated twice while an NMI service program is being executed Main routine NMI request NMI request Held pending because NMI service program is being processed Only one NMI request is acknowledged even though two NMI requests are generated NMI request Held...

Page 141: ...is 1 2 Transfers control back to the address of the restored PC and PSW Figure 7 3 illustrates how the RETI instruction is processed Figure 7 3 RETI Instruction Processing PSW EP RETI instruction PSW NP Original processing restored 1 1 0 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt servicing in or...

Page 142: ...0 0 0 0 0 0 0 Bit position Bit name Function 7 NP Indicates whether NMI interrupt servicing is in progress 0 No NMI interrupt servicing 1 NMI interrupt currently being serviced 7 2 4 Edge detection function 1 External interrupt mode register 0 INTM0 External interrupt mode register 0 INTM0 is a register that specifies the valid edge of a non maskable interrupt NMI The NMI valid edge can be specifi...

Page 143: ...g a higher priority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority level cannot be nested However if multiple interrupts are executed the following processing is necessary 1 Save EIPC and EIPSW in memory or a general purpose register before executing the ...

Page 144: ...interrupt request Highest default priority of interrupt requests with the same priority EIPC EIPSW ECR EICC PSW EP PSW ID Corresponding bit of ISPRNote PC Restored PC PSW Exception code 0 1 1 Handler address Note For details of the ISPR register see 7 3 6 In service priority register ISPR The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is bei...

Page 145: ...Figure 7 5 illustrates the processing of the RETI instruction Figure 7 5 RETI Instruction Processing PSW EP RETI instruction PSW NP Restores original processing 1 1 0 0 PC PSW Corresponding bit of ISPRNote EIPC EIPSW 0 PC PSW FEPC FEPSW Note For details of the ISPR register see 7 3 6 In service priority register ISPR Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instructio...

Page 146: ...iority level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level beforehand For more information refer to Table 7 1 Interrupt Exception Source List The programmable priority control customizes interrupt requests into eight levels by setting the priority level speci...

Page 147: ...upt request d is higher than that of c d is held pending because interrupts are disabled Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g Interrupt request b level 2 Interrupt request d level 2 Interrupt request f level 3 Ca...

Page 148: ...d Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status Pending interrupt requests are acknowledged after servicing of interrupt request l At this time interrupt requests n is acknowledge...

Page 149: ...rvicing of interrupt request a Interrupt request b and c are acknowledged first according to their priorities Because the priorities of b and c are the same b is acknowledged first according to the default priority NMI request Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts When returning from multiple interrupt servicing restore the values of ...

Page 150: ...name Function 7 xxIFn This is an interrupt request flag 0 Interrupt request not issued 1 Interrupt request issued The flag xxlFn is reset automatically by the hardware if an interrupt request is acknowledged 6 xxMKn This is an interrupt mask flag 0 Enables interrupt servicing 1 Disables interrupt servicing pending 8 levels of priority order are specified for each interrupt xxPRn2 xxPRn1 xxPRn0 Int...

Page 151: ...PR10 FFFFF12AH CC10IC0 CC10IF0 CC10MK0 0 0 0 CC10PR02 CC10PR01 CC10PR00 FFFFF12CH CC1CIC1 CC10IF1 CC10MK1 0 0 0 CC10PR12 CC10PR11 CC10PR10 FFFFF12EH CM10IC0 CM10IF0 CM10MK0 0 0 0 CM10PR02 CM10PR01 CM10PR00 FFFFF130H CM10IC1 CM10IF1 CM10MK1 0 0 0 CM10PR12 CM10PR11 CM10PR10 FFFFF132H Not used Note FFFFF134H Not used Note FFFFF136H Not used Note FFFFF138H Not used Note FFFFF13AH TM2IC0 TM2IF0 TM2MK0 ...

Page 152: ...0 FFFFF168H STIC0 STIF0 STMK0 0 0 0 STPR02 STPR01 STPR00 FFFFF16AH SEIC0 SEIF0 SEMK0 0 0 0 SEPR02 SEPR01 SEPR00 FFFFF16CH SRIC1 SRIF1 SRMK1 0 0 0 SRPR12 SRPR11 SRPR10 FFFFF16EH STIC1 STIF1 STMK1 0 0 0 STPR12 STPR11 STPR10 FFFFF170H Not used Note FFFFF172H Not used Note FFFFF174H ADIC0 ADIF0 ADMK0 0 0 0 ADPR02 ADPR01 ADPR00 FFFFF176H ADIC1 ADIF1 ADMK1 0 0 0 ADPR12 ADPR11 ADPR10 FFFFF178H Not used N...

Page 153: ...0MK0 7 DETMK0 IMR0 14 CC10MK1 6 1 13 CC10MK0 5 1 12 CM03MK1 4 P0MK4 11 TM0MK1 3 P0MK3 10 CM03MK0 2 P0MK2 9 TM0MK0 1 P0MK1 8 DETMK1 0 P0MK0 Address FFFFF100H After reset FFFFH 15 CC3MK1 7 CC2MK0 IMR1 14 CC3MK0 6 TM2MK1 13 TM3MK0 5 TM2MK0 12 CC2MK5 4 1 11 CC2MK4 3 1 10 CC2MK3 2 1 9 CC2MK2 1 1 8 CC2MK1 0 CM10MK1 Address FFFFF102H After reset FFFFH 15 STMK1 7 1 IMR2 14 SRMK1 6 1 13 SEMK0 5 1 12 STMK0 ...

Page 154: ...s returned from non maskable interrupt servicing or exception processing This register is read only in 8 bit or 1 bit units Caution In the interrupt enabled EI state if an interrupt is acknowledged during the reading of the ISPR register the value of the ISPR register may be read after the bit is set 1 by this interrupt acknowledgment To read the value of the ISPR register properly before interrup...

Page 155: ...ble interrupt requests and exceptions are acknowledged regardless of this flag When a maskable interrupt is acknowledged the ID flag is automatically set to 1 by hardware The interrupt request generated during the acknowledgment disabled period ID 1 is acknowledged when the xxIFn bit of xxICn register is set to 1 and the ID flag is reset to 0 7 3 8 Interrupt trigger mode selection The valid edge o...

Page 156: ...mode register n0 ADSCMn0 setting the ES20 and ES21 and ES30 and ES31 bits of INTM1 also specifies the valid edge of the external trigger input ADTRG0 and ADTRG1 n 0 1 The valid edge can be specified independently for each pin rising edge falling edge or both rising and falling edges These registers can be read written in 8 bit or 1 bit units 7 ES31 INTM1 6 ES30 5 ES21 4 ES20 3 ES11 2 ES10 1 ES01 0...

Page 157: ...IUD10 TCUD10 or TCLR10 pin should be performed after setting the PMC1 register If the PMC1 register is set after setting the SESA10 register an invalid interrupt may occur when the PMC1 register is set 1 2 7 TESUD01 SESA10 6 TESUD00 5 CESUD01 4 CESUD00 3 IES1011 2 IES1010 1 IES1001 0 IES1000 Address FFFFF5EDH After reset 00H TIUD10 TCUD10 TCLR10 INTP101 INTP100 Bit position Bit name Function Speci...

Page 158: ...M10 holds cleared status while TCLR10 input is low level 11 TM10 holds cleared status while TCLR10 input is high level Caution The values set to the CESUD01 and CESUD00 bits are valid only in UDC mode A Note Specifies the valid edge of the pin selected using the CSL0 bit of the CSL10 register INTP101 INTP100 IES1011 IES1010 Valid edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Bot...

Page 159: ...30 and TO3 INTP31 pins as INTP30 and INTP31 even if not using timer 3 2 Setting the trigger mode of the INTP30 INTP31 TCLR3 or TI3 pin should be performed after setting the PMC2 register If the PMC2 register is set after setting the SESC register an invalid interrupt may occur when the PMC2 register is set 7 TES31 SESC 6 TES30 5 CES31 4 CES30 3 IES311 2 IES310 1 IES301 0 IES300 Address FFFFF689H A...

Page 160: ...h rising and falling edges These registers can be read written in 8 bit or 1 bit units Cautions 1 Be sure to clear 0 the STFTE bit of timer 2 clock stop register 0 STOPTE0 even when using the TI2 INTP20 TO21 INTP21 TO22 INTP22 TO23 INTP23 TO24 INTP24 and TCLR2 INTP25 pins as INTP20 INTP21 INTP22 INTP23 INTP24 and INTP25 respectively even if not using timer 2 2 Setting the trigger mode of the INTP2...

Page 161: ...EDGE004 1 TMS014 0 TMS004 Address FFFFF634H After reset 00H INTP24 7 DFEN05 FEM5 6 0 5 0 4 0 3 EDGE015 2 EDGE005 1 TMS015 0 TMS005 Address FFFFF635H After reset 00H INTP25 Bit position Bit name Function 7 DFEN0n Specifies the filter of the INTP2n pin 0 Analog filter 1 Digital filter Caution When the DFEN0n bit 1 the sampling clock of the digital filter is fXTM2 clock selected by the PRM02 register...

Page 162: ...0n Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers Set the TMS01m and TMS00m bits of the FEMm register to 00B or 01B All other settings are prohibited m 1 3 to 5 Subchannels 1 and 2 of timer 2 can be captured by INTP21 INTP22 and INTCM100 INTCM101 An example is given below a When subchannel 1 is captured by INTCM101 FEM1 register xxxxxx1...

Page 163: ...errupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 7 8 illustrates the processing of a software exception Figure 7 8 Software Exception Processing TRAP instruction EIPC EIPSW ECR EICC PSW EP PSW ID PC Restored PC PSW Exception code 1 1 Handler address CPU processing Exce...

Page 164: ... to the address of the restored PC and PSW Figure 7 9 illustrates the processing of the RETI instruction Figure 7 9 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception processing in order to restore the PC a...

Page 165: ...ed to indicate that exception processing is in progress It is set when an exception occurs 31 0 PSW After reset 00000020H 7 NP 6 EP 5 ID 4 SAT 3 CY 2 OV 1 S Z 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit position Bit name Function 6 EP Shows that exception processing is in progress 0 Exception processing not in progress 1 Exception processing in progress ...

Page 166: ...erated when an instruction applicable to this illegal instruction is executed 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to Arbitrary Caution Since it is possible that this instruction will be assigned to an illegal opcode in the future it is recommended that it not be used 1 Operation If an exception trap occurs the CPU performs the following processing and transfers control t...

Page 167: ...cessing is carried out by the DBRET instruction By executing the DBRET instruction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 7 11 illustrates the processing for restoring from an exception trap Figure 7 11 Processing for R...

Page 168: ...the CPU performs the following processing transfers control to the debug monitor routine and shifts to debug mode 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the debug trap to the PC and transfers control Figure 7 12 illustrates the processing of the debug trap Figure 7 12 Debug Trap ...

Page 169: ...ss of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Caution DBPC and DBPSW can be accessed during the period between when the DBTRAP is executed and when the DBRET instruction is executed Figure 7 13 illustrates the processing for restoring from a debug trap Figure 7 13 Processing for Restoring from Debug...

Page 170: ... processing control is executed when interrupts are enabled ID 0 Thus if multiple interrupts are executed it is necessary for interrupts to be enabled ID 0 even during an interrupt servicing routine If a maskable interrupt or a software exception is generated in a maskable interrupt or software exception service program it is necessary to save EIPC and EIPSW This is accomplished by the following p...

Page 171: ...rupt control request register xxlCn which is provided for each maskable interrupt request After system reset an interrupt request is masked by the xxMKn bit and the priority order is set to level 7 by the xxPRn0 to xxPRn2 bits The priority order of maskable interrupts is as follows High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt servicing that has been suspended ...

Page 172: ... Time Internal System Clock fXX External Interrupt Internal Interrupt INTP0 to INTP4 INTP20 to INTP25 INTP20 to INTP25 INTP100 INTP30 INTP101 INTP31 Condition Mini mum 4 4 analog delay time 4 digital noise filter 4 Note 1 digital noise filter Maxi mum 7 Note 2 7 analog delay time 7 digital noise filter 7 Note 1 digital noise filter The following cases are exceptions In IDLE software STOP mode Exte...

Page 173: ...ted registers Clocked serial interface mode registers 0 1 CSIM0 CSIM1 Clocked serial interface clock selection registers 0 1 CSIC0 CSIC1 Clocked serial interface receive buffer registers 0 1 SIRB0 SIRB1 Clocked serial interface receive buffer registers L0 L1 SIRBL0 SIRBL1 Clocked serial interface transmit buffer registers 0 1 SOTB0 SOTB1 Clocked serial interface transmit buffer registers L0 L1 SOT...

Page 174: ...tiplier function using a phase locked loop PLL synthesizer Clock sources Oscillation by connecting a resonator External clock Power saving modes HALT mode IDLE mode Software STOP mode Internal system clock output function 8 2 Configuration X1 X2 Clock generator CG CKSEL fX CPU on chip peripheral I O Time base counter TBC CLKOUT fXX Remark fX External resonator or external clock frequency fXX Inter...

Page 175: ... frequencies Caution In direct mode an external clock must be input an external resonator should not be connected 8 3 2 PLL mode In PLL mode an external resonator is connected or external clock is input and multiplied by the PLL synthesizer The multiplied PLL output is divided by the division ratio specified by the clock control register CKC to generate a system clock that is 10 5 2 5 or 1 times t...

Page 176: ...rs that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution This register is write only in 8 bit units when it is read undefined data is read out Writing to the first specific register CKC or FLPMC register is only valid after first writing to the PHCMD register Because of this the register value can be overwritten only i...

Page 177: ...he X1 and X2 pins 0 A resonator is connected to the X1 and X2 pins 1 An external clock is connected to the X1 pin When CESEL 1 the oscillator feedback loop is disconnected to prevent current leakage in software STOP mode Sets the internal system clock frequency fXX when PLL mode is used CKDIV2 CKDIV1 CKDIV0 Internal system clock fXX 0 0 0 fX 0 0 1 2 5 fX 0 1 1 5 fX 1 1 1 10 fX Other than above Set...

Page 178: ...alue written to PSW rY Value returned to PSW No special sequence is required to read the specific register Cautions 1 If an interrupt is acknowledged between the issuing of data to PHCMD 3 and writing to the specific register immediately after 4 the write operation to the specific register is not performed and a protection error the PRERR bit of the PHS register 1 may occur Therefore set the NP bi...

Page 179: ...1 bit units 7 6 5 4 3 2 1 0 Address After reset PHS 0 0 0 0 0 0 0 PRERR FFFFF802H 00H Bit position Bit name Function 0 PRERR 0 Protection error does not occur 1 Protection error occurs The operation conditions of the PRERR flag are as follows Set conditions 1 If the operation of the relevant store instruction for the on chip peripheral I O is not a write operation for the PHCMD register but the pe...

Page 180: ... 0 LOCK This is a read only flag that indicates the PLL state This flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset 0 Indicates that the PLL is locked 1 Indicates that the PLL is not locked UNLOCK state If the clock stops the power fails or some other factor operates to cause an unlock state to occur for control processing that depends on soft...

Page 181: ...are STOP mode and HALT mode in relation to the clock stabilization time and current consumption It is used for situations in which a low current consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released 3 Software STOP mode In this mode the overall system is stopped by stopping the clock generator oscillator and PLL synthesizer The system enters...

Page 182: ...Figure 8 1 Power Save Mode State Transition Diagram Normal operation mode Software STOP mode Set STOP mode IDLE mode Set IDLE mode Release according to RESET NMI or maskable interruptNote Set HALT mode Release according to RESET NMI or maskable interrupt HALT mode Release according to RESET NMI or maskable interruptNote Note INTPn n 0 to 4 20 to 25 However in cases such as when a digital filter us...

Page 183: ... Mode Oscillator PLL Synthesizer Clock Supply to Peripheral I O Clock Supply to CPU Normal operation HALT mode IDLE mode Oscillation with resonator Software STOP mode Normal operation HALT mode IDLE mode PLL mode External clock Software STOP mode Normal operation HALT mode IDLE mode Direct mode External clock Software STOP mode Remark Operating Stopped ...

Page 184: ... STOP mode 2 Command register PRCMD This is an 8 bit register that is used to set protection for write operations to registers that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution Writing to the first specific register power save control register PSC is only valid after first writing to the PRCMD register Because of t...

Page 185: ...dby mode release using valid edge input of NMI Note 0 Enables NMI cancellation 1 Disables NMI cancellation 4 INTM This is the enable disable setting for standby mode release using an unmasked maskable interrupt INTPn n 0 to 4 20 to 25 30 31 100 101 Note 0 Enables maskable interrupt cancellation 1 Disables maskable interrupt cancellation 1 STB Indicates the standby mode status If 1 is written to th...

Page 186: ...or the command register This coding is made on assumption that 3 and 4 above are executed by the program with consecutive store instructions If another instruction is set between 3 and 4 the above sequence may become ineffective when the interrupt is acknowledged by that instruction and a malfunction of the program may result 2 Although the data written to the PRCMD register is dummy data use the ...

Page 187: ...mode the contents of all registers internal RAM and ports are maintained in the state they were in immediately before HALT mode began Also operation continues for all on chip peripheral I O units other than ports that do not depend on CPU instruction processing Table 8 2 shows the status of each hardware unit in the HALT mode Table 8 2 Operation Status in HALT Mode Function Operation Status Clock ...

Page 188: ...f the interrupt request that is currently being serviced HALT mode is released but the newly generated interrupt request is not acknowledged The new interrupt request is held pending ii If an interrupt request including non maskable interrupt requests is generated with a higher priority than that of the interrupt request that is currently being serviced HALT mode is released and the newly generate...

Page 189: ...l registers In the IDLE mode program execution is stopped and the contents of all registers internal RAM and ports are maintained in the state they were in immediately before execution stopped The operation of on chip peripheral I O units excluding ports also is stopped Table 8 4 shows the status of each hardware unit in the IDLE mode Table 8 4 Operation Status in IDLE Mode Function Operation Stat...

Page 190: ...the system is set to IDLE mode during a maskable interrupt servicing routine operation will differ as follows i If an interrupt request is generated with a lower priority than that of the interrupt request that is currently being serviced IDLE mode is released but the newly generated interrupt request is not acknowledged The new interrupt request is held pending ii If an interrupt request includin...

Page 191: ...ion stops in software STOP mode the contents of all registers internal RAM and ports are maintained in the state they were in immediately before software STOP mode began The operation of all on chip peripheral I O units excluding ports is also stopped Table 8 6 shows the status of each hardware unit in the software STOP mode Table 8 6 Operation Status in Software STOP Mode Function Operation Statu...

Page 192: ...errupt DI Status Non maskable interrupt request Branch to handler address Maskable interrupt request Branch to handler address or execute next instruction Execute next instruction If the system is set to software STOP mode during an interrupt servicing routine operation will differ as follows i If an interrupt request is generated with a lower priority than that of the interrupt request that is cu...

Page 193: ... and processing branches to the NMI interrupt or maskable interrupt INTPn handler address Oscillation waveform X2 Set software STOP mode Oscillator is stopped CLKOUT output Internal main clock STOP state NMI input Note Time base counter s counting time Note Valid edge When specified as the rising edge The NMI pin should usually be set to an inactive level for example high level when the valid edge...

Page 194: ...signal Oscillation stabilization time secured by RESET RESET input Undefined CLKOUT output Undefined 8 6 2 Time base counter TBC The time base counter TBC is used to secure the oscillator s oscillation stabilization time when software STOP mode is released When an external clock is connected CESEL bit of CKC register 1 or a resonator is connected PLL mode and CESEL bit of CKC register 0 the TBC co...

Page 195: ...M mode 2 sawtooth wave Interrupt culling function Culling ratios 1 1 1 2 1 4 1 8 1 16 Forcible 3 phase PWM output stop function 3 phase PWM output can be forcibly stopped by inputting a signal to the external signal input pin ESOn when an anomaly occurs This function can also be used when the clock is stopped Real time output function 3 phase PWM output or rectangular wave output can be selected a...

Page 196: ...4 1 4 fXX 4 fXX 8 1 8 fXX 8 fXX 16 1 16 fXX 16 fXX 32 1 32 fXX 32 fXX 64 Interrupt request sources a Compare match interrupt request 9 types Interrupt request signal INTCM0n3 generated by match of TM0n register count value and compare register CM0n3 Interrupt request signals INTCM010 to INTCM012 INTCM0n4 and INTCM0n5 generated by match of TM0n register count value and compare registers CM010 to CM...

Page 197: ... to CM012 CM0n4 and CM0n5 registers are as follows n 0 1 a This interrupt signal is not affected by the STINTn bit of the TMC0n register that specifies occurrence of an interrupt when timer TM0n is started b The compare match interrupt output function of the CM010 to CM012 CM0n4 and CM0n5 registers does not have an interrupt culling function Therefore it is not affected by the CUL02 to CUL00 bits ...

Page 198: ...M0n5 R S R S R S R S R S R S R S R S R S DTMn2 DTMn1 DTMn0 DTRRn ALVTO ALVUB ALVVB ALVWB Output control by external input ESOn TM0n timer operation 6 Underflow Underflow Underflow TO0n0 U phase TO0n1 U phase TO0n2 V phase TO0n3 V phase TO0n4 W phase TO0n5 W phase fXX Remarks 1 TM0n Timer register CM0n0 to CM0n5 Compare registers BFCMn0 to BFCMn5 Buffer registers DTRRn Dead time timer reload regist...

Page 199: ...derflow R S R S R S R S R S R S ALVTO ALVUB ALVVB ALVWB 6 TO0n0 U phase TO0n1 U phase TO0n2 V phase TO0n3 V phase TO0n4 W phase TO0n5 W phase BFCMn4 CM0n4 BFCMn5 CM0n5 INTCM0n4 INTCM0n5 INTCM010 INTCM011 INTCM012 fXX Remarks 1 TM0n Timer register CM0n0 to CM0n5 Compare registers BFCMn0 to BFCMn5 Buffer registers DTRRn Dead time timer reload register DTMn0 to DTMn2 Dead time timers ALVTO Bit 7 of T...

Page 200: ...ted using timer control register 0n TMC0n Table 9 2 Operation Modes of Timer 0 Operation Mode Count Operation Timer Clear Source Interrupt Source BFCMn3 CM0n3 Transfer Timing BFCMn0 to BFCMn2 BFCMn4 BFCMn5 CM0n0 to CM0n2 CM0n4 CM0n5 Transfer Timing PWM mode 0 symmetric triangular wave Up down INTTM0n INTCM010 to INTCM012 INTCM0n3 to INTCM0n5 INTTM0n INTTM0n PWM mode 1 asymmetric triangular wave Up...

Page 201: ...ted signal without dead time is output to TO0n0 and TO0n1 TO0n2 and TO0n3 and TO0n4 and TO0n5 3 Dead time timer reload registers 0 1 DTRR0 DTRR1 The DTRRn register is a 12 bit register used to set the values of the three dead time timers DTMn0 to DTMn2 registers n 0 1 However a value is transferred from the DTRRn register to each dead time register independently DTRRn can be read written in 16 bit...

Page 202: ...count value of TM0n CM0n3 also has a buffer register BFCMn3 and transfers the buffer contents to CM0n3 at the next transfer timing Transfer enable or disable is controlled by the BFTE3 bit of the TMC0n register 7 Buffer registers CM00 to CM02 CM04 CM05 CM10 to CM12 CM14 CM15 BFCM00 to BFCM02 BFCM04 BFCM05 BFCM10 to BFCM12 BFCM14 BFCM15 BFCMn0 to BFCMn2 BFCMn4 and BFCMn5 are 16 bit registers that t...

Page 203: ...11 15 1 0 BFCM11 Address FFFFF5B4H After reset FFFFH 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 BFCM02 Address FFFFF576H After reset FFFFH 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 BFCM12 Address FFFFF5B6H After reset FFFFH 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 BFCM04 Address FFFFF59CH After reset FFFFH 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 BFCM14 Address FFFFF5DCH After reset FFFFH 14 13 12 2 3 4 5 6 7 8 ...

Page 204: ...ter at the following timing n 0 1 When TM0CEn bit of TMC0n register 0 Transfer at the next operation timing after writing to the BFCMn3 register When TM0CEn bit of TMC0n register 1 The value of the BFCMn3 register is transferred to the CM0n3 register upon occurrence of INTTM0n At this time transfer enable or disable is controlled by the BFTE3 bit of the timer control register TMC0n 2 Setting the B...

Page 205: ... Caution Always set this register before using the timer 7 0 PRM01 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM1 Address FFFFF5D0H After reset 00H Bit position Bit name Function 0 PRM1 Specifies the base clock fCLK of timer 0 TM0n See Figure 9 3 0 fXX 2 1 fXX Caution Set fCLK to 40 MHz or less Remark fXX Internal system clock Figure 9 3 Timer 00 and Timer 01 Clock Timer 00 Timer 01 PRM1 fCLK fXX 2 Select fXX Rem...

Page 206: ... name Function 15 TM0CEn Specifies the operation of TM0n 0 Count disabled stops after all count values are cleared 1 Count enabled Caution When TM0CEn 0 TO0n0 to TO0n5 output becomes high impedance 14 STINTn Specifies interrupt during TM0n timer start 0 Interrupt not generated at operation start 1 Interrupt generated at operation start When STINTn 1 an interrupt is generated immediately after the ...

Page 207: ...2 to CUL00 bits the interrupts occur each time at the same culling ratio as when CUL02 to CUL00 000 1 1 Specifies the count clock for TM0n PRM02 PRM01 PRM00 Count clock 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 16 1 0 1 fCLK 32 Other than above Setting prohibited 10 to 8 PRM02 to PRM00 Caution The division ratio switch timing is from when the TM0n value has become 0000H and the ...

Page 208: ...ular wave INTTM0n 1 PWM mode 1 asymmetric triangular wave INTTM0n INTCM0n3 1 PWM mode 2 sawtooth wave INTCM0n3 3 BFTEN When BFTEN 1 the values of the BFCMn0 to BFCMn2 BFCMn4 and BFCMn5 registers are transferred to the CM0n0 to CM0n2 CM0n4 and CM0n5 registers upon occurrence of the INTTM0n or INTCM0n3 interrupt When culling of the INTTM0n and INTCM0n3 interrupts is set by the CUL02 to CUL00 bits th...

Page 209: ...WM mode 2 sawtooth wave Up INTCM0n3 INTCM0n3 INTCM0n3 1 1 Setting prohibited 1 0 MOD01 MOD00 Caution Changing the value of the MOD01 and MOD00 bits during TM0n operation TM0CEn bit 1 is prohibited Remark n 0 1 Figure 9 4 Specification of INTTM0n Interrupt in PWM Mode 0 Symmetric Triangular Wave PWM Mode 1 Asymmetric Triangular Wave MOD01 MOD00 Bits of TMC0n Register 0n CM0n3 TM0n count value 0000H...

Page 210: ... 1 asymmetric triangular wave CM0n3 TM0n count value 0000H CUL02 to CUL00 INTTM0n occurrence INTCM0n3 occurrence Interrupt request INTCM0n3 occurrence INTCM0n3 occurrence INTCM0n3 occurrence INTTM0n occurrence Interrupt culling 1 1 cycle Interrupt culling 1 2 cycle INTTM0n occurrence INTTM0n occurrence 000 001 Remark n 0 1 c PWM mode 2 sawtooth wave CM0n3 TM0n count value 0000H CUL02 to CUL00 INTC...

Page 211: ...INTCM0n3 INTTM0n INTCM0n3 INTCM0n3 001 010 000 Interrupt culling 1 2 cycle Interrupt culling 1 4 cycle Interrupt culling 1 1 cycle TM0CEn bit TM0n count value CUL02 to CUL00 bits STINTn 1 INTTM0n INTTM0n INTTM0n INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTCM0n3 001 010 000 Interrupt culling 1 2 cycle Interrupt culling 1 4 cycle Interrupt culling 1 1 cyc...

Page 212: ... Cautions1 If the level is set to the ESOn pin input level TOMR register TOEDG1 bit 1 TOEDG0 bit 0 or 1 the output disabled state is not released TOSTAn bit 1 even if 1 is written to the TORSn bit while output is disabled TOSTAn bit 1 If the input level is the inactive level the output disabled state is released TOSTAn bit 0 2 If the edge is set to the ESOn pin input TOEDG1 bit 0 TOEDG0 bit 0 or 1...

Page 213: ...e internal bus during servicing of these interrupts Add one of the following processing items during the TOMRn register write routine Prior to write access to the TOMRn register disable acknowledgment of all interrupts of the CPU Following write access to the TOMRn register check that write was performed normally 1 2 7 ALVTO TOMR0 6 ALVUB 5 ALVVB 4 ALVWB 3 TOSP 2 0 1 TOEDG1 0 TOEDG0 Address FFFFF5...

Page 214: ...n pin input 0 Enables ESOn pin input 1 Disables ESOn pin input Cautions 1 The output stop status can be released by writing 1 to the TORSn bit of the TUC0n register The operation continues even if output is prohibited for all timers and counters 2 Before changing the ESOn pin input status from disabled to enabled changing the TOSP bit from 1 to 0 write 1 to the TORSn bit of the TUCn register to re...

Page 215: ... 0 asymmetric triangular waves are shown below Figure 9 7 Output Waveforms of TO000 and TO001 in PWM Mode 0 Symmetric Triangular Waves Without Dead Time TM0CED0 Bit 1 a TOMR0 register value 80H TM00 CM000 TO000 TO001 TM00 CM000 b TOMR0 register value 00H TM00 CM000 TO000 TO001 TM00 CM000 c TOMR0 register value C0H TM00 CM000 TO000 TO001 TM00 CM000 d TOMR0 register value 40H TM00 CM000 TO000 TO001 ...

Page 216: ...0 a TOMR0 register value 80H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period b TOMR0 register value 00H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period c TOMR0 register value C0H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period d TOMR0 register value 40H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period ...

Page 217: ...pulation instruction SET1 CLR1 NOT1 instructions Description Example 1 MOV 0x04 r10 2 ST B r10 SPECn r0 3 ST B r10 TOMRn r0 Remark n 0 1 To read the TOMRn register no special sequence is required Cautions 1 Prohibit interrupts between SPECn issuance 2 and the TOMRn register write that immediately follows 3 2 The data written to the SPECn register is dummy data use the same register as the general ...

Page 218: ...is high impedance 1 TO0n4 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin 3 OE11n Specifies the output status of the TO0n3 pin 0 TO0n3 output status is high impedance 1 TO0n3 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin 2 OE10n Specifies the output status of the TO0n2 pin 0 TO0n2 ...

Page 219: ...0n operation TM0CEn bit 1 INTTM0n and INTCM0n3 interrupts Continue occurring at each timing in accordance with timer and compare operations TO0n0 to TO0n5 outputs Software output has priority 3 If the TORTOn bit is changed from 1 to 0 during TM0n operation TM0CEn bit 1 the software output state is retained for the TO0n0 to TO0n5 outputs until one of the set reset condition of the flip flop for the...

Page 220: ... as during normal timer operation 1 VPORTn Specifies the TO0n2 V phase TO0n3 V phase pin output value Caution If the VPORTn bit setting value is changed when TORTOn 1 the dead time setting becomes valid for the TO0n2 TO0n3 output signal in the same way as during normal timer operation Remark n 0 1 ALVTO bit Bit 7 of the TOMRn register ALVUB bit Bit 6 of the TOMRn register ALVVB bit Bit 5 of the TO...

Page 221: ...peration enabled TORTOn 1 software output enabled to TM0CEn 1 timer operation enabled TORTOn 0 software output disabled the TO0n0 to TO0n5 pins continue to perform software output until the occurrence of the first F F set reset due to a match between TM0n and the compare register after the TORTOn bit setting changes The relationship between the settings of the TORTOn and TM0CEn bits when ALVTO 1 a...

Page 222: ...te 2 Note 1 Note 4 Notes 1 F F set by compare match during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the TORTOn bit changes from 1 to 0 while the UPORTn bit is set to 1 in the P1 period in Figure 9 9 above the F F continues to hold the TORTOn bit setting of 1 until the T1 timing However b...

Page 223: ...up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the TORTOn bit changes from 1 to 0 while the UPORTn bit is set to 0 in the P1 period in Figure 9 10 above the F F continues to hold the TORTOn bit setting of 0 until the T2 timing However because the F F is set at the T2 timing by a compare match ...

Page 224: ... F F set by compare match during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the TORTOn bit changes from 0 to 1 while the UPORTn bit is set to 0 during TM0n operation TM0CEn 1 the TO0n0 output changes from 1 to 0 because the F F is reset at the T3 timing Examples of the software output wave...

Page 225: ...tput Waveforms of TO000 and TO001 Without Dead Time TM0CED0 1 a TOMR0 register value 80H UPORT0 1 TO000 TO001 UPORT0 0 b TOMR0 register value 00H UPORT0 1 TO000 TO001 UPORT0 0 c TOMR0 register value C0H UPORT0 1 TO000 TO001 UPORT0 0 d TOMR0 register value 40H UPORT0 1 TO000 TO001 UPORT0 0 ...

Page 226: ... register value 80H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period b TOMR0 register value 00H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period c TOMR0 register value C0H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period d TOMR0 register value 40H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period ...

Page 227: ...RT0 0 UPORT0 1 TO000 TO001 Dead time period Dead time period The following table shows the output status of external pulse output in the case of TO0n0 Table 9 3 Output Status of External Pulse Output In Case of TO0n0 OE00n Bit TORTOn UPORTn Bits TM0CEn Bit TO0n0 0 0 1 0 1 High impedance 0 High impedance 0 1 Timer output 1 1 0 1 Output by UPORTn bit Remarks 1 OE00n bit Bit 0 of POERn register TORTO...

Page 228: ...r writing to the SPECn register any data can be written write processing to the TOMRn register is not performed normally Normally 0000H is read The SPECn register can be read written in 16 bit units Remark n 0 1 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 0 0 0 SPEC0 Address FFFFF580H After reset 0000H 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 0 0 0 SPEC1 ...

Page 229: ...by the TM0CEn bit of timer control register 0n TMC0n The count operation is started by setting the TM0CEn bit to 1 by software Resetting the TM0CEn bit to 0 clears TM0n and stops the count operation When the value of compare register 0n3 CM0n3 set beforehand and the value of the TM0n counter match a match interrupt INTCM0n3 is generated The count clock to TM0n can be selected from among 6 internal...

Page 230: ... 0 Symmetric triangular wave Up down INTTM0n INTCM010 to INTCM012 INTCM0n3 to INTCM0n5 INTTM0n INTTM0n 0 1 PWM mode 1 Asymmetric triangular wave Up down INTTM0n INTCM010 to INTCM012 INTCM0n3 to INTCM0n5 INTTM0n INTTM0n INTCM0n3 1 0 PWM mode 2 Sawtooth wave Up INTCM0n3 INTCM010 to INTCM012 INTCM0n3 to INTCM0n5 INTCM0n3 INTCM0n3 1 1 Setting prohibited Caution Changing the MOD01 and MOD00 bits during...

Page 231: ...e PWM cycle in BFCMn0 to BFCMn2 d Clear 0 the TM0CEDn bit of the TMC0n register to enable dead time timer operation Set TM0CEDn 1 when not using dead time e Setting 1 the TM0CEn bit of the TMC0n register starts TM0n counting and a 6 channel PWM signal is output from the TO0n0 to TO0n5 pins Cautions 1 Setting CM0n3 to 0000H is prohibited 2 Setting BFCMnx BFCMn3 is prohibited when the TM0CEn bit of ...

Page 232: ...pt Furthermore software processing is started up and calculation performed and the set reset timing of the F F for the next cycle is set to BFCMn0 to BFCMn2 The PWM cycle and the PWM duty are set in the above procedure The F F set reset conditions upon match of CM0n0 to CM0n2 are as follows Set CM0n0 to CM0n2 match detection during TM0n up count operation Reset CM0n0 to CM0n2 match detection durin...

Page 233: ...set is the high impedance state When the control mode is selected thereafter the following levels are output until TM0n is started TO0n0 TO0n2 TO0n4 When active low High level When active high Low level TO0n1 TO0n3 TO0n5 When active low Low level When active high High level The active level is set with the ALVTO bit of the TOMRn register The default is active low Caution If a value such that the p...

Page 234: ...hase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx 0000H Remarks 1 The above figure shows the timing chart when both BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 0 to 2 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 To not use dead time set the T...

Page 235: ...n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTTM0n INTCM0n3 INTTM0n c TM0n count value Interrupt request BFCMnx BFCMn3 CM0n3 CM0nx 0000H Remarks 1 The above figure shows the timing chart when both BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 4 5 4 INTCM0nx is generated on a...

Page 236: ... Triangular Wave CM0n3 TM0n count value TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output 0000H CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 CM0n3 CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 Without dead time With dead time Remark n 0 1 ...

Page 237: ...ters 0n0 to 0n2 CM0n0 to CM0n2 CM0n3 CM0n3 a a CM0nx match CM0nx match CM0nx match BFCMnx CM0n3 BFCMnx CM0n3 BFCMnx CM0n3 a BFCMnx CM0n3 a INTTM0n INTCM0n3 INTCM01x INTCM01x INTCM01x BFCM1x CM013 INTCM0n3 INTTM0n TM0n count value BFCMnx Interrupt request CM0nx 0000H t t Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 DTMnx F F Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK...

Page 238: ...nd CM0nx a in the above figure When a value greater than CM0n3 is set to BFCMn0 to BFCMn2 the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a low level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a high level This feature is effective for outputting a low level or high level width exceeding the PWM cycle in an application such as inverter control Furthermore if CM0n...

Page 239: ...tch CM0nx match CM0nx match 0000H 0000H a 0000H a INTTM0n INTTM0n INTCM0n3 INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM01x TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H CM0nx match Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case 5 INTCM01x is generated...

Page 240: ...NTCM0nx TM0n count value BFCMnx Interrupt request CM0nx 0000H CM0nx match Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a in the above figure Since TM0n CM0n0 to CM0n2 0000H match is detected during up counting by TM0n the F F is just set and does not get reset Even when the setting value is 0000H F F is changed in the cycle during which transfer is performed fr...

Page 241: ...000H b c a a 0000H 0000H Note b CM0n3 CM0n3 a a CM0nx match CM0nx match CM0nx match CM0n3 b b CM0nx match CM0nx match CM0nx match t t t t t t INTTM0n INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM01x INTCM01x INTCM01x INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n Note F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows...

Page 242: ...unt value BFCM0nx CM0nx Interrupt request 0000H 0000H b c a a 0000H 0000H b CM0n3 CM0n3 a a CM0nx match CM0nx match CM0nx match CM0n3 b b CM0nx match CM0nx match CM0nx match INTTM0n INTCM0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a and b in the above f...

Page 243: ...ter iii Set the dead time width in DTRRn Dead time width DTRRn 1 fCLK fCLK Base clock iv Set the set timing of the F F used in the PWM cycle in BFCMn0 to BFCMn2 BFCMn4 and BFCMn5 d Clear 0 the TM0CEDn bit of the TMC0n register to enable dead time timer operation Set TM0CEDn 1 when not using dead time e Setting 1 the TM0CEn bit of the TMC0n register starts TM0n counting and a 6 channel PWM signal i...

Page 244: ...above procedure The F F set reset conditions upon match of CM0n0 to CM0n2 are as follows Set CM0n0 to CM0n2 match detection during TM0n up count operation Reset CM0n0 to CM0n2 match detection during TM0n down count operation The values of DTRRn are transferred to the corresponding dead time timers DTMn0 to DTMn2 in synchronization with the set reset timing of the F F and down counting is started D...

Page 245: ...levels are output until TM0n is started TO0n0 TO0n2 TO0n4 When active low High level When active high Low level TO0n1 TO0n3 TO0n5 When active low Low level When active high High level The active level is set with the ALVTO bit of the TOMRn register The default is active low Caution If a value such that the positive phase or negative phase active width is 0 or a negative value is set in the above f...

Page 246: ...TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx 0000H Remarks 1 The above figure shows the timing chart when both BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 0 to 2 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 To...

Page 247: ...0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTTM0n INTCM0n3 INTTM0n c d e TM0n count value Interrupt request BFCMnx BFCMn3 CM0n3 CM0nx 0000H Remarks 1 The above figure shows the timing chart when both BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 4 5 4 INTCM0nx is generated...

Page 248: ...c Triangular Wave CM0n3 TM0n count value TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output 0000H CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 CM0n3 CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 Without dead time With dead time Remark n 0 1 ...

Page 249: ...CM0nx match CM0nx match CM0nx match BFCMnx CM0n3 INTTM0n INTTM0n TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H b c c c a b a c c c INTCM0n3 INTCM01x INTCM01x INTCM01x BFCM1x CM013 INTCM0n3 Remarks 1 n 0 1 2 x 0 to 2 3 c CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case 6 ...

Page 250: ...a and b in the above figure When a value greater than CM0n3 is set to BFCMn0 to BFCMn2 the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a low level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a high level This feature is effective for outputting a low level or high level width exceeding the PWM cycle in an application such as inverter control Furthermore if CM0n0 t...

Page 251: ...0n2 CM0n0 to CM0n2 t CM0n3 CM0n3 a CM0nx match INTTM0n INTTM0n TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H b b b b a b a b b b INTCM0n3 INTCM01x INTCM0n3 Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case 6 INTCM01x is generated on a match ...

Page 252: ...between TM0n and CM0nx a in the above figure When a value greater than CM0n3 is set to BFCMn0 to BFCMn2 the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a high level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a low level This feature is effective for outputting a low level or high level width exceeding the PWM cycle in an application such as inverter control The a...

Page 253: ...e phase TO0n1 TO0n3 TO0n5 b b b b b c d e Note CM0n3 CM0n3 a CM0nx match CM0n3 c d CM0nx match CM0nx match a b b b b b c d e t t t t INTTM0n INTCM0n3 INTCM01x INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n INTCM01x INTCM01x Note F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case 6 INT...

Page 254: ...CM0n4 CM0n5 CM0n3 TM0n count value BFCM0nx 0000H CM0nx Interrupt request b b b b b c d e CM0n3 CM0n3 a CM0nx match CM0n3 c d CM0nx match CM0nx match a b b b b b c d e INTTM0n INTCM0n3 INTCM0nx INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n INTCM0nx INTCM0nx Remarks 1 n 0 1 2 x 4 5 3 b CM0n3 4 INTCM0nx is generated on a match between TM0n and CM0nx a to c in the above figure ...

Page 255: ...0nx match CM0nx match INTTM0n TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H b 0000H 0000H 0000H a b a 0000H 0000H 0000H INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM01x INTCM0n3 INTTM0n CM0nx match CM0nx match Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high ...

Page 256: ...H 0000H 0000H a b a 0000H 0000H 0000H INTCM0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0n3 INTTM0n CM0nx match CM0nx match Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a and b in the above figure Since a TM0n CM0n0 to CM0n2 0000H match is detected during up counting by TM0n the F F is just set and is not reset The F F is also set upon match detection in the cy...

Page 257: ...0n3 a c CM0nx match CM0n3 d b CM0nx match CM0nx match 0000H 0000H 0000H 0000H d e t t t t t t INTTM0n INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM01x INTCM01x INTCM01x INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n CM0nx match CM0nx match 0000H 0000H 0000H 0000H b c a CM0nx match Note The F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 ...

Page 258: ...0000H CM0nx Interrupt request b c d e CM0n3 CM0n3 a c CM0nx match CM0n3 d b CM0nx match CM0nx match 0000H 0000H 0000H 0000H d e INTTM0n INTCM0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n CM0nx match CM0nx match 0000H 0000H 0000H 0000H b c a CM0nx match Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a ...

Page 259: ...3 a CM0nx match INTTM0n INTTM0n TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H 0000H 0000H 0000H 0000H a 0000H a 0000H 0000H 0000H INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM0n3 CM0nx match CM0nx match Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case 5 ...

Page 260: ...CM0nx match Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a in the above figure Since TM0n CM0n0 to CM0n2 0000H match is detected during up counting by TM0n the F F is just set and is not reset Therefore the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a high level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a low level The above...

Page 261: ...e CM0n3 CM0n3 a CM0nx match CM0n3 b c CM0nx match CM0nx match a 0000H 0000H 0000H 0000H 0000H b d t t t t INTTM0n INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n 0000H 0000H 0000H 0000H 0000H c CM0nx match CM0nx match INTCM01x INTCM01x Note F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above f...

Page 262: ...BFCM0nx 0000H CM0nx Interrupt request b c d CM0n3 CM0n3 a CM0nx match CM0n3 b c CM0nx match CM0nx match a 0000H 0000H 0000H 0000H 0000H b d INTTM0n INTCM0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n 0000H 0000H 0000H 0000H 0000H c CM0nx match CM0nx match INTCM0nx INTCM0nx Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a to c in...

Page 263: ... CM0n3 CM0n3 a CM0nx match CM0nx match INTTM0n INTTM0n TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H b b b b a b a b b b INTCM0n3 INTCM0n3 INTCM01x INTCM01x INTCM01x CM0nx match Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case 6 INTCM01x is...

Page 264: ...and CM0nx a in the above figure Since TM0n and CM0n0 to CM0n2 match is detected during count down of TM0n when BFCMn0 to BFCMn2 CM0n3 has been set the F F remains reset as is and is not set Therefore the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a low level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a high level Moreover the timing of matching with TM0n with CM...

Page 265: ...0n5 is set using the BFTEN bit c Set the initial values i Specify the interrupt culling ratio using the CUL02 to CUL00 bits of the TMC0n register ii Set the cycle width of the PWM cycle in BFCMn3 PWM cycle BFCMn3 value 1 TM0n count clock The TM0n count clock is set by the TMC0n register iii Set the dead time width in DTRRn Dead time width DTRRn 1 fCLK fCLK Base clock iv Set the set reset timing of...

Page 266: ...reset timing of the F F for the next cycle is set to BFCMn0 to BFCMn2 The PWM cycle and the PWM duty are set in the above procedure The F F set reset conditions upon match of CM0n0 to CM0n2 are as follows Set TM0n and CM0n3 match detection and rising edge of TM0CEn bit of TMC0n register Reset TM0n and CM0n0 to CM0n2 match detection The values of DTRRn are transferred to the corresponding dead time...

Page 267: ... When active low High level When active high Low level TO0n1 TO0n3 TO0n5 When active low Low level When active high High level The active level is set with the ALVTO bit of the TOMRn register The default is active low Caution If a value such that the positive phase or negative phase active width is 0 or a negative value is set in the above formula the TO0n0 to TO0n5 pins output a waveform fixed to...

Page 268: ...t request BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx 0000H INTCM0n3 INTCM01x INTCM01x INTCM0n3 Set by rising edge of TM0CEn bit Remarks 1 The above figure shows the timing chart when both BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 0 to 2 4 t Dead time DTRRn 1 fCLK fCLK Base ...

Page 269: ...unt value Interrupt request BFCMnx BFCMn3 CM0n3 CM0nx 0000H INTCM0n3 INTCM0nx INTCM0nx INTCM0n3 Remarks 1 The above figure shows the timing chart when both BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 4 5 4 INTCM0nx is generated on a match between TM0n and CM0nx a and b...

Page 270: ...put TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output 0000H CM0n2 CM0n1 CM0n0 CM0n3 CM0n2 CM0n1 CM0n0 Without dead time With dead time Remarks 1 n 0 1 2 The above figure shows an active low case Since the F F is set at the rising edge of the TM0CEn bit of the TMC0n register in the first cycle the PWM signal can be output ...

Page 271: ...a CM0nx match b b b b b a a TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H INTCM0n3 INTCM01x INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case 6 INTCM01x is generated on a match between TM01 ...

Page 272: ...hen a value greater than CM0n3 is set to BFCMn0 to BFCMn2 the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a high level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a low level Since TM0n and CM0n0 to CM0n2 match does not occur the F F is not reset This feature is effective for outputting a low level or high level width exceeding the PWM cycle in an application such...

Page 273: ... phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 a b b c d a b b c Note CM0n3 CM0n3 a c CM0nx match CM0nx match CM0n3 t t t t t INTCM0n3 INTCM01x INTCM01x INTCM0n3 INTCM0n3 INTCM0n3 Note The F F is reset upon a match with CM0nx Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case 6 INTCM01x is generated on a match bet...

Page 274: ...M0n3 TM0n count value BFCM0nx 0000H CM0nx Interrupt request a b b c d a b b c CM0n3 CM0n3 a c CM0nx match CM0nx match CM0n3 INTCM0n3 INTCM0nx INTCM0nx INTCM0n3 INTCM0n3 INTCM0n3 Remarks 1 n 0 1 2 x 4 5 3 b CM0n3 4 INTCM0nx is generated on a match between TM0n and CM0nx a and c in the above figure The timing at which the F F is reset is upon occurrence of a match with CM0n0 to CM0n2 as usual ...

Page 275: ...0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM01x INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit CM0nx match CM0nx match CM0nx match Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case 6 INTCM01x is g...

Page 276: ...e Interrupt request BFCMnx CM0nx 0000H INTCM0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0n3 INTCM0n3 CM0nx match CM0nx match CM0nx match Remarks 1 n 0 1 2 x 4 5 3 b CM0n3 4 INTCM0nx is generated on a match between TM0n and CM0nx a in the above figure If match signal INTCM0n3 for TM0n and CM0n3 and the match signal for TM0n and CM0n0 to CM0n2 conflict reset of the F F takes precedence so that the ...

Page 277: ...M0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H Note INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM01x INTCM0n3 INTCM0n3 Note Set at the rising edge of the TM0CEn bit Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case 5 W Width between CM0n3 match and CM0nx ma...

Page 278: ...M0n3 a CM0nx match CM0nx match CM0nx match CM0nx match b b b b b a a TM0n count value Interrupt request BFCMnx CM0nx 0000H INTCM0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0n3 INTCM0n3 Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a in the above figure If CM0n0 to CM0n2 0000H has been set the output waveform resulting from the TM0n count clock rate and the DTRR...

Page 279: ...0n3 CM0n3 a CM0nx match CM0nx match CM0nx match CM0nx match b b b b b a a TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H Note INTCM0n3 INTCM01x INTCM01x INTCM01x INTCM01x INTCM0n3 INTCM0n3 Note Set at the rising edge of the TM0CEn bit Remarks 1 n 0 1 2 x 0 to 2 3 The above figure shows an active high case 4 W Width ...

Page 280: ...2 2 b Operation timing of compare registers 0n4 and 0n5 CM0n4 CM0n5 CM0n3 CM0n3 CM0n3 a CM0nx match CM0nx match CM0nx match CM0nx match b b b b b a a TM0n count value Interrupt request BFCMnx CM0nx 0000H INTCM0n3 INTCM0nx INTCM0nx INTCM0nx INTCM0nx INTCM0n3 INTCM0n3 Remarks 1 n 0 1 2 x 4 5 3 INTCM0nx is generated on a match between TM0n and CM0nx a in the above figure ...

Page 281: ...ng Active Level High Are Set 1 2 a Operation timing of compare registers 0n0 to 0n2 CM0n0 to CM0n2 L CM0n3 CM0n3 CM0n3 CM0nx match CM0nx match CM0nx match a a a a a a TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F CM0nx 0000H INTCM0n3 INTCM0n3 INTCM0n3 Interrupt request Remarks 1 n 0 1 2 x 0 to 2 3 The above figure shows an active low case 4 For...

Page 282: ...egister 1 ALVTO Bit of TOMRn Register 1 PWM Driving Active Level High Are Set 2 2 b Operation timing of compare registers 0n4 and 0n5 CM0n4 CM0n5 CM0n3 CM0n3 CM0n3 CM0nx match CM0nx match CM0nx match a a a a a a TM0n count value BFCMnx CM0nx 0000H INTCM0n3 INTCM0n3 INTCM0n3 Interrupt request Remarks 1 n 0 1 2 x 4 5 3 For the timing including the dead time refer to Figure 9 35 ...

Page 283: ...ow Are Set 1 2 a Operation timing of compare registers 0n0 to 0n2 CM0n0 to CM0n2 L L H CM0n3 CM0n3 CM0n3 CM0nx match CM0nx match CM0nx match a a a a a a TM0n count value Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F CM0nx 0000H INTCM0n3 INTCM0n3 INTCM0n3 Interrupt request Remarks 1 n 0 1 2 x 0 to 2 3 The above figure shows an active high case 4 For the timing i...

Page 284: ...egister 1 ALVTO Bit of TOMRn Register 0 PWM Driving Active Level Low Are Set 2 2 b Operation timing of compare registers 0n4 and 0n5 CM0n4 CM0n5 CM0n3 CM0n3 CM0n3 CM0nx match CM0nx match CM0nx match a a a a a a TM0n count value BFCMnx CM0nx 0000H INTCM0n3 INTCM0n3 INTCM0n3 Interrupt request Remarks 1 n 0 1 2 x 4 5 3 For the timing including the dead time refer to Figure 9 35 ...

Page 285: ...iming from when the TM0CEn bit of the TMC0n register is written until the TM0n timer starts operating Figure 9 39 TM0CEn Bit Write and TM0n Timer Operation Timing Register write timing 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H fCLK TM0CEn bit write timing TM0n Caution The operation of TM0n starts 2fCLK after the register write timing Remark fCLK Base clock ...

Page 286: ... 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H CM0nx TM0n INTCM0nx INTTM0n fCLK b When count clock fCLK 4 0002H 0000H 0001H 0002H 0001H 0000H CM0nx TM0n INTCM0nx INTTM0n fCLK Cautions 1 INTCM0nx is generated at the next fCLK after detection of a TM0n and CM0nx match 2 INTTM0n is generated at the next fCLK after detection of a TM0n and 0000H m...

Page 287: ...H 0000H 0001H 0002H 0000H 0001H 0002H CM0nx TM0n INTCM0nx fCLK b When count clock fCLK 4 0002H 0000H 0001H 0002H 0000H 0001H CM0nx TM0n INTCM0nx fCLK Cautions 1 INTCM0nx is generated at the next fCLK after detection of a TM0n and CM0nx match 2 INTCM0nx is generated at the next fCLK after detection of a TM0n and CM0nx match even if the count clock is 1 2 1 8 1 16 or 1 32 Remarks 1 n 0 1 2 Where n 0...

Page 288: ...n 1 1 and count operation is started the interrupt output order differs according to the setting of the STINTn bit when counting starts Figure 9 42 Interrupt Generation Timing in PWM Mode 0 Symmetric Triangular Wave PWM Mode 1 Asymmetric Triangular Wave In Case of Interrupt Culling Ratio of 1 1 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H ...

Page 289: ...of 1 2 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 INTTM0n fCLK b When STINTn bit 1 0004H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 INTTM0n fCLK Remarks 1 n 0...

Page 290: ...en STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK b When STINTn bit 1 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK Remarks 1 n 0 1 2 fCLK Base clock ...

Page 291: ...en STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK b When STINTn bit 1 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK Remarks 1 n 0 1 2 fCLK Base clock ...

Page 292: ...H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0002H FFFFH FFFFH FFFFH 0001H 0000H 0002H 0001H 0000H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0nx TM0n DTMnx Match signal F F TO0n0 TO0n2 TO0n4 TO0n1 TO0n3 TO0n5 DTRRn fCLK CM0n3 TM0CEn bit Remarks 1 The above figure shows the timing until the compare register and the TM0n timer match and the TO0n0 to TO0n5 outputs chang...

Page 293: ...FFH FFFFH 0001H 0000H 0002H 0001H 0000H 0002H FFFFH 0001H 0000H 0006H 0007H 0008H 0009H 000AH 0000H 0001H 0002H 0003H 0004H 0005H 0006H CM0nx TM0n DTMnx Match signal F F TO0n0 TO0n2 TO0n4 TO0n1 TO0n3 TO0n5 DTRRn fCLK CM0n3 TM0CEn bit Remarks 1 The above figure shows the timing until the compare register and the TM0n timer match and the TO0n0 to TO0n5 outputs change 2 x 0 to 2 3 n 0 1 4 fCLK Base c...

Page 294: ... TM10 Compare registers 2 Capture compare registers 2 Interrupt request sources Capture compare match interrupt 2 types Compare match interrupt request 2 types Capture request signal 2 types The TM10 value can be latched using the valid edge of the INTP100 and INTP101 pins corresponding to the capture compare register as the capture trigger Count clock selectable through division by prescaler set ...

Page 295: ...e timer clear operation can be selected from among the following four conditions i Timer clear performed upon occurrence of match with CM100 set value during TM10 up count operation and timer clear performed upon occurrence of match with CM101 set value during TM10 down count operation ii Timer clear performed only by external input iii Timer clear performed upon occurrence of match between TM10 c...

Page 296: ...f timer 1 Figure 9 48 Block Diagram of Timer 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 Edge detector Output control Selector Selector Edge detector Clock controller Edge detector Edge detector Edge detector CLR1 CLR0 CM101 CM100 TM10 TM10 clear control CC101 CC100 MSEL CMD TM1UBD0 ENMD ALVT10 RLEN TM1UDF0 TM1OVF0 Clear TCLR SELCLK fCLK Internal bus Internal bus TCLR10 INTP101 TCUD10 INTP100 TIUD10 fXX 2 ...

Page 297: ...ng the same value is guaranteed even during a count operation 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 TM10 Address FFFFF5E0H After reset 0000H TM10 start and stop is controlled by the TM1CE0 bit of timer control register 10 TMC10 The TM10 operation consists of the following two modes a General purpose timer mode In the general purpose timer mode TM10 operates as a 16 bit interval timer free running ...

Page 298: ...h with CM100 set value 0 0 Cleared only by TCLR10 input 0 1 Cleared upon match with CM100 set value during up count operation 1 0 Cleared by TCLR10 input or upon match with CM100 set value during up count operation UDC mode A 1 0 1 1 Clearing not performed UDC mode B 1 1 Cleared upon match with CM100 set value during up count operation or upon match with CM101 set value during down count operation...

Page 299: ... 2 This register can be read written in 8 bit or 1 bit units Cautions 1 Always set 01H to this register before using the timers 1 and 2 Setting to other than 01H is prohibited 2 Set fCLK to 20 MHz or less 7 0 PRM02 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM2 Address FFFFF5D8H After reset 00H Bit position Bit name Function 0 PRM2 Specifies the base clock fCLK of timer 1 and timer 2 1 fCLK fXX 2 Remark fXX Inter...

Page 300: ...imer output disabled 1 Timer output enabled Caution When CMD bit 1 UDC mode timer output is not performed regardless of the setting of the TOE10 bit At this time timer output consists of the negative phase level of the level set by the ALVT10 bit 2 ALVT10 Specifies active level of timer output TO10 0 Active level is high level 1 Active level is low level Caution When CMD bit 1 UDC mode timer outpu...

Page 301: ...operation enabled 3 RLEN Enables disables transfer from CM100 to TM10 0 Transfer disabled 1 Transfer enabled Cautions 1 When RLEN 1 the value set to CM100 is transferred to TM10 upon occurrence of a TM10 underflow 2 The RLEN bit is valid only in UDC mode A TUM0 register s CMD bit 1 MSEL bit 0 In the general purpose timer mode CMD bit 0 and in UDC mode B CMD bit 1 MSEL bit 1 a transfer operation is...

Page 302: ...lid in general purpose timer mode CMD bit of TUM0 register 0 3 The CLR1 and CLR0 bit settings are invalid in UDC mode B MSEL bit of TUM0 register 1 4 When clearing by TCLR10 has been enabled by bits CLR1 and CLR0 clearing is performed whether the value of the TM1CE0 bit is 1 or 0 4 Capture compare control register 0 CCR0 The CCR0 register specifies the operation mode of the capture compare registe...

Page 303: ...imer 1 is not used and the TCUD10 INTP100 and TCLR10 INTP101 pins are used as INTP100 and INTP101 1 2 7 TESUD01 SESA10 6 TESUD00 5 CESUD01 4 CESUD00 3 IES1011 2 IES1010 1 IES1001 0 IES1000 Address FFFFF5EDH After reset 00H TIUD10 TCUD10 TCLR10 INTP101 INTP100 Bit position Bit name Function Specifies valid edge of pins TIUD10 TCUD10 TESUD01 TESUD00 Valid edge 0 0 Falling edge 0 1 Rising edge 1 0 Se...

Page 304: ...sing edge of TCLR10 10 TM10 cleared status held while TCLR10 input is low level 11 TM10 cleared status held while TCLR10 input is high level Caution The set values of the CESUD01 and CESUD00 bits are valid only in UDC mode A Specifies valid edge of the pin INTP101 INTP100 selected by the CSL0 bit of the CSL10 register IES1011 IES1010 Valid edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibit...

Page 305: ...ck of the TM10 is used or during external clock TIUD10 input CMD 0 CMD 1 PRM12 PRM11 PRM10 Count clock Count clock UDC mode 0 0 0 Setting prohibited 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 Setting prohibited 1 0 0 fCLK 16 Mode 1 1 0 1 fCLK 32 Mode 2 1 1 0 fCLK 64 Mode 3 1 1 1 fCLK 128 TIUD10 Mode 4 2 to 0 PRM12 to PRM10 Remark fCLK Base clock a In general purpose timer mode CMD bit of TUM0 register...

Page 306: ... of a read access to the STATUS0 register from the CPU 0 TM1UBD0 Indicates the operating status of TM10 up down count 0 TM10 up count in progress 1 TM10 down count in progress Caution The state of the TM1UBD0 bit differs according to the mode as follows The TM1UBD0 bit is fixed to 0 in general purpose timer mode CMD bit of TUM0 register 0 The TM1UBD0 bit indicates the TM10 up down count status in ...

Page 307: ...ibited to overwrite the value of the CM100 register 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CM100 Address FFFFF5E2H After reset 0000H 10 Compare register 101 CM101 CM101 is a 16 bit register that always compares its value with the value of TM10 When the value of the compare register matches the value of TM10 an interrupt signal is generated The interrupt generation timing in the various modes is des...

Page 308: ...tual value If CC100 must be read twice be sure to read another register between the first and the second read operation 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CC100 Address FFFFF5E6H After reset 0000H a When set as a capture register When CC100 is set as a capture register the valid edge of the corresponding external interrupt signal INTP100 is detected as the capture trigger TM10 latches the count...

Page 309: ...r register between the first and the second read operation 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CC101 Address FFFFF5E8H After reset 0000H a When set as a capture register When CC101 is set as a capture register the valid edge of either corresponding external interrupt signal INTP100 or INTP101 is selected with the selector and the valid edge of the selected external interrupt signal is detected a...

Page 310: ... clock and resumes counting The free running cycle can be calculated by the following formula Free running cycle 65 536 TM10 count clock rate c Compare function TM10 connects two compare register CM100 CM101 channels and two capture compare register CC100 CC101 channels When the TM10 count value and the set value of one of the compare registers match a match interrupt INTCM100 INTCM101 INTCC100Not...

Page 311: ...put pulse width externally If a single edge is selected as the capture trigger the input pulse cycle can be measured e PWM output operation PWM output operation is performed from the TO10 pin by setting TM10 to the general purpose timer mode CMD bit 0 using timer unit mode register 0 TUM0 The resolution is 16 bits and the count clock can be selected from among seven internal clocks fCLK 2 fCLK 4 f...

Page 312: ...ch The CM101 register is a compare register used to set the PWM output duty Set the duty required for the PWM cycle Figure 9 50 PWM Signal Output Example When ALVT10 Bit 0 Is Set CM100 set value CM101 set value TM10 TO10 INTCM100 INTCM101 Cautions 1 Changing the values of the CM100 and CM101 registers is prohibited during TM10 operation TM1CE0 bit of TMC10 register 1 2 Changing the value of the AL...

Page 313: ...h edges of TIUD10 input and both edges of TCUD10 input The UDC mode is further divided into two modes according to the TM10 clear conditions a count operation is performed only with TIUD10 and TCUD10 input in both modes UDC mode A TUM0 register s CMD bit 1 MSEL bit 0 The TM10 clear source can be selected as only external clear input TCLR10 a match signal between the TM10 count value and the CM100 ...

Page 314: ...re performed based on the level of the TCUD10 pin upon detection of the valid edge of the TIUD10 pin TM10 down count operation when TCUD10 pin high level TM10 up count operation when TCUD10 pin low level Figure 9 51 Mode 1 When Rising Edge Is Specified as Valid Edge of TIUD10 Pin TIUD10 TCUD10 TM10 0006H 0007H Down count Up count 0005H 0004H 0005H 0006H 0007H Figure 9 52 Mode 1 When Rising Edge Is...

Page 315: ...M10 0007H 0008H Up count Hold value Down count 0007H 0006H 0005H iii Mode 3 PRM10 register s PRM12 1 PRM11 1 PRM10 0 In mode 3 when two signals 90 degrees out of phase are input to the TIUD10 and TCUD10 pins the level of the TCUD10 pin is sampled at the input of the valid edge of the TIUD10 pin Refer to Figure 9 54 If the TCUD10 pin level sampled at the valid edge input to the TIUD10 pin is low TM...

Page 316: ...ng to the timing shown in Figure 9 56 In mode 4 counting is executed at both the rising and falling edges of the two signals input to the TIUD10 and TCUD10 pins Therefore TM10 counts four times per cycle of an input signal 4 count Figure 9 56 Mode 4 TIUD10 TCUD10 TM10 0004H 0003H 0006H 0005H 0008H 0007H 000AH 0009H 0008H 0009H 0006H 0007H 0005H Up count Down count Cautions 1 When mode 4 is specifi...

Page 317: ...sfer operation can be combined with the interval operation Figure 9 57 Example of TM10 Operation When Interval Operation and Transfer Operation Are Combined TM10 and CM100 match timer clear TM10 underflow CM100 data transfer TM10 count value CM100 set value Up count Down count 0000H iii Compare function TM10 connects two compare register CM100 CM101 channels and two capture compare register CC100 ...

Page 318: ... UDC Mode CM100 set value CM101 set value TM10 count value Clear TM10 not cleared if count clock counts down following match Clear TM10 not cleared if count clock counts up following match ii Compare function TM10 connects two compare register CM100 CM101 channels and two capture compare register CC100 CC101 channels When the TM10 count value and the set value of one of the compare registers match...

Page 319: ...atch with the CM100 register In case of TM10 down count operation TM10 count value is cleared upon match with the CM101 register Figure 9 59 Clear Operation After Match of CM100 Register Set Value and TM10 Count Value a Up count Up count Count clock Rising edge set as valid edge CM100 register FFFEH TM10 cleared TM10 FFFFH 0000H 0001H FFFFH Up count Up count b Up count Down count Count clock Risin...

Page 320: ...1 register 00FFH TM10 not cleared TM10 00FEH 00FFH 0100H 00FEH Down count Up count 2 Transfer operation If TM10 becomes 0000H during down counting when the RLEN bit of the TMC10 register is 1 in UDC mode A the set value of the CM100 register is transferred to TM10 at the next count clock The transfer operation is not performed during up counting Figure 9 61 Internal Operation During Transfer Opera...

Page 321: ... Timer Mode and Count Clock Set to fCLK 2 Count clock fCLK CM101 0007H TM10 Internal match signal INTCM101 0008H 000BH 0009H 0009H 000AH Remark fCLK Base clock An interrupt signal such as the one illustrated in Figure 9 62 is output at the next count clock following a match of the TM10 count value and the set value of the corresponding compare register 4 TM1UBD0 flag bit 0 of STATUS0 register oper...

Page 322: ...d 9 3 2 Function overview timer 2 16 bit timer counter TM20 TM21 2 channels Bit length Timer 2 registers TM20 TM21 16 bits During cascade operation 32 bits higher 16 bits TM21 lower 16 bits TM20 Capture compare register In 16 bit mode 6 In 32 bit mode 4 capture mode only Count clock division selectable by prescaler set the frequency of the count clock to 10 MHz or less Base clock fCLK 1 type set f...

Page 323: ...ut Note 2 Timer counter clear operation can be performed using the TCLR2 pin input signal Up down count control Notes 3 5 with external pin input Note 2 Up down count operation in the compare mode can be controlled using the TCLR2 pin input signal Output delay operation A clock synchronized output delay can be added to the output signal of the TO21 to TO24 pins This is effective as an EMI counterm...

Page 324: ...Read INTCC23 INTP23 INTP22 Note 2 CVPE20 Read INTCC22 INTP22 INTP23 Note 2 Timer 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 CVPE10 Read INTCC21 INTP21 INTP24 Note 2 Notes 1 Cascade operation with TM20 and TM21 is possible 2 Cascade operation using the CVSEn0 and CVPEn0 registers is possible n 1 to 4 Remark fXX Internal system clock The following shows the capture compare operation sources ...

Page 325: ...OTMEn1 OTMEn0 10 Toggle Mode 3 OTMEn1 OTMEn0 11 Trigger Compare match of sub channel n Compare match of sub channel n TM20 0 Compare match of sub channel n TM21 0 Compare match of sub channel n Compare match of sub channel n 1 Output level Active output Inactive output Active output Inactive output Active output Inactive output Active output Inactive output Remarks 1 n 1 to 4 2 OTMEn1 OTMEn0 Bits ...

Page 326: ...1 RELOAD2A RELOAD2B ED2 Subchannel 3 CVSE30 16 bit CVPE30 16 bit S T RA RB RN Output circuit 4 CVSE00 16 bit TM20 16 bit INTCC20 INTCC21 INTCC22 INTCC23 INTCC24 INTCC25 INTTM20 TO21 TO22 TO23 TO24 INTTM21 CVSE50 16 bit TM21 16 bit TINE5 edge selection TINE4 edge selection TINE3 edge selection TINE2 edge selection TINE1 edge selection TINE0 edge selection Input filter Input filter Input filter Inpu...

Page 327: ...l input subchannel 0 5 RA TM20 zero count signal input reset signal of output circuit RB TM21 zero count signal input reset signal of output circuit RELOAD2A TM20 zero count signal input generated when TM20 0000H RELOAD2B TM21 zero count signal input generated when TM21 0000H RN Subchannel x interrupt signal input reset signal of output circuit S T Subchannel x interrupt signal input set signal of...

Page 328: ...En0 register is the subchannel n 16 bit main capture compare register In the capture register mode this register captures the value of TM21 when the BFEEn bit of the CMSEm0 register 0 m 12 34 When the BFEEn bit 1 this register holds the value of TM20 or TM21 In compare register mode a match between this register and TM2x is detected TM2x timer counter selected by TB1En and TB0En bits If the captur...

Page 329: ...BFEEn bit 1 a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset TM2x timer counter selected by TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CVSE10 Address FFFFF650H After reset 0000H 14 13 12 2...

Page 330: ...p register 0 STOPTE0 The STOPTE0 register is used to stop the operation clock input to timer 2 This register can be read written in 16 bit units When the higher 8 bits of the STOPTE0 register are used as the STOPTE0H register and the lower 8 bits are used as the STOPTE0L register the STOPTE0H register can be read written in 8 bit or 1 bit units and the STOPTE0L register is read only in 8 bit units...

Page 331: ... Function Specifies the valid edge of the TM2n internal count clock TCOUNTEn signal TESnE1 TESnE0 Valid edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Note 11 10 9 8 TESnE1 TESnE0 Specifies the valid edge of the TM2n external clear input TCLR2 CESE1 CESE0 Valid edge 0 0 Falling edge 0 1 Rising edge 1 0 Through input no clear operation 1 1 Both rising...

Page 332: ...he SESE0H register and the lower 8 bits are used as the SESE0L register they can be read written in 8 bit or 1 bit units 14 0 13 0 12 0 2 IESE10 3 IESE11 4 IESE20 5 IESE21 6 IESE30 7 IESE31 8 IESE40 9 IESE41 10 IESE50 11 IESE51 15 0 1 IESE01 0 IESE00 SESE0 Address FFFFF644H After reset 0000H Bit position Bit name Function Specifies the valid edge of external capture signal input TINEn for subchann...

Page 333: ... the external clock TI2 is input 3 The ECREn bit and the ECEEn bit cannot be set to 1 4 If the ECEEn bit is set to 1 and the ECREn bit is set to 0 a down count operation cannot be performed 5 When UDSEn1 UDSEn0 01 and OSTEn 1 the counter does not count up when the counter value is 0 Therefore when the counter value is 0 set OSTEn 0 and after the value of the counter ceases to be 0 set OSTEn 1 Also...

Page 334: ...s selected as the count of TM21 When CASE1 1 TCOUNTE0 and the TM20 overflow signal are selected as the count of TM21 14 6 CLREn Specifies software clear for TM2n 0 TM2n operation continued 1 TM2n count value cleared 0 Caution Do not perform the software clear and hardware clear operations simultaneously 13 5 CEEn Specifies TM2n count operation enable disable 0 Count operation stopped 1 Count opera...

Page 335: ...1 TM2n count is stopped when the count value is 0 TM2n counts up except when the UDSEn1 UDSEn0 bits 10 The count direction when the UDSEn1 and UDSEn0 bits 10 is determined by the value of ECLR Specifies TM2n up down count UDSEn1 UDSEn0 Count 0 0 Perform only up count Clear TM2n with compare match signal 0 1 Count up after TM2n has become 0 and count down after a compare match occurs for subchannel...

Page 336: ...n output 0 Active level is high level 1 Active level is low level Specifies toggle mode OTMEn1 OTMEn0 Toggle mode 0 0 Toggle mode 0 Reverse output level of TO2n output every time a subchannel n compare match occurs 0 1 Toggle mode 1 Upon subchannel n compare match set TO2n output to active level and when TM20 is 0 set TO2n output to inactive level 1 0 Toggle mode 2 Upon subchannel n compare match ...

Page 337: ...tive After that PWM output from the TO2n pin is performed upon a compare match at subchannel n However the first PWM output change timing varies as follows depending on the internal output level and the SWFEn bit clear timing Figure 9 65 PWM Output Change Timing i Example 1 TO2n output ALVEn bit 1 PWM output change timing SWFEn bit Internal output level ii Example 2 TO2n output ALVEn bit 1 PWM out...

Page 338: ...re compare register 0 ED1 and ED2 signal inputs ignored nothing is done even if these signals are input 1 Operation caused by ED1 and ED2 signal inputs enabled 11 3 LNKEn Specifies capture event signal input from edge selection to ED1 or ED2 0 In capture register mode ED1 signal input selected In compare register mode LNKEn bit has no influence 1 In capture register mode ED2 signal input selected ...

Page 339: ...d by TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 Remarks 1 The operations in the capture register mode and compare register mode when the subchannel n sub capture compare register CVSEn0 is not used as a buffer are shown below In capture register mode The CPU can read both the master register CVPEn0 and slave register CVSEn0 ...

Page 340: ... register mode the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes 0 TM2x timer counter selected by bits TB1En TB0En 10 2 CCSEn Selects capture compare register operation mode 0 Capture register mode 1 Compare register mode Sets subchannel n timer counter TB1En TB0En Subchannel n timer counter 0 0 Subchannel n not used 0 1 TM20 set to subchannel ...

Page 341: ...TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 Remarks 1 The operations in the capture register mode and compare register mode when the subchannel n sub capture compare register CVSEn0 is not used as a buffer are shown below In capture register mode The CPU can read both the master register CVPEn0 and slave register CVSEn0 The n...

Page 342: ...e register mode the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes 0 TM2x timer counter selected by bits TB1En TB0En 10 2 CCSEn Selects capture compare register operation mode 0 Capture register mode 1 Compare register mode Sets subchannel n timer counter TB1En TB0En Subchannel n timer counter 0 0 Subchannel n not used 0 1 TM20 set to subchannel...

Page 343: ... 13 0 12 0 2 ECFE0 3 OVFE0 4 0 5 0 6 0 7 0 8 UDFE1 9 RSFE1 10 ECFE1 11 OVFE1 15 0 1 RSFE0 0 UDFE0 TBSTATE0 Address FFFFF664H After reset 0101H Bit position Bit name Function 11 3 OVFEn Indicates TM2n overflow status 0 No overflow 1 Overflow Caution If write access to the TBSTATE0 register is performed when an overflow has not been detected the OVFEn bit is cleared 0 10 2 ECFEn Indicates the ECLR s...

Page 344: ...occurred In compare register mode No compare match has occurred 1 In capture register mode At least one capture operation has occurred In compare register mode At least one compare match has occurred Caution The CEFEn bit can be cleared 0 by performing a write access to the CCSTATE0 register when no capture operation or compare match has occurred When bit manipulation is performed on the CEFE1 CEF...

Page 345: ...0 5 ODLE21 6 ODLE22 7 0 8 ODLE30 9 ODLE31 10 ODLE32 11 0 15 0 1 ODLE11 0 ODLE10 ODELE0 Address FFFFF668H After reset 0000H Bit position Bit name Function Specifies output delay operation ODLEn2 ODLEn1 ODLEn0 Set output delay operation 0 0 0 Output delay operation not performed 0 0 1 Sets output delay of 1 system clock 0 1 0 Sets output delay of 2 system clocks 0 1 1 Sets output delay of 3 system c...

Page 346: ... 0 11 0 15 0 1 SEVE1 0 SEVE0 CSCE0 Address FFFFF66AH After reset 0000H Bit position Bit name Function 5 to 0 SEVEn Specifies capture operation by software in capture register mode 0 Normal operation continued 1 Capture operation performed Cautions 1 The SEVEn bit ignores the settings of the EEVEn and the LNKEn bits of the CMSEm0 register 2 The SEVEn bit is automatically cleared 0 at the end of an ...

Page 347: ...e TESnE1 and TESnE0 bits and the CESE1 and CESE0 bits of the CSE0 register and the IESEx1 and IESEx0 bits of the SESE0 register are shown Remarks 1 fCLK Base clock 2 CT TM2n count signal input in the 16 bit mode ECLR External control signal input from TCLR2 input ED1 ED2 Capture event signal input from edge selector MUXTB0 TM20 multiplex signal TCOUNTEn Timer 2 count enable signal input TINEx Time...

Page 348: ...n Bit 0 ECREn Bit 0 CLREn Bit 0 CASE1 Bit 0 fCLK FFFDH Stop FFFEH FFFFH 0000H 1234H 1235H 0000H Stop CT CNT RNote 2 INTTM2n output CNT 0 OSTEn bitNote 1 CEEn bitNote 1 Notes 1 Bits OSTE CEE of TCRE0 register 2 Can control TM20 TM21 clear by subchannel 0 5 compare match or count direction Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CT TM2n count signal input in 16 bit mode R Compare matc...

Page 349: ...SEn0 Bits 00B OSTEn Bit 0 CEEn Bit 1 CASE1 Bit 0 fCLK ECREn bitNote CLREn bitNote ECLR CNT CT ECEEn bitNote 1234H 1235H 0000H 0001H 0000H Note Bits ECEEn ECREn CLREn of TCRE0 register Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CT TM2n count signal input in 16 bit mode ECLR External control signal input from TCLR2 pin input 3 n 0 1 ...

Page 350: ...CNT 0 CT UDSEn1 UDSEn0 bitsNote 1 FFFFH 0000H 0001H Don t care 01B 10B 0002H 0001H 0000H 0001H 0002H 0003H 0002H FFFEH Notes 1 UDSEn1 UDSEn0 bits of TCRE0 register 2 Can control TM20 TM21 clear by subchannel 0 5 compare match or count direction Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CT TM2n count signal input in 16 bit mode ECLR External control signal input from TCLR2 pin input R ...

Page 351: ...K CNT TB0 CNT TB1 CTC CASCNote TB1 FFFBH FFFCH FFFDH FFFEH FFFFH 0000H 0001H 0002H 0003H 0004H 1234H 1235H Note If in the 32 bit mode CASC CNT MAX for TM20 is input to TM21 and the CTC rising edge is detected TM21 performs a count operation Remarks 1 fCLK Base clock 2 CASC TM21 count signal input in 32 bit mode CNT Count value of timer 2 CTC TM21 count signal input in 32 bit mode TB0 Count value o...

Page 352: ...alue of TM21 is output to subchannels 1 to 4 at the rising edge of MUXTB1 Figure 9 71 shows the block diagram of the timer 2 multiplex count generator and Figure 9 72 shows the multiplex count timing Figure 9 71 Block Diagram of Timer 2 Multiplex Count Generator MUXTB0 to subchannel m capture compare register MUXTB1 to subchannel m capture compare register MUXCNT to subchannel m capture compare re...

Page 353: ...TB0 TB1 TB0 TB1 TB0 TB1 0001H FFFEH 1234H FFFFH FFFFH FFFFH 1234H 1234H 0000H 1234H 1235H 0000H 1235H 0000H 0001H 0001H 0001H 1235H 1235H 1235H Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 MUXTB0 MUXTB1 Multiplex signal of TM20 TM21 MUXCNT Count value to subchannel m m 1 to 4 TB0 Count value of TM20 TB1 Count value of TM21 Figures 9 73 to 9 78 show the operation of the capture compare re...

Page 354: ...TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 1 5 6 2 3 4 7 8 5 9 10 6 11 7 8 9 10 12 13 14 Note 2 Note 2 Undefined Undefined 2 4 13 11 Notes 1 Bits TB0Ey TB1Ey of CMSEx register 2 If an event occurs at this timing it is ignored Remarks 1 fCLK Base clock 2 CAPTURE_P Capture trigger signal of main capture register CAPTURE_S Capture trigger signal of sub capture register ED1 ED2 Capture event ...

Page 355: ...t the start of an operation and read the CVPEm0 register Also read the CVPEm0 register after performing a capture at least once 2 A write operation to the CVPEn0 register is not performed at these signal inputs because the CVSEm0 register operates as a buffer 3 After this timing a write operation from the CVSEm0 register to the CVPEm0 register is enabled Remarks 1 fCLK Base clock 2 BUFFER Timing o...

Page 356: ... 1235H 0000H 0001H 0001H 0001H 1235H 1235H 1235H Note 2 Note 3 Notes 1 TM21 performs a count operation when in the 32 bit mode CASC CNT MAX for TM20 is input to TM21 and the rising edge of CTC is detected 2 If an event occurs during this timing it is ignored 3 CPU read access is not performed at this timing wait status Remarks 1 fCLK Base clock 2 CAPTURE_P Capture trigger signal of main capture re...

Page 357: ...TB0 TB1 5 1 6 2 3 4 7 8 5 9 10 6 11 7 8 9 10 12 13 14 Cleared by timer Set by software Event detection by EEVEy bit prohibited L Notes 1 EEVEy bit of CMSEx0 register 2 SEVEy bit of CSCE0 register Remarks 1 fCLK Base clock 2 BUFFER Timing of write operation from CVSEm0 register to CVPEm0 register CAPTURE_P Capture trigger signal of main capture register CAPTURE_S Capture trigger signal of sub captu...

Page 358: ... 8 8 Note 3 Note 3 Note 3 Note 3 Note 2 Notes 1 TB1Ey TB0Ey bits of CMSEx0 register 2 No interrupt is generated due to a compare match with counter differing from that set by the TB1Ey and TB0Ey bits 3 INTCC2m is generated to match the cycle from the rising edge to the falling edge of MUXTB0 Remarks 1 fCLK Base clock 2 MUXCNT Count value to subchannel m MUXTB0 MUXTB1 Multiplex signal of TM20 TM21 ...

Page 359: ... TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 5 1 6 2 3 4 7 8 5 9 10 6 11 7 0 1 2 12 13 14 4 4 7 1 7 1 Note LNKEy bit of CMSEx0 register Remarks 1 fCLK Base clock 2 MUXCNT Count value to subchannel m MUXTB0 MUXTB1 Multiplex signal of TM20 TM21 RELOAD1 Compare match signal RELOAD2A Zero count signal input of TM20 occurs when TM20 0000H RELOAD_PRIMARY Timing of write operation from CVSEm0 register to CVPEm0 regi...

Page 360: ...er s CCSEy Bit 0 EEVEy Bit 1 and CSCE0 Register s SEVEy Bit 0 fCLK ED1 ED2 CAPTURE_S READ_ENABLE_S CVSEy0 register CNT LNKEyNote 1 1 2 3 4 5 6 7 8 9 10 0 Note 2 Note 2 Undefined 2 6 9 Notes 1 LNKEy bit of CMSE050 register 2 If an event occurs at this timing it is ignored Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CAPTURE_S Capture trigger signal of sub capture register ED1 ED2 Capture ...

Page 361: ...r MATCH RNote 1 INTCC20 INTCC25 output CNT CPU write C C 1 2 2 3 4 4 5 6 7 8 8 9 10 0 Note 2 Note 3 Note 2 Note 2 Note 3 Note 3 Notes 1 Can control TM20 TM21 clear by subchannel 0 5 compare match and count direction 2 When the MATCH signal occurs the same waveform as the MATCH signal is generated 3 The pulse width is always 1 clock Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 MATCH CVSEy...

Page 362: ...CLK RA RB RN TO2n timer output ALVEn bit 0Note 2 TO2n timer output ALVEn bit 1Note 2 OTMEn1 OTMEn0 bitsNote 1 S T 00B 01B Notes 1 OTMEn1 OTMEn0 bits of OCTLE0 register 2 ALVEn bit of OCTLE0 register Remarks 1 fCLK Base clock 2 RA Zero count signal input of TM20 output circuit reset signal RB Zero count signal input of TM21 output circuit reset signal RN Interrupt signal input of subchannel n outpu...

Page 363: ... OCTLE0 register Remarks 1 fCLK Base clock 2 RA Zero count signal input of TM20 output circuit reset signal RB Zero count signal input of TM21 output circuit reset signal RN Interrupt signal input of subchannel n output circuit reset signal S T Interrupt signal input of subchannel n output circuit set signal 3 n 1 to 4 Figure 9 83 Signal Output Operation During Software Control When OCTLE0 Registe...

Page 364: ...ure 9 84 Signal Output Operation During Delay Output Operation When OCTLE0 Register s OTMEn1 OTMEn0 Bits 0 ALVEn 0 SWFEn Bit 0 fCLK TO2n timer output ODELEn2 to ODELEn0 bitsNote S T 5 2 Note ODELEn2 to ODELEn0 bits of OCTLE0 register Remarks 1 fCLK Base clock 2 n 1 to 4 ...

Page 365: ...nel 1 the CVSEn0 register The TO2n pin outputs a high level or low level according to the TO2n internal status and the value of the OCTLE0 ALVEn bit Figure 9 85 During Normal Output Operation When OTMEn1 OTMEn0 Bits 01 in OCTLE0 Register ODLEn2 to ODLEn0 Bits 000 in ODELE0 Register fCLK Match signal with CVSEn0 register TO2n internal TO2n output ALVEn bit 0 TO2n output ALVEn bit 1 TM20 CVSE00 regi...

Page 366: ...r if the SWFEn bit is changed from 1 to 0 forcibly activate the TO2n output once If the SWFEn bit is changed from 0 to 1 forcibly fix the TO2n output to the inactive status If the compare match signal of subchannel n is output immediately after the SWFEn bit has been changed from 1 to 0 the period from when the SWFEn bit changes from 1 to 0 until the compare match signal is output is added to the ...

Page 367: ...ged from 0 to 1 the TO2n output is forcibly fixed to inactive If this operation is generated while active level is output the active level output period is shorter refer to Figure 9 87 Figure 9 87 When Normal Output Operation Starts Ends When OTMEn1 OTMEn0 Bits 01 in OCTLE0 Register ODLEn2 to ODLEn0 Bits 000 in ODELD0 Register fCLK Match signal with CVSE0 register TO2n internal TO2n output ALVEn b...

Page 368: ... fXX Selected fXX 2 Selected 1 2 fXX 2 fXX 4 1 4 fXX 4 fXX 8 1 8 fXX 8 fXX 16 1 16 fXX 16 fXX 32 1 32 fXX 32 fXX 64 1 64 fXX 64 fXX 128 1 128 fXX 128 fXX 256 1 256 fXX 256 fXX 512 Interrupt request sources Capture compare match interrupt requests 2 sources In case of capture register INTCC3n generated by INTP3n input In case of compare register INTCC3n generated by CC3n match signal Overflow inter...

Page 369: ...30 TO3 S Timer 3 fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 CC31 Read write INTC31 INTP31 TO3 R Notes 1 When fXX is selected as the base clock fCLK of TM3 2 When fXX 2 is selected as the base clock fCLK of TM3 Remark fXX Internal system clock S R Set Reset Figure 9 88 shows the block diagram of timer 3 Figure 9 88 Block Diagram o...

Page 370: ...ounts the valid edges of the external clock input TI3 synchronized with the internal count clock The valid edge is specified by valid edge selection register SESC Caution When using the INTP30 TI3 and TCLR3 pins as TI3 andTCLR3 either mask the interrupt signal to INTP30 or set CC3n in compare mode n 0 or 1 b Selection of the internal count clock TM3 operates as a free running timer When an interna...

Page 371: ...isters to capture registers CMS1 and CMS0 of TMC31 0 When these registers are set to capture registers the valid edges of the corresponding external interrupt signals INTP30 and INTP31 are detected as capture triggers The timer TM3 is synchronized with the capture trigger and the value of TM3 is latched in the CC30 and CC31 registers capture operation The valid edge of the INTP30 pin is specified ...

Page 372: ...ized with the generation of a match signal The interrupt selection source differs according to the function of the selected register Cautions 1 To write to capture compare registers 30 and 31 CC30 CC31 always set the TM3CAE bit to 1 first When the TM3CAE bit is 0 even if writing to registers CC30 and CC31 the data that is written will be invalid because the reset is asynchronous 2 Perform a write ...

Page 373: ...imer 3 TM3 This register can be read written in 8 bit or 1 bit units Cautions 1 Always set this register before using the timer 2 Set fCLK to 32 MHz or less 7 0 PRM03 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM3 Address FFFFF690H After reset 00H Bit position Bit name Function 0 PRM3 Specifies the base clock fCLK of timer 3 TM3 0 fXX 2 when fXX 32 MHz 1 fXX when fXX 32 MHz Remark fXX Internal system clock ...

Page 374: ... Bit position Bit name Function 7 TM3OVF Flag that indicates TM3 overflow 0 No overflow 1 Overflow The TM3OVF bit becomes 1 when TM3 changes from FFFFH to 0000H An overflow interrupt request INTTM3 is generated at the same time However if CC30 is set to the compare mode CMS0 bit of the TMC31 register 1 and match clear during comparison of TM3 and CC30 is enabled CCLR bit of TMC31 register 1 and TM...

Page 375: ...E Controls the operation of TM3 0 Count disabled timer stopped at 0000H and does not operate 1 Count operation performed Caution If TM3CE 0 the external pulse output TO3 becomes inactive level The active level of TO3 output is set with the ALV bit of the TMC31 register 0 TM3CAE Controls the internal count clock 0 Entire TM3 unit asynchronously reset Stop base clock supply to TM3 unit 1 Base clock ...

Page 376: ...overwritten during timer operation the operation is not guaranteed 2 If the ENT1 bit and the ALV bit are changed simultaneously a glitch spike shaped noise may be generated in the TO3 pin output Either design a circuit that will not malfunction even if a glitch is generated or make sure that the ENT1 bit and the ALV bit do not change at the same time 3 TO3 output remains unchanged by external inte...

Page 377: ... until a match signal is generated Caution If either CC30 or CC31 is specified as a capture register the ENT1 bit must be set to 0 5 ALV Specifies active level of external pulse output TO3 0 Active level is low level 1 Active level is high level Caution The initial value of the ALV bit is 1 4 ETI Switches count clock between external clock and internal clock 0 Specifies input clock internal The co...

Page 378: ...egister during timer operation If they are to be changed they must be changed after setting the TM3CE bit of the TMC30 register to 0 If the SESC register is overwritten during timer operation the operation is not guaranteed 7 TES31 SESC 6 TES30 5 CES31 4 CES30 3 IES311 2 IES310 1 IES301 0 IES300 Address FFFFF689H After reset 00H TI3 TCLR3 INTP31 INTP30 Bit position Bit name Function 7 6 TES31 TES3...

Page 379: ...h register and the status of the TO3 P27 and INTP31 pins Table 9 14 Relationship Between Setting of Each Register and Status of TO3 P27 and INTP31 Pins TO3 P27 INTP31 PMC27 Bit PFC27 Bit PM27 Bit TO3SP Bit Operation Mode of Pin Output Buffer Status Pin Function 0 0 Output port mode On Output port 0 1 Input port mode Off Input port 1 0 INTP31 input mode Off INTP31 1 1 0 On TO3 1 1 1 TO3 output mode...

Page 380: ... TO3 can be set or reset Also a capture operation that holds the TM3 count value in the CC30 or CC31 register is performed synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger The capture value is held until the next capture trigger is generated Caution When using the INTP30 TI3 and TCLR3 pins as TI3 and TCLR3 either mask the inter...

Page 381: ...0000H Also the overflow interrupt INTTM3 is not generated When the TM3 register is changed from FFFFH to 0000H because the TM3CE bit changes from 1 to 0 the TM3 register is considered to be cleared but the TM3OVF bit is not set 1 and no INTTM3 interrupt is generated Also timer operation can be stopped after an overflow by setting the OST bit of the TMC31 register to 1 When the timer is stopped due...

Page 382: ... as an external trigger capture trigger The TM3 count value during counting is captured and held in the capture register synchronized with that capture trigger signal The capture register value is held until the next capture trigger is generated Also an interrupt request INTCC30 or INTCC31 is generated by INTP30 or INTP31 signal input The valid edge of the capture trigger is set by valid edge sele...

Page 383: ...nual U15195EJ5V0UD Figure 9 92 TM3 Capture Operation Example When Both Edges Are Specified TM3 Count start TM3CE 1 Overflow TM3OVF 1 D0 D1 D2 D0 D1 D2 Interrupt request INTP31 TM3 count values Capture register CC31 Remark D0 to D2 TM3 count values ...

Page 384: ...e timer output pin TO3 to change and an interrupt request signal INTCC30 INTCC31 to be generated at the same time If the CC30 or CC31 register is set to 0000H 0000H after the TM3 register counts up from FFFFH to 0000H is judged as a match In this case the value of the TM3 register is cleared to 0 at the next count timing but 0000H is not judged as a match at that time 0000H when the TM3 register b...

Page 385: ...mpare Operation Example 2 2 b If CCLR bit 1 and CC30 register is 0000H 0001H TM3 Count up 0000H 0000H 0000H FFFFH Compare register CC30 INTTM3 Match detection INTCC30 TO3 output Remark The match is detected immediately after the count up and the match detection signal is generated ...

Page 386: ...he output level of the TO3 pin is reset The output level of the TO3 pin can be specified by the TMC31 register Table 9 15 TO3 Output Control TO3 Output ENT1 ALV External Pulse Output Output Level 0 0 Disable High level 0 1 Disable Low level 1 0 Enable When the CC30 register is matched Low level When the CC31 register is matched High level 1 1 Enable When the CC30 register is matched High level Whe...

Page 387: ...rned off the TO3 pin goes into a high impedance state To resume output of the TO3 pin output buffer on after output of the TO3 pin has been stopped output buffer off by the valid edge of the INTP4 pin rewrite the TO3SP bit from 1 to 0 The valid edge of the INTP4 pin can be specified by the ES40 and ES41 bits of the external interrupt mode register 2 INTM2 Figure 9 95 Example of Operation of TO3 Ou...

Page 388: ...of the CC30 register the TM3 register is cleared 0000H and an interrupt request signal INTCC30 is generated at the same time that the count operation resumes Figure 9 96 Contents of Register Settings When Timer 3 Is Used as Interval Timer Supply input clocks to internal units Enable count operation 0 0 1 0 1 0 1 1 0 1 0 1 1 OST ENT ALV ETI CCLR CMS1 CMS0 0 1 0 1 0 1 0 1 0 0 1 1 TM3OVF TMC30 TMC31 ...

Page 389: ...Operation Timing Example 0000H 0001H p 0000H 0001H p p p p p p 0000H 0001H Count start Clear Clear Interval time Interval time Interval time t Count clock TM3 register CC30 register INTCC30 interrupt Remark p Setting value of CC30 register 0000H to FFFFH t Count clock cycle Interval time p 1 t ...

Page 390: ...continues counting This enables a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register to be output When the setting value of the CC30 register and the setting value of the CC31 register are the same the TO3 output remains inactive and does not change The active level of TO3 output can be set by the ALV bit of the TMC31 register Figure 9 98 Contents of Regist...

Page 391: ...FFH 0001H Count start Clear Count clock TM3 register CC30 register CC31 register INTCC30 interrupt INTCC31 interrupt TO3 output t Remarks 1 p Setting value of CC30 register 0000H to FFFFH q Setting value of CC31 register 0000H to FFFFH p q t Count clock cycle PWM cycle 65536 t q p 65536 2 In this example the active level of TO3 output is set to high level Duty ...

Page 392: ...erence between the TM3 register s count value Dx that was captured in the CC30 register according to the x th valid edge input of the INTP30 pin and the TM3 register s count value D x 1 that was captured in the CC30 register according to the x 1 th valid edge input of the INTP30 pin and multiplying the value of this difference by the cycle of the clock control signal The cycle of signals input to ...

Page 393: ...D0 D1 D0 t D3 D2 t 10000H D1 D2 tNote Count clock TM3 register INTP30 input CC30 register INTCC30 interrupt INTTM3 interrupt No overflow Overflow occurs No overflow Count start Clear Note When an overflow occurs once Remarks 1 D0 to D3 TM3 register count values t Count clock cycle 2 In this example the valid edge of INTP30 input has been set to both edges rising and falling ...

Page 394: ...t 1 the TM3CAE bit 5 The analog noise elimination time two count clock cycles are required to detect a valid edge of the external interrupt input INTP30 or INTP31 and external clock input TI3 Therefore edge detection will not be performed normally for changes that are less than the analog noise elimination time two count clock cycles For the analog noise elimination refer to 12 5 Noise Eliminator ...

Page 395: ...of the count clock to 16 MHz or less Base clock fCLK 1 type set fCLK to 32 MHz or less fXX 2 Prescaler division ratio The following division ratios can be selected according to the base clock fCLK Division Ratio Base Clock fCLK 1 2 fXX 4 1 4 fXX 8 1 8 fXX 16 1 16 fXX 32 1 32 fXX 64 1 64 fXX 128 1 128 fXX 256 1 256 fXX 512 Interrupt request source 1 Compare match interrupt INTCM4 generated by CM4 m...

Page 396: ...er Timer Output S R Other Functions TM4 Read Timer 4 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 CM4 Read write INTCM4 Remark fXX Internal system clock S R Set Reset Figure 9 102 shows the block diagram of timer 4 Figure 9 102 Block Diagram of Timer 4 TM4 16 bit CM4 INTCM4 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 fXX 2 Clear start fCLK Remark fCLK Base clock 32 MHz MAX fXX Internal syst...

Page 397: ...1 If the TM4CAE0 bit of the TMC4 register is cleared 0 a reset is performed asynchronously 2 If the TM4CE0 bit of the TMC4 register is cleared 0 a reset is performed synchronized with the internal clock Similarly a synchronized reset is performed after a match with the CM4 register and after an overflow 3 The count clock must not be changed during a timer operation If it is to be overwritten it sh...

Page 398: ...ister is performed data on the master side is read out CM4 can be read written in 16 bit units Cautions 1 A write operation to the CM4 register requires 4 internal system clocks until the value that was set in the CM4 register is transferred to internal units When writing continuously to the CM4 register be sure to reserve a time interval of at least 4 internal system clocks 2 The CM4 register can...

Page 399: ...mple of Timing During TM4 Operation a When TM4 CM4 TM4 TM4CAE0 TM4CE0 CM4 INTCM4 M N N N Remark M TM4 value when overwritten N CM4 value after overwrite M N b When TM4 CM4 TM4 TM4CAE0 TM4CE0 CM4 INTCM4 M FFFFH N N N Remark M TM4 value when overwritten N CM4 value after overwrite M N ...

Page 400: ...If they are to be changed they must be changed after setting the TM4CE0 bit to 0 If the CS2 to CS0 bits are overwritten during timer operation the operation is not guaranteed 1 TM4CE0 Controls the operation of TM4 0 Count disabled timer stopped at 0000H and does not operate 1 Count operation performed Caution The TM4CE0 bit is not cleared even if a match is detected by the compare operation To sto...

Page 401: ...causes TM4 to be cleared 0 at the next count timing This function enables timer 4 to be used as an interval timer CM4 can also be set to 0 In this case when an overflow occurs and TM4 becomes 0 a match is detected and INTCM4 is generated Although the TM4 value is cleared 0 at the next count timing INTCM4 is not generated by this match Figure 9 104 TM4 Compare Operation Example 1 2 a When CM4 is se...

Page 402: ...2 User s Manual U15195EJ5V0UD Figure 9 104 TM4 Compare Operation Example 2 2 b When CM4 is set to 0 1 0 0 0 FFFFH Overflow TM4 Count clock CM4 TM4 clear Match detection INTCM4 Count up Clear Remark Interval time FFFFH 2 Count clock cycle ...

Page 403: ...ount operation begins the count cycle from 0000H to 0001H differs from subsequent count cycles 3 To initialize the TM4 register status and start counting again clear 0 the TM4CE0 bit and then set 1 the TM4CE0 bit after an interval of 4 internal system clocks has elapsed 4 Up to 4 internal system clocks are required until the value that was set in the CM4 register is transferred to internal units W...

Page 404: ...9 6 1 Overview The V850E IA2 provides a function to connect timer 1 and timer 2 Figure 9 105 Block Diagram of Timer Connection Function Timer 2 Timer 1 CVSE10 CVPE10 CVSE20 CVPE20 Capture 0 Capture 1 TMIC0 TMIC1 TMIC2 TMIC3 TMIC0 register INTCM1 INTCM0 INTCM101 INTCM100 Timer connection selector ...

Page 405: ...o CVSE20 CVPE20 registers 0 INTCM101 signal not input to CVSE20 CVPE20 registers 1 INTCM101 signal input to CVSE20 CVPE20 registers 2 TMIC2 Enables disables input of INTCM100 signal to CVSE20 CVPE20 registers 0 INTCM100 signal not input to CVSE20 CVPE20 registers 1 INTCM100 signal input to CVSE20 CVPE20 registers 1 TMIC1 Enables disables input of INTCM101 signal to CVSE10 CVPE10 registers 0 INTCM1...

Page 406: ...ronous serial interfaces UART0 UART1 2 channels 2 Clocked serial interfaces CSI0 CSI1 2 channels UART0 UART1 in which one byte of serial data is transmitted received following a start bit support full duplex communication In the UART1 interface one higher bit is added to 8 bits of transmit receive data enabling communication using 9 bit data CSI0 and CSI1 perform data transfer according to three t...

Page 407: ... register PFC3 refer to 12 3 4 Port 3 Caution UART1 or CSI1 transmission reception operations are not guaranteed if the mode is switched between UART1 and CSI1 during transmission or reception Figure 10 1 Selecting Mode of UART1 or CSI1 7 0 PMC3 6 0 5 0 4 PMC34 3 PMC33 2 PMC32 1 PMC31 0 PMC30 Address FFFFF446H After reset 00H 7 0 PFC3 6 0 5 0 4 PFC34 3 PFC33 2 PFC32 1 0 0 0 Address FFFFF466H After...

Page 408: ...NTSER0 Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSR0 Interrupt is generated when receive data is transferred from the receive shift register to receive buffer register 0 after serial transfer is completed during a reception enabled state Transmission completion interrupt INTST0 Interrupt is generated when the serial ...

Page 409: ...ion is in progress 4 Reception control parity check The receive operation is controlled according to the contents set in the ASIM0 register A check for parity errors is also performed during a receive operation and if an error is detected a value corresponding to the error contents is set in the ASIS0 register 5 Receive shift register This is a shift register that converts the serial data that was...

Page 410: ... data that is written to the TXB0 register according to the contents that were set in the ASIM0 register Figure 10 2 Asynchronous Serial Interface 0 Block Diagram Parity Framing Overrun Internal bus Asynchronous serial interface mode register 0 ASIM0 Receive buffer register 0 RXB0 Receive shift register Reception control parity check Transmit buffer register 0 TXB0 Transmit shift register Addition...

Page 411: ...RTCAE0 Controls the operating clock 0 Stops clock supply to UART0 1 Supplies clock to UART0 Cautions 1 If UARTCAE0 0 UART0 is asynchronously reset Note 2 If UARTCAE0 0 UART0 is reset To operate UART0 first set UARTCAE0 to 1 3 If the UARTCAE0 bit is cleared from 1 to 0 all the registers of UART0 are initialized To set UARTCAE0 to 1 again be sure to re set the registers of UART0 The output of the TX...

Page 412: ... number of bits with the value 1 the parity bit is set 1 If it contains an even number of bits with the value 1 the parity bit is cleared 0 This controls the number of bits with the value 1 contained in the transmit data and the parity bit so that it is an even number During reception the number of bits with the value 1 contained in the receive data and the parity bit is counted and if the number ...

Page 413: ...L bit first clear 0 the TXE0 and RXE0 bits 1 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Cautions 1 To overwrite the SL bit first clear 0 the TXE0 bit 2 Since reception is always done with a stop bit length of 1 the SL bit setting does not affect receive operations 0 ISRM Enables disables generation of reception completion interrupt requests when an error occurs 0 Generate a rec...

Page 414: ... a status flag that indicates a parity error 0 When the ASIM0 register s UARTCAE0 and RXE0 bits are both set to 0 or after the ASIS0 register is read 1 When the receive data parity does not match the parity bit after receive completion Caution The operation of the PE bit differs according to the settings of the PS1 and PS0 bits of the ASIM0 register 1 FE This is a status flag that indicates a fram...

Page 415: ...egister s UARTCAE0 or TXE0 bits is 0 or when data has been transferred to the transmit shift register 1 Data to be transferred next exists in TXB0 register Data exists in TXB0 register when the TXB0 register has been written to Caution When transmission is performed continuously data should be written to the TXB0 register after confirming that this flag is 0 If writing to TXB0 register is performe...

Page 416: ...the ASIM0 register the contents of the RXB0 register are retained and no processing is performed for transferring data to the RXB0 register even when the shift in processing of one frame is completed Also no INTSR0 signal is generated When 7 bits is specified for the data length bits 6 to 0 of the RXB0 register are transferred for the receive data and the MSB bit 7 is always 0 However if an overru...

Page 417: ...register data is transferred to the transmit shift register and a transmission completion interrupt request INTST0 is generated synchronized with the completion of the transmission of one frame from the transmit shift register For information about the timing for generating this interrupt request refer to 10 2 5 2 Transmit operation When TXBF0 bit 1 in the ASIF0 register writing must not be perfor...

Page 418: ...n data is shifted in to the receive shift register and transferred to receive buffer register 0 RXB0 An INTSR0 signal can be generated in place of a reception error interrupt INTSER0 according to the ISRM bit of the ASIM0 register even when a reception error has occurred When reception is disabled no INTSR0 signal is generated 2 Transmission completion interrupt INTST0 An INTST0 signal is generate...

Page 419: ... Figure 10 3 The character bit length within one data frame the type of parity and the stop bit length are specified according to asynchronous serial interface mode register 0 ASIM0 Also data is transferred with LSB first Figure 10 3 Asynchronous Serial Interface Transmit Receive Data Format 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bits Character bits Start bit 1 bit Characte...

Page 420: ...nsmit buffer register 0 TXB0 When a transmit operation is started the data in the TXB0 register is transferred to transmit shift register Then the transmit shift register outputs data to the TXD0 pin the transmit data is transferred sequentially starting with the start bit The start bit parity bit and stop bits are added automatically c Transmission interrupt request When the transmit shift regist...

Page 421: ...195EJ5V0UD 421 Figure 10 4 Asynchronous Serial Interface Transmission Completion Interrupt Timing Start Stop D0 D1 D2 D6 D7 Parity Parity TXD0 output INTST0 output Start D0 D1 D2 D6 D7 TXD0 output INTST0 output a Stop bit length 1 b Stop bit length 2 Stop ...

Page 422: ...ased only on the TXBF0 bit when performing continuous transmission TXBF0 Whether or Not Writing to TXB0 Register Is Enabled 0 Writing is enabled 1 Writing is not enabled Caution When transmission is performed continuously write the first transmit data first byte to the TXB0 register and confirm that the TXBF0 bit is 0 and then write the next transmit data second byte to TXB0 register If writing to...

Page 423: ...rrupt Required number of transfers performed Write the first byte of the transmit data to TXB0 register Write transmit data to TXB0 register When reading ASIF0 register TXBF0 0 When reading ASIF0 register TXSF0 1 When reading ASIF0 register TXSF0 0 No No No No Yes Yes Yes Yes End of transmission processing Write the second byte of the transmit data to the TXB0 register ...

Page 424: ... 10 Note Refer to 10 2 7 Cautions 2 ASIF0 Register Transmission Starting Procedure Internal Operation TXBF0 TXSF0 Set transmission mode 1 Start transmission unit 0 0 Write data 1 1 0 2 Generate start bit Read ASIF0 register confirm that TXBF0 bit 0 Start data 1 transmission 1 0 0 0 1 Note 1 1 1 Write data 2 Transmission in progress 1 1 3 INTST0 interrupt occurs Read ASIF0 register confirm that TXB...

Page 425: ...op bit Stop bit ASIF0 Register Transmission End Procedure Internal Operation TXBF0 TXSF0 6 Transmission of data m 2 is in progress 1 1 7 INTST0 interrupt occurs Read ASIF0 register confirm that TXBF0 bit 0 0 0 1 1 Write data m 8 Generate start bit Start data m 1 transmission Transmission in progress 1 1 9 INTST0 interrupt occurs Read ASIF0 register confirm that TXSF0 bit 1 There is no write data 1...

Page 426: ... operation is started by the detection of a start bit The RXD0 pin is sampled using the serial clock from baud rate generator 0 BRG0 c Reception completion interrupt When RXE0 1 in the ASIM0 register and the reception of one frame of data is completed the stop bit is detected a reception completion interrupt INTSR0 is generated and the receive data in the receive shift register is transferred to t...

Page 427: ...overrun error As a result of data reception the various flags of the ASIS0 register are set 1 and a reception error interrupt INTSER0 or a reception completion interrupt INTSR0 is generated at the same time The ISRM bit of the ASIM0 register specifies whether an INTSER0 or INTSR0 signal is generated The type of error that occurred during reception can be detected by reading the contents of the ASI...

Page 428: ...ption INTSR0 signal output Reception completion interrupt INTSER0 signal output Reception error interrupt INTSR0 signal output Reception completion interrupt INTSER0 signal output Reception error interrupt INTSR0 signal does not occur Figure 10 10 When Reception Error Interrupt Is Included in INTSR0 Signal ISRM Bit 1 a No error occurs during reception b An error occurs during reception INTSR0 sign...

Page 429: ... is odd b Odd parity i During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd The parity bit value is as follows If the number of bits with the value 1 within the transmit data is odd 0 If the number of bits with the value 1 within the transmit data is even 1 ii During receptio...

Page 430: ... not delivered to the internal circuit see Figure 10 12 Refer to 10 2 6 1 a Base clock Clock regarding the base clock Also since the circuit is configured as shown in Figure 10 11 internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status Figure 10 11 Noise Filter Circuit RXD0 fCLK Q Clock In LD_EN Q In Internal signal A Internal signal B Ma...

Page 431: ...eception 1 Baud rate generator 0 BRG0 configuration Figure 10 13 Configuration of Baud Rate Generator 0 BRG0 fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1 024 fXX 2 048 Clock fCLK Selector UARTCAE0 8 bit counter Match detector Baud rate BRGC0 MDL7 to MDL0 1 2 UARTCAE0 and TXE0 or RXE0 CKSR0 TPS3 to TPS0 fXX Remark fXX Internal system clock a Base clock Clock When the UARTCAE...

Page 432: ... in 8 bit units Cautions 1 The maximum allowable frequency of the base clock fCLK is 20 MHz Therefore when the system clock s frequency is 40 MHz TPS3 to TPS0 bits cannot be set to 0000B At 40 MHz set the TPS3 to TPS0 bits to a value other than 0000B and set the UARTCAE0 bit of the ASIM0 register to 1 2 Set the UARTCAE0 bit of the ASIM0 register to 0 before rewriting the TPS3 to TPS0 bits 7 6 5 4 ...

Page 433: ...FFA07H FFH Bit position Bit name Function Specifies the 8 bit counter s division value MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 Division value k Serial clock 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fCLK 8 0 0 0 0 1 0 0 1 9 fCLK 9 0 0 0 0 1 0 1 0 10 fCLK 10 1 1 1 1 1 0 1 0 250 fCLK 250 1 1 1 1 1 0 1 1 251 fCLK 251 1 1 1 1 1 1 0 0 252 fCLK 252 1 1 1 1 1 1 0 1 253 fCLK 253 1 1 1 1 1 1 1 0 254 f...

Page 434: ...ate baud Desired error with rate baud rate baud Actual Error Cautions 1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable baud rate range during reception which is described in 4 Allowable baud rate during reception Example Base clock frequency 20 MHz ...

Page 435: ... 3 130 0 16 9600 fXX 2 5 65 0 16 fXX 2 3 215 0 07 fXX 2 2 130 0 16 19200 fXX 2 4 65 0 16 fXX 2 2 215 0 07 fXX 2 1 130 0 16 31250 fXX 2 3 80 0 fXX 2 2 132 0 fXX 2 1 80 0 38400 fXX 2 3 65 0 16 fXX 2 1 215 0 07 fXX 2 0 130 0 16 76800 fXX 2 2 65 0 16 fXX 2 1 107 0 39 fXX 2 0 65 0 16 153600 fXX 2 1 65 0 16 fXX 2 1 54 0 54 fXX 2 0 33 1 36 312500 fXX 2 1 32 0 fXX 2 1 26 1 54 fXX 2 0 16 0 625000 fXX 2 1 1...

Page 436: ...ty bit Minimum allowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 10 14 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the BRGC0 register If all data up to the final data stop bit is in time for this l...

Page 437: ...d rate error of UART0 and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 10 4 Maximum and Minimum Allowable Baud Rate Error Division Ratio k Maximum Allowable Baud Rate Error Minimum Allowable Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks 1 The receptio...

Page 438: ...autions to be observed when using UART0 are shown below 1 When the supply of clocks to UART0 is stopped for example in IDLE or software STOP mode operation stops with each register retaining the value it had immediately before the supply of clocks was stopped The TXD0 pin output also holds and outputs the value it had immediately before the supply of clocks was stopped However operation is not gua...

Page 439: ...rror Framing error Overrun error Interrupt sources 2 types Reception completion interrupt INTSR1 Interrupt is generated when receive data is transferred from the shift register to receive buffer register 1 RXB1 after serial transfer is completed during a reception enabled state Transmission completion interrupt INTST1 Interrupt is generated when the serial transmission of trans mit data 8 7 bits f...

Page 440: ...ffer register RXB1 receive buffer register RXBL1 RXB1 is a 16 bit during 2 frame continuous reception 9 bit extension data reception buffer register that holds receive data During 7 or 8 bit character reception 0 is stored in the MSB For 16 bit access to this register specify RXB1 and for access to the lower 8 bits specify RXBL1 In the reception enabled state receive data is transferred from the r...

Page 441: ... 10 11 ASIM10 ASIM11 Asynchronous serial interface status registers 1 ASIS1 Transmission control parity addition Reception buffers 1 L1 RXB1 RXBL1 PE1 FE1 OVE1 Receive shift register RXD1 TXD1 MOD bit ASCK1 Reception control parity check Selector Selector Selector INTST1 INTSR1 SOT1 flag BRG1 SIR1 flag Internal bus 1 16 1 16 Remark The TXD1 RXD1 and ASCK1 pins function alternately as the SO1 SI1 a...

Page 442: ...read written in 8 bit or 1 bit units Cautions 1 If any bits other than the RXE1 bit of the ASIM10 register are changed during UART1 transmission or reception the UART1 operation cannot be guaranteed 2 Set bits other than the RXE1 bit of the ASIM10 register when the UART1 operation is stopped when RXE1 0 and transmission is completed Change the port 3 mode control register PMC3 after setting the co...

Page 443: ...0 Operation 0 0 No parity extension bit operation 0 1 0 parity Transmit side Transmission with parity bit 0 Receive side No parity error generated during reception 1 0 Odd parity 1 1 Even parity 5 4 PS1 PS0 3 CL Specifies character length of transmit data 1 frame 0 7 bits 1 8 bits 2 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Specifies serial clock source Operation SCLS In async...

Page 444: ...rame receptions 0 1 frame data reception 1 2 frame continuous data reception 0 EBS Specifies extension bit operation for transmit receive data when no parity is specified PS0 PS1 0 0 Disables extension bit addition 1 Enables extension bit addition When the extension bit is specified 1 data bit is added on top of the 8 bits of transmit receive data enabling 9 bit data communication Extension bit sp...

Page 445: ...n end The status flag that indicates reception errors always indicates the most recent error status In other words if the same error occurs several times before receive data is read this flag holds only the status of the error that occurred last Each time the ASIS1 register is read after a reception completion interrupt INTSR1 read the reception buffer RXB1 or RXBL1 The error flag is cleared when ...

Page 446: ...tart bit detection timing 4 RB8 Indicates contents of receive data extension bit 1 bit when 9 bit extended format is specified EBS bit of ASIM11 register 1 2 PE1 Status flag indicating parity error 0 Processing to read data from reception buffer 1 When transmit parity and receive parity don t match Caution No parity error is generated if no parity is specified or 0 parity is specified by the PS1 P...

Page 447: ...disabled status transfer processing to the reception buffer is not performed even if shift in processing for 1 frame of data has been completed and the contents of the reception buffer are held Neither is a reception completion interrupt request generated The RXB1 register can be read in 16 bit units and the RXBL1 register can be read in 8 bit units 14 RXB14 13 RXB13 12 RXB12 2 RXB2 3 RXB3 4 RXB4 ...

Page 448: ...5 RXB15 1 RXB1 0 RXB0 RXB1 7 8 bit data of 1st frame 7 8 bit data of 2nd frame b When 9 bit extension reception is set 14 RXB14 13 RXB13 12 RXB12 2 RXB2 3 RXB3 4 RXB4 5 RXB5 6 RXB6 7 RXB7 8 RXB8 9 RXB9 10 RXB10 11 RXB11 15 RXB15 1 RXB1 0 RXB0 RXB1 9 bit extended data When 9 bit extension is set the extension bit RXB8 is stored in the RB8 bit of the ASIS1 register simultaneously with saving to the ...

Page 449: ...f reception of 2nd frame no error RXD1 Frame 1 Frame 2 No reception completion interrupt generated at end of reception of 3rd frame occurrence of error RXD1 Frame 3 Frame 3 Value of OVE1 bit of ASIS1 register becomes 1 Reception completion interrupt INTSR1 generated at end of reception of 4th frame no error RXD1 Frame 3 Frame 4 Value of OVE1 frame of ASIS1 register remains 1 Start of reception of ...

Page 450: ... and for access to the lower 8 bits specify TXSL1 The TXS1 register is write only in 16 bit units and the TXSL1 register is write only in 8 bit units Caution TXS1 TXSL1 can be read but since shifting is done in synchronization with the shift clock the data that is read cannot be guaranteed 14 TXS14 13 TXS13 12 TXS12 2 TXS2 3 TXS3 4 TXS4 5 TXS5 6 TXS6 7 TXS7 8 TXS8 9 TXS9 10 TXS10 11 TXS11 15 TXS15...

Page 451: ...t INTSR1 is generated when data in the receive shift register undergoes shift in processing and is transferred to the reception buffer The reception completion interrupt request INTSR1 is generated following stop bit sampling and upon the occurrence of an error In the reception disabled state no reception completion interrupt is generated Caution A reception completion interrupt INTSR1 is generate...

Page 452: ...register 10 ASIM10 Specification of the number of frames and specification of the extension bit is mode using asynchronous serial interface mode register 11 ASIM11 Data is transmitted LSB first Figure 10 17 Asynchronous Serial Interface Transmit Receive Data Format a 1 frame format 1 frame Data Stop bit Start bit Parity extension bit D0 D1 D2 D3 D4 D5 D6 D7 b 2 frame format Higher frame Lower fram...

Page 453: ... DATA Parity bit Stop bit 0 0 0 DATA Stop bit Stop bit 0 Other than PS1 PS0 0 DATA Parity bit Stop bit Stop bit 1 0 0 DATA DATA Stop bit Stop bit 1 Other than PS1 PS0 0 1 0 DATA DATA Parity bit Stop bit Stop bit 0 0 0 DATA Stop bit 0 Other than PS1 PS0 0 DATA Parity bit Stop bit 1 0 0 DATA DATA DATA Stop bit 1 Other than PS1 PS0 0 0 1 DATA DATA Parity bit Stop bit 0 0 0 DATA Stop bit Stop bit 0 Ot...

Page 454: ...smission interrupt request When the transmit shift register becomes empty upon completion of the transmission of 1 or 2 frames of data a transmission completion interrupt request INTST1 is generated The INTST1 interrupt generation timing differs depending on the specification of the stop bit length The INTST1 interrupt is generated at the same time that the last stop bit is output The transmission...

Page 455: ...bit Start Parity Stop D0 TXD1 output INTST1 interrupt Flag in transmission SOT1 D1 D2 D6 D7 b When stop bit length 2 bits Start Parity Stop D0 TXD1 output INTST1 interrupt Flag in transmission SOT1 D1 D2 D6 D7 c In 2 frame continuous transmission mode Start Start Stop Parity Stop D0 TXD1 output INTST1 interrupt Flag in transmission SOT1 D1 1st frame 2nd frame D1 D5 D6 D7 Parity ...

Page 456: ...ression t Time of one stop bit 2 2 fXX 4 2 fXX fXX Internal system clock Caution 4 2 fXX has a margin of double the clock that can actually be used for operation Example Count clock frequency 32 MHz 32 000 000 Hz Target baud rate in synchronous mode 9 600 bps t 1 9615 385 4 8 32 000 000 104 000 0 375 103 625 µs Therefore be sure to write transmit data to TXS1 TXSL1 within 103 µs of the generation ...

Page 457: ...rator After 8 serial clocks have been output following detection of the falling edge of the RXD1 pin the RXD1 pin is again sampled If a low level is detected at this time the falling edge of the RXD1 pin is interpreted as a start bit the operation shifts to reception processing and the RXD1 pin input is sampled from this point on in units of 16 serial clock output If the high level is detected dur...

Page 458: ...1 bit of the ASIM10 register 1 the receive data in the shift register is transferred to RXB1 RXBL1 and a reception completion interrupt request INTSR1 is generated after 1 frame or 2 frames of data have been transferred to RXB1 RXBL1 A reception completion interrupt is also generated upon detection of an error When the RXE1 bit 0 reception disabled no reception completion interrupt is generated ...

Page 459: ...ial clocks 8 serial clocks c In 2 frame continuous transmission mode D0 D1 D1 D5 D6 D7 Start Start Parity Stop Parity Stop RXD1 input INTSR1 interrupt Flag in reception SIR1 1st frame 2nd frame 8 serial clocks 8 serial clocks Cautions 1 Even if a reception error occurs be sure to read 2 frame continuous reception buffer register 1 RXB1 receive buffer register 1 RXBL1 If the RXB1 or RXBL1 register ...

Page 460: ...Reception Error Causes PE1 Parity error The parity specification during transmission did not match the parity of the reception data FE1 Framing error No stop bit was detected OVE1 Overrun error The reception of the next data was completed before data was read from the reception buffer 6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data Normal...

Page 461: ...e transmit data is even 1 2 During reception The number of bits with the value 1 within the receive data including the parity bit is counted and a parity error is generated if this number is even c 0 parity During transmission the parity bit is set to 0 regardless of the transmit data During reception no parity bit check is performed Therefore no parity error is generated regardless of whether the...

Page 462: ...hat outputs between connection nodes do not conflict In the synchronous mode the falling edge of the serial clock is used as the transmission timing and the rising edge as the reception timing but transmit data is output with a delay of 1 system clock serial clock in the external clock synchronous mode the maximum delay is 2 5 system clocks Figure 10 21 Transmission Reception Timing in Synchronous...

Page 463: ...1 frame transmission reception mode Serial clock Transmission register write signal Flag in transmission SOT1 Transmission completion interrupt INTST1 Reception completion interrupt INTSR1 Reception buffer RXB1 Reception buffer RXBL1 Flag in reception SIR1 Transmit data Stop bit Undefined hold previous value Undefined hold previous value 005AH 5AH ...

Page 464: ...ous transmission reception mode Serial clock Transmission register write signal Flag in transmission SOT1 Transmission completion interrupt INTST1 Reception completion interrupt INTSR1 Reception buffer RXBL1 Reception buffer RXBL1 Flag in reception SIR1 Transmit data Stop bit Stop bit Undefined hold previous value Undefined hold previous value 5A5AH 5AH 5A15H 15H ...

Page 465: ...ng Note The transmit data is delayed by 1 system clock in relation to the serial clock d Transmission reception timing and transmit data timing using external serial clock Note External serial clock System clock Transmit data Transmission timing Reception timing Note Since during external serial clock synchronization synchronization is done with the internal system clock when feeding the external ...

Page 466: ...a Flag in reception SIR1 Reception completion interrupt INTSR1 Error interrupt STOP STOP 1 2 3 Explanation 1 If the start bit of the second frame is not detected no reception completion interrupt is generated 2 If an error occurs in the first frame an error interrupt is generated following detection of the stop bit of the first frame at the calculated position 3 If an error occurs in the second fr...

Page 467: ...h channel The serial clock source is specified by register ASIM10 If dedicated baud rate generator output is specified BRG1 is selected as the clock source Since the same serial clock can be shared for transmission and reception for one channel baud rate is the same for the transmission reception Figure 10 24 Block Diagram of Baud Rate Generator 1 BRG1 BGCS1 BGCS0 PRSCM1 Match detector 1 2 UART1 8...

Page 468: ...te signal These registers can be read written in 8 bit or 1 bit units Cautions 1 Do not change the values of the BGCS1 and BGCS0 bits during transmission reception operations 2 Set PRSM1 bits other than the UARTCE1 bit prior to setting the UARTCE1 bit to 1 7 UARTCE1 PRSM1 6 0 5 0 4 0 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFFA2EH After reset 00H Bit position Bit name Function 7 UARTCE1 Enables baud rat...

Page 469: ... 3 PRSCM3 2 PRSCM2 1 PRSCM1 0 PRSCM0 Address FFFFFA30H After reset 00H d Baud rate generation First when the UARTCE1 bit of the PRSM1 register is overwritten by 1 the 8 bit timer counter for baud rate signal generation starts counting up with the clock selected by bits BGCS1 and BGCS0 of the PRSM1 register The count value of the 8 bit timer counter is compared with the value of the PRSCM1 register...

Page 470: ...of PRSM1 register k 0 1 2 3 Note The setting of m 256 is performed by writing 00H to the PRSCM1 register 2 Formula for calculating the baud rate in synchronous mode Baud rate bps fXX Internal system clock frequency Hz CPU clock 2 Hz m Setting value of PRSCM1 register 1 m 256 Note k Value set by bits BGCS1 BGCS0 of PRSM1 register k 0 1 2 3 Note The setting of m 256 is performed by writing 00H to th...

Page 471: ... 153 600 9 600 153 846 2 9 615 385 2 13 0 16 166 400 10 400 166 666 7 10 416 67 1 24 0 16 307 200 19 200 307 692 3 19 230 77 1 13 0 16 614 400 38 400 615 384 6 38 461 54 0 13 0 16 Not possible 76 800 71 428 57 0 7 6 99 Not possible 153 600 166 666 7 0 3 8 51 b When fXX 40 MHz Target Baud Rate Actual Baud Rate Synchronous Mode Asynchronous Mode Synchronous Mode Asynchronous Mode BGCSm Bit m 0 1 PRS...

Page 472: ...llowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 10 25 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the PRSCM1 register If all data up to the final data stop bit is in time for this latch timing the...

Page 473: ... FLmax can be obtained as follows FL k 2 2 k 21 FL k 2 2 k FL 11 max FL 11 10 11 FL k 20 2 k 21 max FL Therefore the transfer destination s minimum receivable baud rate BRmin is as follows BRmin FLmax 11 1 Brate 4 Transfer rate in 2 frame continuous reception In 2 frame continuous reception the timing is initialized by detecting the start bit of the second frame so the transfer results are not aff...

Page 474: ...n MSB first and LSB first Eight clock signals can be selected 7 master clocks and 1 slave clock 3 wire type SOn Serial transmit data output SIn Serial receive data input SCKn Serial clock I O Interrupt sources 1 type Transmission reception completion interrupt INTCSIn Transmission reception mode and reception only mode can be specified Two transmit buffers SOTBFn SOTBFLn SOTBn SOTBLn and two recei...

Page 475: ...LSB side The actual transmission reception operations are started up by access of the buffer register 5 Clocked serial interface receive buffer registers 0 1 SIRB0 SIRB1 The SIRBn register is a 16 bit buffer register that stores receive data 6 Clocked serial interface receive buffer registers L0 L1 SIRBL0 SIRBL1 The SIRBLn register is an 8 bit buffer register that stores receive data 7 Clocked ser...

Page 476: ...elector The selector selects the serial clock to be used 14 Serial clock controller Controls the serial clock supply to the shift register Also controls the clock output to the SCKn pin when the internal clock is used 15 Serial clock counter Counts the serial clock output or input during transmission reception operation and checks whether 8 bit or 16 bit data transmission reception has been perfor...

Page 477: ...er register SIRBn SIRBLn Shift register SIOn SIOLn Initial transmit buffer register SOTBFn SOTBFLn Interrupt controller Clock start stop control clock phase control Serial clock controller SCKn INTCSIn SOn SIn Control signal Transmission data control fXX 27 fXX 26 fXX 25 fXX 24 fXX 23 fXX 22 BRG3 SCKn Remarks 1 n 0 1 2 fXX Internal system clock 3 The SO1 SI1 and SCK1 pins function alternately as t...

Page 478: ...ing mode of UART1 or CSI1 1 Clocked serial interface mode registers 0 1 CSIM0 CSIM1 The CSIMn register controls the CSIn operation n 0 1 These registers can be read written in 8 bit or 1 bit units however bit 0 is read only Caution Overwriting the TRMDn CCL DIRn CSIT and AUTO bits of the CSIMn register can be done only when the CSOTn bit 0 If these bits are overwritten at any other time the operat...

Page 479: ...en the TRMDn bit 1 transmission reception is started by writing data to the SOTBn register 5 CCL Specifies data length 0 8 bits 1 16 bits 4 DIRn Specifies transfer direction mode MSB LSB 0 First bit of transfer data is MSB 1 First bit of transfer data is LSB 3 CSIT Controls delay of interrupt request signal 0 No delay 1 Delay mode interrupt request signal is delayed 1 2 cycle The delay mode CSIT b...

Page 480: ...rface clock selection registers 0 1 CSIC0 CSIC1 The CSICn register is an 8 bit register that controls the CSIn transfer operation n 0 1 These registers can be read written in 8 bit or 1 bit units Caution The CSICn register can be overwritten only when the CSICAEn bit of the CSIMn register 0 ...

Page 481: ...1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn output SCKn I O SIn input 1 0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn output SCKn I O SIn input 1 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn output SCKn I O SIn input 4 3 CKP DAP Remark n 0 1 Specifies serial clock CKS2 CKS1 CKS0 Serial clock Mode 0 0 0 fXX 2 7 Master mode 0 0 1 fXX 2 6 Master mode 0 1...

Page 482: ...he 16 bit data length has been set CCL bit of CSIMn register 1 2 When the single transfer mode has been set AUTO bit of CSIMn register 0 perform a read operation only in the idle state CSOTn bit of CSIMn register 0 If the SIRBn register is read during data transfer the data cannot be guaranteed 14 SIRB 14 13 SIRB 13 12 SIRB 12 2 SIRB 2 3 SIRB 3 4 SIRB 4 5 SIRB 5 6 SIRB 6 7 SIRB 7 8 SIRB 8 9 SIRB 9...

Page 483: ...f the CSIMn register The SIRBLn register is the same as the lower bytes of the SIRBn register Cautions 1 Read the SIRBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform a read operation only in the idle state CSOTn bit of CSIMn register 0 If the SIRBLn register is read during data transfer...

Page 484: ...Cautions 1 The receive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if the 16 bit data length is set CCL bit of CSIMn register 1 14 SIRBE 14 13 SIRBE 13 12 SIRBE 12 2 SIRBE 2 3 SIRBE 3 4 SIRBE 4 5 SIRBE 5 6 SIRBE 6 7 SIRBE 7 8 SIRBE 8 9 SIRBE 9 10 SIRBE 10 11 SIRBE 11 15 SIRBE 15 1 SIRBE 1 0 SIRBE 0 14 SIRBE 14 13 SIRBE 13 12 SIRBE 1...

Page 485: ...SIRBELn register is the same as the SIRBLn register It is used to read the contents of the SIRBLn register Cautions 1 The receive operation is not started even if data is read from the SIRBELn register 2 The SIRBELn register can be read only if the 8 bit data length has been set CCL bit of CSIMn register 0 7 SIRBE7 SIRBEL0 6 SIRBE6 5 SIRBE5 4 SIRBE4 3 SIRBE3 2 SIRBE2 1 SIRBE1 0 SIRBE0 Address FFFF...

Page 486: ...SIMn register 1 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOTn bit of CSIMn register 0 If the SOTBn register is accessed during data transfer the data cannot be guaranteed 14 SOTB 14 13 SOTB 13 12 SOTB 12 2 SOTB 2 3 SOTB 3 4 SOTB 4 5 SOTB 5 6 SOTB 6 7 SOTB 7 8 SOTB 8 9 SOTB 9 10 SOTB 10 11 SOTB 11 15 SOTB 15 1 SOTB 1 0 SOTB 0 SOTB0 A...

Page 487: ...same as the lower bytes of the SOTBn register Cautions 1 Access the SOTBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOTn bit of CSIMn register 0 If the SOTBLn register is accessed during data transfer the data cannot be guaranteed 7 SOTB7 SOTBL0 6 SOTB...

Page 488: ...CSIMn register 1 and only in the idle state CSOTn bit of CSIMn register 0 If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 14 SOTBF 14 13 SOTBF 13 12 SOTBF 12 2 SOTBF 2 3 SOTBF 3 4 SOTBF 4 5 SOTBF 5 6 SOTBF 6 7 SOTBF 7 8 SOTBF 8 9 SOTBF 9 10 SOTBF 10 11 SOTBF 11 15 SOTBF 15 1 SOTBF 1 0 SOTBF 0 14 SOTBF 14 13 SOTBF 13 12 SOTBF 12 2 SOTBF 2 3 SOTBF 3 4 SOTBF 4 5 ...

Page 489: ...is the same as the lower bytes of the SOTBFn register Caution Access the SOTBFLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOTn bit of CSIMn register 0 If the SOTBFLn register is accessed during data transfer the data cannot be guaranteed 7 SOTBF7 SOTBFL0 6 SOTBF6 5 SOTBF5 4 SOTBF4 3 SOTBF3 2 SOTBF2 1 SOTBF1 0 SOTBF0 Address FFFFF...

Page 490: ...only when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOTn bit of CSIMn register 0 If the SIOn register is accessed during data transfer the data cannot be guaranteed 14 SIO14 13 SIO13 12 SIO12 2 SIO2 3 SIO3 4 SIO4 5 SIO5 6 SIO6 7 SIO7 8 SIO8 9 SIO9 10 SIO10 11 SIO11 15 SIO15 1 SIO1 0 SIO0 SIO0 Address FFFFF90AH After reset 0000H 14 SIO14 13 SIO13 12...

Page 491: ...egister The SIOLn register is the same as the lower bytes of the SIOn register Caution Access the SIOLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOTn bit of CSIMn register 0 If the SIOLn register is accessed during data transfer the data cannot be guaranteed 7 SIO7 SIOL0 6 SIO6 5 SIO5 4 SIO4 3 SIO3 2 SIO2 1 SIO1 0 SIO0 7 SIO7 6 S...

Page 492: ... value of the CSOTn bit of the CSIMn register becomes 1 transmission execution status Upon transfer completion the transmission reception completion interrupt INTCSIn is set 1 and the CSOTn bit is cleared 0 The next data transfer request is then waited for Notes 1 When the 16 bit data length CCL bit of CSIMn register 1 has been set read the SIRBn register When the 8 bit data length CCL bit of CSIM...

Page 493: ...ration mode CKP bit 0 DAP bit 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 55H AAH AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt 55H transmit data Write 55H to SOTBLn register Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data...

Page 494: ...ration mode CKP bit 0 DAP bit 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt 55H AAH 55H transmit data Write 55H to SOTBLn register Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data...

Page 495: ...st signal delay control CSIT bit of CSIMn register 0 Figure 10 28 Timing Chart According to Clock Phase Selection 1 2 a When CKP bit 0 DAP bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 b When CKP bit 1 DAP bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTC...

Page 496: ...O1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 d When CKP bit 1 DAP bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn writ...

Page 497: ...not 111B The delay mode cannot be set when the slave mode is set bits CKS2 to CKS0 111B Figure 10 29 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKP bit 0 DAP bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit Delay Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indi...

Page 498: ...hen CKP bit 1 DAP bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit Delay Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed ...

Page 499: ...ransmission reception completion interrupt request INTCSIn has been set 1 read the SIRBn registerNote reserve next transfer 5 Repeat steps 3 and 4 N 2 times N Number of transfer data 6 Following output of the last transmission reception completion interrupt request INTCSIn read the SIRBEn register and the SIOn registerNote Note When transferring N number of data receive data is loaded by reading t...

Page 500: ... indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the first transfer Following the transmission reception completion interrupt request INTCSIn transfer is continued if the SIRBn register...

Page 501: ...nterrupt request INTCSIn 5 When the transmission reception completion interrupt request INTCSIn has been set 1 write the next data to the SOTBn register reserve next transfer and read the SIRBn register to load the receive data 6 Repeat steps 4 and 5 as long as data to be sent remains 7 Wait for the INTCSIn interrupt When the interrupt request signal is set 1 read the SIRBn register to load the N ...

Page 502: ...al This signal indicates that the transmit data buffer register SOTBn SOTBLn has been written Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the firs...

Page 503: ...red with the period shown in Figure 10 32 Figure 10 32 Timing Chart of Next Transfer Reservation Period 1 2 a When data length 8 bits operation mode CKP bit 0 DAP bit 0 SCKn I O INTCSIn interrupt Reservation period 7 SCKn cycles b When data length 16 bits operation mode CKP bit 0 DAP bit 0 SCKn I O INTCSIn interrupt Reservation period 15 SCKn cycles Remark n 0 1 ...

Page 504: ... Next Transfer Reservation Period 2 2 c When data length 8 bits operation mode CKP bit 0 DAP bit 1 SCKn I O INTCSIn interrupt Reservation period 6 5 SCKn cycles d When data length 16 bits operation mode CKP bit 0 DAP bit 1 SCKn I O INTCSIn interrupt Reservation period 14 5 SCKn cycles Remark n 0 1 ...

Page 505: ...etween transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore transfer is interrupted and normal data transfer cannot be performed Figure 10 33 Transfer Request Clear and Register Access Conflict SCKn I O INTCSIn interrupt rq_clr Reg_R W Transfer reservation period Remarks 1 n 0 1 2 rq_clr Internal signal Transfer re...

Page 506: ... 10 34 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 10 34 Interrupt Request and Register Access Conflict SCKn I O INTCSIn interrupt rq_clr Reg_R W Transfer reservation period 0 1 2 3 4 Remarks 1 n 0 1 2 rq_clr Internal signal Transfer request clear signal Reg_R W Internal signal This signal indicates that receive data buffer r...

Page 507: ...output changes 2 SOn pin When the CSIn operation is disabled CSICAEn bit of CSIMn register 0 the SOn pin output status is as follows n 0 1 Table 10 10 SOn Pin Output Status TRMDn DAP AUTO CCL DIRn SOn Pin Output 0 Don t care Don t care Don t care Don t care Fixed to low level 0 Don t care Don t care Don t care SO latch value low level 0 SOTB7 value 0 1 SOTB0 value 0 SOTB15 value 0 1 1 SOTB0 value ...

Page 508: ... The serial clock source is specified by registers CSIC0 and CSIC1 If dedicated baud rate generator output is specified BRG3 is selected as the clock source Since the same serial clock can be shared for transmission and reception baud rate is the same for both transmission and reception Figure 10 35 Block Diagram of Baud Rate Generator 3 BRG3 BGCS1 BGCS0 PRSCM3 Match detector 1 2 CSIn 8 bit timer ...

Page 509: ... signals This register can be read written in 8 bit or 1 bit units Cautions 1 Do not change the value of the BGCS1 BGCS0 bits during a transmission reception operation 2 Set the PRSM3 register prior to setting the CSICAEn bit of the CSIMn register to 1 n 0 1 7 0 PRSM3 6 0 5 0 4 CE 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFF920H After reset 00H Bit position Bit name Function 4 CE Enables baud rate counte...

Page 510: ...ting the CSICAEn bit of the CSIMn register to 1 n 0 1 If the contents of the PRSCM3 register are overwritten when the value of the CSICAEn bit is 1 the cycle of the baud rate signal is not guaranteed 7 PRSCM7 PRSCM3 6 PRSCM6 5 PRSCM5 4 PRSCM4 3 PRSCM3 2 PRSCM2 1 PRSCM1 0 PRSCM0 Address FFFFF922H After reset 00H d Baud rate signal cycle The baud rate signal cycle is calculated as follows When setti...

Page 511: ... 8 500 000 0 0 16 250 000 0 0 40 100 000 0 0 80 50 000 0 0 160 25 000 0 1 200 10 000 1 0 200 5 000 b When fXX 40 MHz BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 2 2 500 000 0 0 5 1 000 000 0 0 10 500 000 0 0 20 250 000 0 0 50 100 000 0 0 100 50 000 0 0 200 25 000 0 1 250 10 000 1 0 250 5 000 Caution Set the transfer clock so that it does not fall below the minimum value of 200 ns of the SCKn cyc...

Page 512: ...iguration A D converters 0 and 1 which employ a successive approximation technique perform A D conversion operations using A D scan mode registers 00 01 10 and 11 ADSCM00 ADSCM01 ADSCM10 and ADSCM11 and registers ADCR0m and ADCR1n m 0 to 5 n 0 to 7 1 Input circuit The input circuit selects an analog input ANI0m or ANI1n according to the mode set in the ADSCM00 or ADSCM10 register and sends it to t...

Page 513: ...g to the mode set by the ADSCMn0 or ADSCMn1 register 8 ANI0m ANI1n pins m 0 to 5 n 0 to 7 The ANI0n and ANI1n pins are the analog input pins of each channel total of 14 channels for two circuits for analog converters 0 and 1 They input analog signals to be A D converted Caution Make sure that the voltages input to ANI0m and ANI1n are within the range of the ratings In particular if a voltage inclu...

Page 514: ...e input pin AVDD0 AVDD1 may give rise to an invalid conversion result m 0 to 5 n 0 to 7 Software processing is needed in order to prevent this invalid conversion result from adversely affecting the system The following are examples of software processing Use the average value of the results of multiple A D conversions as the A D conversion result Perform A D conversion several times consecutively ...

Page 515: ...M01 INTCM004 INTCM005 1 0 1 0 ITRG10 00 01 1X INTCM014 INTCM015 ITRG23 ITRG0 ITRG1 ITRG22 ITRG21 ITRG20 ITRG13 ITRG12 ITRG11 ITRG10 0 0 ITRG41 ITRG40 0 0 ITRG31 ITRG30 Selector Selector Selector Internal bus Selector Selector Trigger Trigger Trigger Trigger A D converter 0 A D converter 1 Selector Caution For the selection of the trigger source in timer trigger mode refer to Table 11 4 Timer Trigg...

Page 516: ...M0n5 is selected using A D internal trigger selection registers 0 and 1 ITRG0 and ITRG1 when the timer trigger mode is set by A D scan mode registers 00 and 10 ADSCM00 and ADSCM10 With the V850E IA2 bit 3 ITRG13 and bit 7 ITRG23 of the ITRG0 register as well as the ITRG1 register have been added 2 Changing analog input to a total of 14 channels for two circuits 3 Multiplexing AVREF0 and AVREF1 wit...

Page 517: ...0 13 0 12 AD MS0 2 ANIS2 3 ANIS3 4 SANI0 5 SANI1 6 SANI2 7 SANI3 8 TRG0 9 TRG1 10 TRG2 11 AD PLM0 15 AD CE0 1 ANIS1 0 ANIS0 14 AD CS1 13 0 12 AD MS1 2 ANIS2 3 ANIS3 4 SANI0 5 SANI1 6 SANI2 7 SANI3 8 TRG0 9 TRG1 10 TRG2 11 AD PLM1 15 AD CE1 1 ANIS1 0 ANIS0 ADSCM00 Address FFFFF200H After reset 0000H ADSCM10 Address FFFFF240H After reset 0000H Bit position Bit name Function 15 ADCEn Specifies enabli...

Page 518: ...rt analog input pin number that is set by bits SANI3 to SANI0 to a smaller pin number than the conversion end analog input pin number that is set by bits ANIS3 to ANIS0 Specifies analog input pin in select mode In scan mode specifies conversion termination analog input pin ANIS3 ANIS2 ANIS1 ANIS0 In select mode In scan mode 0 0 0 0 ANIn0 ANIn0 0 0 0 1 ANIn1 SANI ANIn1 0 0 1 0 ANIn2 SANI ANIn2 0 0 ...

Page 519: ...version operation is suspended and subsequently terminates 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 FR0 9 FR1 10 FR2 11 0 15 0 1 0 0 0 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 FR0 9 FR1 10 FR2 11 0 15 0 1 0 0 0 ADSCM01 Address FFFFF202H After reset 0000H ADSCM11 Address FFFFF242H After reset 0000H Bit position Bit name Function Specifies conversion time Conversion time µs Note FR2 FR1 FR0 Conversi...

Page 520: ... DET CMP9 10 DET ANI0 11 DET ANI1 15 ADET EN0 1 DET CMP1 0 DET CMP0 ADETM0 Address FFFFF244H After reset 0000H 14 ADET LH1 13 DET ANI3 12 DET ANI2 2 DET CMP2 3 DET CMP3 4 DET CMP4 5 DET CMP5 6 DET CMP6 7 DET CMP7 8 DET CMP8 9 DET CMP9 10 DET ANI0 11 DET ANI1 15 ADET EN1 1 DET CMP1 0 DET CMP0 ADETM1 Bit position Bit name Function 15 ADETENn Specifies voltage detection mode 0 Operates in normal mode...

Page 521: ...bits are always read as 0 14 0 13 0 12 0 2 ADCRm2 3 ADCRm3 4 ADCRm4 5 ADCRm5 6 ADCRm6 7 ADCRm7 8 ADCRm8 9 ADCRm9 10 0 11 0 15 0 1 ADCRm1 0 ADCRm0 ADCR0m m 0 to 5 Address See Table 11 1 After reset 0000H ADCR1n n 0 to 7 Address See Table 11 2 After reset 0000H 14 0 13 0 12 0 2 ADCRn2 3 ADCRn3 4 ADCRn4 5 ADCRn5 6 ADCRn6 7 ADCRn7 8 ADCRn8 9 ADCRn9 10 0 11 0 15 0 1 ADCRn1 0 ADCRn0 Table 11 1 Correspon...

Page 522: ...Table 11 3 Correspondence Between Analog Input Pins and ADCR0m and ADCR1n Registers A D Converter Analog Input Pin A D Conversion Result Register ANI00 ADCR00 ANI01 ADCR01 ANI02 ADCR02 ANI03 ADCR03 ANI04 ADCR04 A D converter 0 ANI05 ADCR05 ANI10 ADCR10 ANI11 ADCR11 ANI12 ADCR12 ANI13 ADCR13 ANI14 ADCR14 ANI15 ADCR15 ANI16 ADCR16 A D converter 1 ANI17 ADCR17 ...

Page 523: ...urns integer of value in VIN Analog input voltage AVDD AVDD0 or AVDD1 pin voltage ADCR Value of A D conversion result register ADCR0m or ADCR1n Figure 11 3 illustrates the relationship between the analog input voltages and A D conversion results Figure 11 3 Relationship Between Analog Input Voltages and A D Conversion Results 1 023 1 022 1 021 3 2 1 0 Input voltage AVDDm 1 2 048 1 1 024 3 2 048 2 ...

Page 524: ... written in 8 bit or 1 bit units 7 ITRG23 ITRG0 6 ITRG22 5 ITRG21 4 ITRG20 3 ITRG13 2 ITRG12 1 ITRG11 0 ITRG10 Address FFFFF280H After reset 00H 7 0 ITRG1 6 0 5 ITRG41 4 ITRG40 3 0 2 0 1 ITRG31 0 ITRG30 Address FFFFF288H After reset 00H Bit position Bit name Function 7 to 0 ITRG0 5 4 1 0 ITRG1 ITRG23 to ITRG20 ITRG13 to ITRG10 ITRG0 ITRG41 ITRG40 ITRG31 ITRG30 ITRG1 Specifies timer trigger source ...

Page 525: ... 1 Selects INTCM015 1 0 1 1 Selects INTCM014 INTCM015 1 1 0 0 0 0 0 0 Selects INTCM003 INTTM00 INTCM004 INTCM014 1 1 0 0 0 0 0 1 Selects INTCM013 INTTM00 INTCM004 INTCM014 1 1 0 0 0 0 1 0 Selects INTCM003 INTTM01 INTCM004 INTCM014 1 1 0 0 0 0 1 1 Selects INTCM013 INTTM01 INTCM004 INTCM014 1 1 0 0 0 1 0 0 Selects INTCM003 INTTM00 INTCM005 INTCM014 1 1 0 0 0 1 0 1 Selects INTCM013 INTTM00 INTCM005 I...

Page 526: ...TCM003 INTTM01 INTCM005 INTCM015 1 1 0 1 0 1 1 1 Selects INTCM013 INTTM01 INTCM005 INTCM015 1 1 0 1 1 0 0 Selects INTCM003 INTTM00 INTCM004 INTCM005 INTCM015 1 1 0 1 1 0 1 Selects INTCM013 INTTM00 INTCM004 INTCM005 INTCM015 1 1 0 1 1 1 0 Selects INTCM003 INTTM01 INTCM004 INTCM005 INTCM015 1 1 0 1 1 1 1 Selects INTCM013 INTTM01 INTCM004 INTCM005 INTCM015 1 1 1 0 0 0 0 Selects INTCM003 INTTM00 INTCM...

Page 527: ...rter n 1 1 1 0 1 1 1 Selects INTCM013 INTTM01 INTCM005 INTCM014 INTCM015 1 1 1 1 0 0 Selects INTCM003 INTTM00 INTCM004 INTCM005 INTCM014 INTCM015 1 1 1 1 0 1 Selects INTCM013 INTTM00 INTCM004 INTCM005 INTCM014 INTCM015 1 1 1 1 1 0 Selects INTCM003 INTTM01 INTCM004 INTCM005 INTCM014 INTCM015 1 1 1 1 1 1 Selects INTCM013 INTTM01 INTCM004 INTCM005 INTCM014 INTCM015 Remarks 1 n 0 1 Where n 0 m 1 Where...

Page 528: ...verter A D Conversion End Interrupt Signal 0 Generates INTAD0 1 Generates INTAD1 2 Voltage detection interrupt INTDET0 INTDET1 In the voltage detection mode ADETEN0 or ADETEN1 bit of ADETM0 or ADETM1 1 the value of the ADCR0m or ADCR1n register of the relevant analog input pin is compared with the reference voltage set in the DETCMP9 to DETCMP0 bits of the ADETM0 or ADETM1 register and a voltage d...

Page 529: ... the conversion result in the ADCR0m or ADCR1n register When the specified number of A D conversions have ended generate the A D conversion end interrupt INTAD0 INTAD1 m 0 to 5 n 0 to 7 Notes 1 If the contents of the ADSCM00 or ADSCM10 register are changed during an A D conversion operation the A D conversion operation preceding the change stops and a conversion result is not stored in the ADCR0m ...

Page 530: ...log input set for the ANI0m or ANI1n pin m 0 to 5 n 0 to 7 is a mode in which A D conversion is started by setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 In this mode it is necessary to set the ADCE0 or ADCE1 bit to 1 as an A D conversion restart operation after the INTAD0 or INTAD1 interrupt ADCS0 ADCS1 0 b A D trigger polling mode A D trigger polling mode which starts the...

Page 531: ...log input ANI0m or ANI1n m 0 to 5 n 0 to 7 Figure 11 4 Example of Select Mode Operation Timing ANI01 For A D Converter 0 ANI01 input A D conversion Data 1 ANI01 Data 2 ANI01 Data 3 ANI01 Data 4 ANI01 Data 5 ANI01 Data 6 ANI01 Data 7 ANI01 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI01 Data 2 ANI01 Data 3 ANI01 Data 4 ANI01 Data 6 ANI01 ADCR01 register INTAD0 interrupt Conversion sta...

Page 532: ...rrupt INTAD0 or INTAD1 is generated Figure 11 5 Example of Scan Mode Operation Timing For A D Converter 0 4 Channel Scan ANI00 to ANI03 ANI00 input ANI01 input ANI02 input ANI03 input A D conversion Data 1 ANI00 Data 2 ANI01 Data 3 ANI02 Data 4 ANI03 Data 5 ANI00 Data 6 ANI01 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 ANI00 ADCR00 Data 2 ANI01 ADCR01 Data 3 ANI02 ADCR02 Data 4 ANI03 ADCR03 D...

Page 533: ...pt INTAD0 INTAD1 is generated at the end of each A D conversion which terminates A D conversion ADCS0 ADCS1 bit 0 Analog Input A D Conversion Result Register ANIx ADCRx Remark x 00 to 05 10 to 17 To restart A D conversion write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register This is optimal for an application that reads a result for each A D conversion Figure 11 6 Example of Select ...

Page 534: ...ts of the ADSCM00 or ADSCM10 register Be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to Note 2 2 Set using the ANIS3 to ANIS0 bits of the ADSCM00 or ADSCM10 register Remark x 00 to 05 10 to 17 To restart A D conversion write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register This is optimal for an application that regul...

Page 535: ... INTAD1 is generated at the end of each A D conversion A D conversion operations are repeated until the ADCE0 or ADCE1 bit 0 ADCS0 ADCS1 bit 1 Analog Input A D Conversion Result Register ANIx ADCRx Remark x 00 to 05 10 to 17 In A D trigger polling mode it is not necessary to write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register as an A D conversion restart operationNote This is opti...

Page 536: ...the ADSCM00 or ADSCM10 register Remark x 00 to 05 10 to 17 It is not necessary to write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register as an A D conversion restart operation in A D trigger polling modeNote This is optimal for applications that regularly read A D conversion values Note In A D trigger polling mode the fact that the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 registe...

Page 537: ...sult is stored in the ADCR0m or ADCR1n register corresponding to the analog input m 0 to 5 n 0 to 7 The A D conversion end interrupt INTAD0 or INTAD1 is generated at the end of each A D conversion which terminates A D conversion ADCS0 ADCS1 0 This is optimal for applications that read A D conversion values synchronized to a timer trigger Trigger Analog Input A D Conversion Result Register Interrup...

Page 538: ...version Result Register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANI16 ADCR16 Interrupt specified by ITRG0 ITRG1 register ANI17 ADCR17 Remark n 0 1 After all of the specified A D conversions have ended the A D converter changes to the trigger wait status ADCE0 ADCE1 1 A D conversion is performed again when the interrupt signal specified by the ITRG0 or ITRG1 re...

Page 539: ...g input is A D converted at a time and the result is stored in the ADCR0m or ADCR1n register Analog inputs correspond one to one with A D conversion result registers For each A D conversion an A D conversion end interrupt INTAD0 or INTAD1 is generated which terminates A D conversion ADCS0 ADCS1 bit 0 Trigger Analog Input A D Conversion Result Register ADTRGm signal ANImn ADCRmn Remark m 0 1 n 0 to...

Page 540: ...CRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANI16 ADCR16 ADTRGn signal ANI17 ADCR17 Remark n 0 1 After all specified A D conversions have ended A D conversion is restarted when an external trigger signal occurs This is optimal for applications that regularly monitor multiple analog inputs in synchronization with an external trigger Figure 11 13 Example of Scan Mode External Trigger Scan Operation For A D Conve...

Page 541: ... Operation in standby modes 1 HALT mode A D conversion is suspended If released by NMI or maskable interrupt input the ADSCM00 ADSCM10 ADSCM01 or ADSCM11 register and ADCR0m or ADCR1n register maintain their values m 0 to 5 n 0 to 7 If released by RESET input the ADCR0m and ADCR1n registers are initialized 2 IDLE mode software STOP mode Since clock provision to A D converter 0 or 1 stops A D conve...

Page 542: ...have done so by the time the next conversion result is complete The conversion result read timing is shown in Figures 11 14 and 11 15 below Figure 11 14 Conversion Result Read Timing When Conversion Result Is Undefined A D conversion end A D conversion end ADCRnm INTADn ADCEn Normal conversion result read Normal conversion result Undefined value A D operation stopped Undefined value read Remark n ...

Page 543: ...wing formula regardless of the resolution 1 FSR Max value of analog input voltage that can be converted Min value of analog input voltage that can be converted 100 AVDDn 0 100 AVDDn 100 Remark n 0 1 1LSB is as follows when the resolution is 10 bits 1LSB 1 210 1 1024 0 098 FSR Accuracy has no relation to resolution but is determined by overall error 2 Overall error This shows the maximum error valu...

Page 544: ...ero scale error full scale error integral linearity error and differential linearity error in the characteristics table Figure 11 17 Quantization Error 0 0 1 1 Digital output Quantization error 1 2LSB 1 2LSB Analog input 0 AVDDn n 0 1 4 Zero scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value 1 2 LSB when the digital outp...

Page 545: ...1 Figure 11 19 Full Scale Error 100 011 010 000 0 AVDDn AVDDn 1 AVDDn 2 AVDDn 3 Digital output Lower 3 bits Analog input LSB Full scale error 111 n 0 1 6 Differential linearity error While the ideal width of code output is 1LSB this indicates the difference between the actual measurement value and the ideal value Figure 11 20 Differential Linearity Error 0 AVDDn n 0 1 Digital output Analog input D...

Page 546: ...l scale error are 0 Figure 11 21 Integral Linearity Error 0 AVDDn n 0 1 Digital output Analog input Integral linearity error Ideal line 1 1 0 0 8 Conversion time This expresses the time from when each trigger was generated to the time when the digital output was obtained The sampling time is included in the conversion time in the characteristics table 9 Sampling time This is the time the analog sw...

Page 547: ...nly ports The port configuration is shown below Port DH P00 P05 P10 P12 P20 P27 P30 P34 P40 P42 PDH0 PDH5 PDL0 PDL15 PCT0 PCT1 PCT4 PCT6 PCM0 PCM1 Port DL Port CT Port CM Port 0 Port 1 Port 2 Port 3 Port 4 1 Functions of each port The V850E IA2 has the ports shown below Any port can operate in 8 bit or 1 bit units and can provide a variety of controls Moreover besides its function as a port each h...

Page 548: ...nding bits of port n n 0 to 4 CM CS CT DH and DL 2 Switch to the control mode using the port n mode control register PMCn If 1 above is not performed the contents of port n may be output for a moment when switching from the port mode to the control mode 2 When port manipulation is performed by a bit manipulation instruction SET1 CLR1 or NOT1 perform byte data read for the port and process the data...

Page 549: ...22 TO22 INTP22 P22 input mode P23 TO23 INTP23 P23 input mode P24 TO24 INTP24 P24 input mode PMC2 PFC2 P25 TCLR2 INTP25 P25 input mode P26 TI3 TCLR3 INTP30 P26 input mode PMC2 Port 2 P27 TO3 INTP31 P27 input mode PMC2 PFC2 P30 RXD0 P30 input mode P31 TXD0 P31 input mode P32 RXD1 SI1 P32 input mode P33 TXD1 SO1 P33 input mode Port 3 P34 ASCK1 SCK1 P34 input mode PMC3 P40 SI0 P40 input mode P41 SO0 P...

Page 550: ...er s Manual U15195EJ5V0UD 3 Port block diagrams Figure 12 1 Type A Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Pmn Address Internal bus Selector Selector Selector Remark m Port number n Bit number ...

Page 551: ...r s Manual U15195EJ5V0UD Figure 12 2 Type B Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Noise elimination Edge detection Input signal in control mode Internal bus Selector Selector Remark m Port number n Bit number ...

Page 552: ...FUNCTIONS 552 User s Manual U15195EJ5V0UD Figure 12 3 Type C Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Internal bus Selector Selector Remark m Port number n Bit number ...

Page 553: ...T FUNCTIONS 553 User s Manual U15195EJ5V0UD Figure 12 4 Type D Block Diagram WRPMC Set reset control of PMC Address PMCCM0 PMCM0 PCM0 PCM0 RDIN Input signal in control mode WRPM WRPORT Selector Internal bus Selector ...

Page 554: ...Address Noise elimination Edge detection 1 Input signal in control mode Internal bus Selector Remark m Port number n Bit number Figure 12 6 Type F Block Diagram Internal bus Selector Selector Selector Selector WRPFC WRPMC WRPM WRPORT PFC33 PMC33 PM33 P33 Output signal in control mode RDIN Address P33 ...

Page 555: ...PFC32 PMC32 PM32 P32 Selector Selector Selector RDIN Address Input signal in control modeNote P32 Note The signal level of the input signal is as follows in control mode Input signal in control mode PMC32 bit PMC3 register PFC32 bit PFC3 register RXD1 SI1 0 H L 1 0 Pin level L 1 1 H Pin level H High level L Low level Don t care ...

Page 556: ...l 1 in control mode ASCK1 output enable signal SCK1 output enable signal Output signal 2 in control mode 1 1 1 WRPFC WRPMC WRPM WRPORT Input signal in control modeNote P34 Note The signal level of the input signal is as follows in control mode Input signal in control mode PMC34 bit PMC3 register PFC34 bit PFC3 register ASCK1 SCK1 0 L L 1 0 Pin level L 1 1 L Pin level H High level L Low level Don t...

Page 557: ... Manual U15195EJ5V0UD Figure 12 9 Type I Block Diagram WRPMC WRPM Set reset control of PMC PMCmn PMmn WRPORT Pmn Internal bus Selector Selector Selector Output signal in control mode RDIN Pmn 1 1 Address Remark m Port number n Bit number ...

Page 558: ...er s Manual U15195EJ5V0UD Figure 12 10 Type J Block Diagram WRPMC WRPM WRPORT RDIN PMC42 PM42 P42 P42 Address Input signal in control mode Output signal in control mode SCK0 output enable signal Internal bus Selector Selector Selector ...

Page 559: ...igure 12 11 Type K Block Diagram WRPFC WRPMC WRPM WRPORT RDIN PFCmn PMCmn PMmn Pmn Pmn Address Input signal in control mode Output signal in control mode Internal bus Selector Selector Selector Noise elimination Edge detection Remark m Port number n Bit number ...

Page 560: ...gram Internal bus WRPFC PFC27 WRPMC PMC27 INTP4Note TO3SP WRPM PM27 WRPORT P27 Noise elimination Edge detection Selector Selector Selector Output signal in control mode Input signal in control mode RDIN Address R Q D P27 Note Output signal after an edge on the INTP4 pin has been detected ...

Page 561: ...C PMCmn PSTPOFF BOENx WRPM PMmn WRPORT Pmn BOENx BOENx Selector Selector Selector Selector Output signal in control mode Input signal in control mode RDIN Address Pmn Set reset control of PMC 1 1 1 Remarks 1 m Port number n Bit number 2 x 0 1 3 PSTPOFF Signal in IDLE software STOP mode BOENx A D output signal ...

Page 562: ...14 Type N Block Diagram WRPMC Set reset control of PMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address 1 1 PSTPOFF Output signal in control mode Selector Selector Selector Selector Internal bus Remarks 1 m Port number n Bit number 2 PSTPOFF Signal in IDLE software STOP mode ...

Page 563: ...output stop signal input Although this port is also used as NMI ESO0 INTP0 ESO1 INTP1 ADTRG0 INTP2 ADTRG1 INTP3 and INTP4 TO3OFF these functions cannot be switched with input port functions The status of each pin is read by reading the port 1 Operation in control mode Port Alternate Pin Name Remarks Block Type P00 NMI Non maskable interrupt request input P01 ESO0 INTP0 P02 ESO1 INTP1 Timer counter...

Page 564: ... INTP101 Timer counter input or external interrupt request input B Caution P10 to P12 have hysteresis characteristics when the alternate functions are input but not in the port mode 2 Setting of I O mode and control mode The port 1 mode register PM1 is used to set the I O mode of port 1 and the port 1 mode control register PMC1 and port function control register 1 PFC1 are used to set the operatio...

Page 565: ...mode 1 TCLR10 input mode or external interrupt request INTP101 input mode 1 PMC11 Specifies operation mode of P11 pin 0 I O port mode 1 TCUD10 input mode or external interrupt request INTP100 input mode 0 PMC10 Specifies operation mode of P10 pin 0 I O port mode 1 TIUD10 input mode or TO10 output mode c Port 1 function control register PFC1 This register can be read or written in 8 bit or 1 bit un...

Page 566: ...K P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 Timer counter input or external interrupt request input B Port 2 P27 TO3 INTP31 Timer counter output or external interrupt request input L Caution P20 P21 and P25 to P27 have hysteresis characteristics when the alternate functions are input but not in the port mode 2 Setting of I O mode and control mode The port 2 mode register PM2 is used to set the I O mod...

Page 567: ...t mode 1 TCLR2 input mode or external interrupt request INTP25 input mode 4 to 1 PMC24 to PMC21 Specify operation mode of P24 to P21 pins 0 I O port mode 1 TO24 to TO21 output mode or external interrupt request INTP24 to INTP21 input mode 0 PMC20 Specifies operation mode of P20 pin 0 I O port mode 1 TI2 input mode or external interrupt request INTP20 input mode c Port 2 function control register P...

Page 568: ...34 ASCK1 SCK1 Serial interface UART0 UART1 CSI1 I O H Caution P30 P32 and P34 have hysteresis characteristics when the alternate functions are input but not in the port mode 2 Setting of I O mode and control mode The port 3 mode register PM3 is used to set the I O mode of port 3 and the port 3 mode control register PMC3 and the port 3 function control register PFC3 are used to set the operation in...

Page 569: ...in 0 I O port mode 1 TXD0 output mode 0 PMC30 Specifies operation mode of P30 pin 0 I O port mode 1 RXD0 input mode c Port 3 function control register PFC3 This register can be read or written in 8 bit or 1 bit units Write 0 in bits other than 2 to 4 Caution When port mode is specified by the port 3 mode control register PMC3 the setting of this register is invalid 7 0 PFC3 6 0 5 0 4 PFC34 3 PFC33...

Page 570: ...Undefined Bit position Bit name Function 2 to 0 P4n n 2 to 0 I O port Besides functioning as a port in control mode it also can operate as the serial interface CSI0 I O 1 Operation in control mode Port Alternate Pin Name Remarks Block Type P40 SI0 C P41 SO0 A Port 4 P42 SCK0 Serial interface CSI0 I O J Caution P40 and P42 have hysteresis characteristics when the alternate functions are input but n...

Page 571: ...er reset FFH Bit position Bit name Function 2 to 0 PM4n n 2 to 0 Specifies input output mode of P4n pin 0 Output mode output buffer on 1 Input mode output buffer off b Port 4 mode control register PMC4 This register can be read or written in 8 bit or 1 bit units 7 0 PMC4 6 0 5 0 4 0 3 0 2 PMC42 1 PMC41 0 PMC40 Address FFFFF448H After reset 00H Bit position Bit name Function 2 PMC42 Specifies opera...

Page 572: ...4 3 PDH3 2 PDH2 1 PDH1 0 PDH0 Address FFFFF006H After reset Undefined Bit position Bit name Function 5 to 0 PDHn n 5 to 0 I O port Besides functioning as a port in control mode this can operate as an address bus when memory is expanded externally 1 Operation in control mode Port Alternate Pin Name Remarks Block Type Port DH PDH5 to PDH0 A21 to A16 Memory expansion address bus N ...

Page 573: ... position Bit name Function 5 to 0 PMDHn n 5 to 0 Specifies input output mode of PDHn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port DH mode control register PMCDH This register can be read or written in 8 bit or 1 bit units Caution Set bits 7 and 6 as follows Operation Mode Bit 7 Bit 6 Single chip mode 0 0 ROMless mode 1 1 7 PMCDH7 PMCDH 6 PMCDH6 5 PMCDH5 4 PMCDH4 3 PMCD...

Page 574: ...s 15 PDL15 PDL 14 PDL14 13 PDL13 12 PDL12 11 PDL11 10 PDL10 9 PDL9 8 PDL8 7 PDL7 6 PDL6 5 PDL5 4 PDL4 3 PDL3 2 PDL2 1 PDL1 0 PDL0 Address FFFFF005H After reset Undefined Address FFFFF004H Bit position Bit name Function 15 to 0 PDLn n 15 to 0 I O port Besides functioning as a port in control mode this can operate as an address data bus when memory is expanded externally 1 Operation in control mode ...

Page 575: ...025H After reset FFFFH Address FFFFF024H Bit position Bit name Function 15 to 0 PMDLn n 15 to 0 Specifies input output mode of PDLn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port DL mode control register PMCDL The PMCDL register can be read or written in 16 bit units When using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCD...

Page 576: ...00AH After reset Undefined Bit position Bit name Function 6 4 1 0 PCTn n 6 4 1 0 I O port Besides functioning as a port in control mode this can operate as control signal outputs when memory is expanded externally 1 Operation in control mode Port Alternate Pin Name Remarks Block Type PCT0 LWR PCT1 UWR Write strobe signal output PCT4 RD Read strobe signal output Port CT PCT6 ASTB Address strobe sig...

Page 577: ...ecifies input output mode of PCTn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port CT mode control register PMCCT This register can be read or written in 8 bit or 1 bit units 7 0 PMCCT 6 PMCCT6 5 0 4 PMCCT4 3 0 2 0 1 PMCCT1 0 PMCCT0 Address FFFFF04AH After resetNote 00H 53H Note 00H Single chip mode 53H ROMless mode Bit position Bit name Function 6 PMCCT6 Specifies operatio...

Page 578: ...e wait insertion signal input and internal system clock output 1 Operation in control mode Port Alternate Pin Name Remarks Block Type PCM0 WAIT Note Wait insertion signal input D Port CM PCM1 CLKOUT Internal system clock output I Note In the ROMless mode the default operation mode of the PCM0 pin is the WAIT input mode When unused fix the pin to the inactive level When used as a port this pin func...

Page 579: ...FFF02CH After reset FFH Bit position Bit name Function 1 0 PMCMn n 1 0 Specifies input output mode of PCMn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port CM mode control register PMCCM This register can be read or written in 8 bit or 1 bit units 7 0 PMCCM 6 0 5 0 4 0 3 0 2 0 1 PMCCM1 0 PMCCM0 Address FFFFF04CH After resetNote 00H 03H Note 00H Single chip mode 03H ROMless ...

Page 580: ...pulates 1 bit but accesses a port in 8 bit units If this instruction is executed to manipulate a port with a mixture of input and output bits the contents of the output latch of a pin set in the input mode in addition to the bit to be manipulated are overwritten to the current input pin status and become undefined 12 4 2 Reading from I O port 1 In output mode The contents of the output latch Pn ca...

Page 581: ... valid only in control mode 12 5 2 Timer 10 timer 3 input pins Noise filtering using the clock sampling shown below is added to the pins that operate as valid edge inputs to timer 10 and timer 3 A signal input that changes in less than these elimination times is not accepted internally Pin Noise Elimination Time Sampling Clock Timer 10 P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 Select f...

Page 582: ... 2 3 rising edge detection Timers 1 2 3 falling edge detection 2 clocks 2 clocks 5 clocks 5 clocks 4 clocks 4 clocks 3 clocks 3 clocks Caution If there are three or less noise elimination clocks while the timer 1 or 3 input signal is high level or low level the input pulse is eliminated as noise If it is sampled at least four times the edge is detected as valid input ...

Page 583: ...unction starts operating by setting the TM1CE0 bit of the TMC10 register to 1 enabling count operations 7 0 NRC10 6 0 5 0 4 0 3 0 2 0 1 NRC101 0 NRC100 Address FFFFF5F8H After reset 00H Bit position Bit name Function Selects the TIUD10 TO10 TCUD10 INTP100 and TCLR10 INTP101 pin noise elimination clocks NRC101 NRC100 Noise elimination clocks 0 0 fXXTM10 8 0 1 fXXTM10 4 1 0 fXXTM10 2 1 1 fXXTM10 1 0...

Page 584: ...nabling count operations 7 0 NRC3 6 0 5 0 4 0 3 NRC33 2 NRC32 1 NRC31 0 NRC30 Address FFFFF698H After reset 00H Bit position Bit name Function Selects the TO3 INTP31 pin noise elimination clock NRC33 NRC32 Noise elimination clock 0 0 fXXTM3 256 0 1 fXXTM3 128 1 0 fXXTM3 64 1 1 fXXTM3 32 3 2 NRC33 NRC32 Remark fXXTM3 Clock of TM3 selected by PRM03 register Selects the TI3 INTP30 TCLR3 pin noise eli...

Page 585: ...n Analog Filter Noise Elimination Time Noise Elimination Time Sampling Clock P20 TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 10 to 100 ns 4 to 5 clocks fXXTM2 Cautions 1 Since digital filtering uses clock sampling if it is selected input signals are not received when the CPU clock is stopped 2 The noise eliminator is valid only in control mode 3 Refer to Figure 12 15 for an exam...

Page 586: ... to 5 3 The noise elimination function starts operating by setting the CEEn bit of the TCRE0 register to 1 enabling count operations 1 2 7 DFEN00 FEM0 6 0 5 0 4 0 3 EDGE010 2 EDGE000 1 TMS010 0 TMS000 Address FFFFF630H After reset 00H Address FFFFF631H After reset 00H Address FFFFF632H After reset 00H Address FFFFF633H After reset 00H Address FFFFF634H After reset 00H Address FFFFF635H After reset...

Page 587: ... noise eliminator specification 1 0 Capture to subchannel 1 according to timer 1 1 Capture to subchannel 2 according to timer 1 0 TMS01n TMS00n Note Capture input according to INTCM100 and INTCM101 can be selected only for the FEM1 and FEM2 registers Set the values of the TMS01m and TMS00m bits in the FEMm register to 00B or 01B Settings other than these are prohibited m 1 3 to 5 Capture according...

Page 588: ... FUNCTIONS 588 User s Manual U15195EJ5V0UD 12 6 Cautions 12 6 1 Hysteresis characteristics The following ports do not have hysteresis characteristics in the port mode P10 to P12 P20 P21 P25 to P27 P30 P32 P34 P40 P42 ...

Page 589: ...gh impedance Similarly perform pin processing so that on chip peripheral I O function signal outputs and output ports are not affected Note In ROMless mode CLKOUT signals are also output during a reset period In single chip mode CLKOUT signals are not output until the PMCCM register is set Table 13 1 shows the operation status of each pin during a reset period Table 13 1 Operation Status of Each P...

Page 590: ...iod of at least 4 system clocks after the timing of a reset release by the RESET pin 2 Reset at power on 1 Reset circuit RESET 5 V 5 V 5 V 5 V reset generator Regulator control REGRES5 Pin high impedance control RES5 Internal circuit control RES3 3 3 V reset generator 3 3 V 3 3 V Note Note Apply 5 V initially If 5 V is not applied initially this level cannot be determined and a reset will not occu...

Page 591: ...plied When supplying the two power supplies from external supplies with the regulator turned off be sure to supply 5 V system power first 2 The V850E IA2 is internally reset after 3 3 V system power has been supplied During the regulator output stabilization time the internal circuits may not be reset when only 5 V system power is being supplied Consequently the pins may output undefined levels Fo...

Page 592: ... 0 Output buffer off 1 Output buffer on at 3 3 V system reset VDD VDD Pin to be controlled Level shifter c Internal reset of 5 V system 3 3 V system power supply i Operation on turning ON OFF power VDD 5 V system REGIN 3 3 V system RESET input Internal RES5 5 V system Internal RES3 3 3 V system Pin to be controlled Analog delay High impedance Pin manipulation instruction Low level because power is...

Page 593: ...T input Internal RES5 5 V system Internal RES3 3 3 V system Pin to be controlled High impedance Operates Operates Pin manipulation instruction Note 1 Note 1 Note 2 Note 1 H H Notes 1 Analog delay 2 The internal system reset signal stays active for at least 4 system clocks after the reset status caused by the RESET pin is released ...

Page 594: ... 0 1 2C11H Bus size configuration register BSC 5555H Bus control function System wait control register VSWC 77H Bus cycle type configuration register n BCTn n 0 1 CCCCH Data wait control register n DWCn n 0 1 3333H Address wait control register AWC 0000H Memory control function Bus cycle control register BCC AAAAH DMA source address register nL DSAnL n 0 to 3 Undefined DMA source address register ...

Page 595: ...egister PHS 00H Dead time timer reload register n DTRRn n 0 1 0FFFH Buffer registers CM0n CM1n BFCM0n BFCM1n n 0 to 5 FFFFH Timer control register 0n TMC0n n 0 1 0508H Timer control register 0nL TMC0nL n 0 1 08H Timer control register 0nH TMC0nH n 0 1 05H Timer unit control register 0n TUC0n n 0 1 01H Timer output mode register n TOMRn n 0 1 00H PWM software timing output register n PSTOn n 0 1 00...

Page 596: ... output control register 0H OCTLE0H 00H Timer 2 subchannels 0 and 5 capture compare control register CMSE050 0000H Timer 2 subchannels 1 and 2 capture compare control register CMSE120 0000H Timer 2 subchannels 3 and 4 capture compare control register CMSE340 0000H Timer 2 subchannel n secondary capture compare register CVSEn0 n 0 to 4 0000H Timer 2 subchannel n main capture compare register CVPEn0...

Page 597: ...buffer register Ln SIRBELn n 0 1 00H Clocked serial interface first stage transmit buffer register n SOTBFn n 0 1 0000H Clocked serial interface first stage transmit buffer register Ln SOTBFLn n 0 1 00H Serial I O shift register n SIOn n 0 1 0000H Serial I O shift register Ln SIOLn n 0 1 00H Prescaler mode register 3 PRSM3 00H Serial interface function CSI0 CSI1 Prescaler compare register 3 PRSCM3...

Page 598: ... trigger selection register n ITRGn n 0 1 00H Ports P0 to P4 PDH PCT PCM Undefined Port PDL Undefined Port PDLL Undefined Port PDLH Undefined Mode registers PM1 to PM4 PMDH PMCT PMCM FFH Mode register PMDL FFFFH Mode register PMDLL FFH Mode register PMDLH FFH Mode control registers PMC1 to PMC4 00H Mode control registers PMCDH 00H FFH Mode control register PMCDL 0000H FFFFH Mode control register P...

Page 599: ...e power supply system To use this regulator connect an N ch transistor 2SD1950 VL standard product surface mount type or 2SD1581 independent type is recommended to the REGOUT pin and the REGIN pin to CVSS via a capacitor for stabilizing the regulator output refer to 14 3 Connection Example If two power supplies 5 V system for the peripheral interface and 3 3 V system for the internal CPU are avail...

Page 600: ...e 2SD1950 VL standard product when using a glass epoxy board are shown below Figure 14 1 Example of Connection When Using N ch Transistor RVDD VDD 4 5 to 5 5 V REGOUT N ch transistor 22 F recommended REGOFF generator REGIN 3 3 V Internal circuit Regulator V850E IA2 R CVSS µ Remark The 2SD1950 VL standard product surface mount type or 2SD1581 independent type is recommended as the N ch transistor 1...

Page 601: ...2 When using an external regulator When an on chip regulator is not used an external regulator can be used An example of connection when using an external regulator application is shown below Figure 14 3 Connection When Using External Regulator RVDD VDD REGOUT Open REGIN V850E IA2 CVSS 3 3 V regulator 5 V regulator Power supply Remark Connect a capacitor or inductance to the regulator I O as requi...

Page 602: ...open REGIN pin Supply 3 3 V 3 0 to 3 6 V to this pin 3 Also make sure that the pins are set as follows when the REGC0 bit 0 regulator operating for details of the connection method refer to 14 3 Connection Example REGOUT pin Connect this pin to the base of the external transistor REGIN pin Connect this pin to the emitter of the external transistor and to an electrolytic capacitor Connect a bias re...

Page 603: ... the V850E IA2 is solder mounted on the target system Small scale production of various models is made easier by differentiating software Data adjustment in starting mass production is made easier 15 1 Features All area batch erase Communication via serial interface from the dedicated flash programmer Erase write voltage VPP 7 8 V On board programming 15 2 Writing Using Flash Programmer Writing ca...

Page 604: ...VPP 62 RESERVE HS A16 PDH0 Note 2 56 VDD 39 64 86 VDD 39 64 86 AVDD0 94 AVDD0 94 AVDD1 2 AVDD1 2 MODE0 12 MODE0 12 VDD Note 3 RVDD 14 RVDD 14 VSS3 13 63 VSS3 13 63 VSS 38 87 VSS 38 87 AVSS0 95 AVSS0 95 CVSS 20 CVSS 20 AVSS1 3 AVSS1 3 GND Note 3 NMI P00 74 NMI P00 74 Note 4 CKSEL 21 CKSEL 21 Notes 1 The clock amplitude of X1 and X2 is 3 3 V Configure the oscillator on the FA 100GC 8EU board using a...

Page 605: ...VPP 64 RESERVE HS A16 PDH0 Note 2 58 VDD 41 66 88 VDD 41 66 88 AVDD0 96 AVDD0 96 AVDD1 4 AVDD1 4 MODE0 14 MODE0 14 VDD Note 3 RVDD 16 RVDD 16 VSS3 15 65 VSS3 15 65 VSS 40 89 VSS 40 89 AVSS0 97 AVSS0 97 CVSS 22 CVSS 22 AVSS1 5 AVSS1 5 GND Note 3 NMI P00 76 NMI P00 76 Note 4 CKSEL 23 CKSEL 23 Notes 1 The clock amplitude of X1 and X2 is 3 3 V Configure the oscillator on the FA 100GF 3BA board using a...

Page 606: ...uired for controlling the dedicated flash programmer UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850E IA2 to perform writing erasing etc A dedicated program adapter FA series and dual power supply adapter FA TVC are required for off board writing 15 4 Communication Mode 1 UART0 Transfer rate 4 800 bps to 76 800 bps LSB first Figure 15 2 Communication wit...

Page 607: ...perating clock amplitude of the V850E IA2 is 3 3 V The dedicated flash programmer outputs transfer clocks and the V850E IA2 operates as a slave 3 Handshake supported CSI communication Transfer rate up to 2 MHz MSB first Figure 15 4 Communication with Dedicated Flash Programmer Handshake Supported CSI Communication V850E IA2 Dedicated flash programmer VPP1 VPP RESET RESET SO SI SO0 SI0 PDH0 SCK SCK...

Page 608: ...7 8 V writing voltage is supplied to the MODE1 VPP pin The following shows an example of the connection of the MODE1 VPP pin Figure 15 5 Connection Example of MODE1 VPP Pin V850E IA2 MODE1 VPP Pull down resistor RVPP 5 to 50 kΩ Dedicated flash programmer connection pin 15 5 2 Serial interface pin The following shows the pins used by each serial interface Table 15 3 Pins Used by Each Serial Interfa...

Page 609: ... output connected to another device input the signal output to the other device may cause the device to malfunction To avoid this isolate the connection to the other device or make the setting so that the input signal to the other device is ignored Figure 15 7 Malfunction of Other Device V850E IA2 Output pin Input pin Other device Dedicated flash programmer connection pin In the flash memory progr...

Page 610: ...the signals on the reset signal generator side 15 5 4 NMI pin Do not change the input signal to the NMI pin in flash memory programming mode If it is changed in flash memory programming mode programming may not be performed correctly 15 5 5 MODE0 MODE1 pins To shift to the flash memory programming mode set MODE0 to high level apply the writing voltage 7 8 V to the MODE1 VPP pin and release reset 1...

Page 611: ...ng Method 15 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Figure 15 9 Flash Memory Manipulating Procedure Start Switch to flash memory programming mode Supply RESET pulse Select communication mode Manipulate flash memory End End No Yes ...

Page 612: ...Mode n 1 Flash memory programming mode 7 8 V MODE1 VPP 3 3 V 0 V RESET 2 15 6 3 Selection of communication mode In the V850E IA2 a communication mode is selected by inputting pulses 16 pulses max to VPP pin after switching to the flash memory programming mode The VPP pulse is generated by the dedicated flash programmer The following shows the relationship between the number of pulses and the commu...

Page 613: ...fy command Compares the contents of the specified area and the input data Batch erase command Erases the contents of the entire memory Area erase command Erases the contents of the specified area Erase Write back command Writes back the contents which were erased Batch blank check command Checks the erase state of the entire memory Blank check Area blank check command Checks the erase state of the...

Page 614: ...elf programming Self programming implements erasure and writing of the flash memory by calling the self programming function device s internal processing on the program placed in the block 0 space 000000H to 1FFFFFH and areas other than internal ROM area To place the program in the block 0 space and internal ROM area copy the program to areas other than 000000H to 1FFFFFH e g internal RAM area and...

Page 615: ...y area in which an over erase occurred Acquire information Flash memory information read Reads out information about flash memory 15 7 3 Outline of self programming interface To execute self programming using the self programming interface the environmental conditions of the hardware and software for manipulating the flash memory must be satisfied It is assumed that the self programming interface ...

Page 616: ...y a high voltage must be applied to the VPP pin To execute self programming a circuit that can generate a write voltage VPP and that can be controlled by software is necessary on the application system An example of a circuit that can select a voltage to be applied to the VPP pin by manipulating a port is shown below Figure 15 14 Example of Self Programming Circuit Configuration VDD 3 3 V 0 3 V PD...

Page 617: ...memory starts until manipulation is complete Cautions 1 Apply 0 V to the VPP pin when reset is released 2 Implement self programming in single chip mode 0 or 1 3 Apply the voltage to the VPP pin in the entry program 4 If both writing and erasing are executed by using the self programming function and flash memory programmer on the target board be sure to communicate with the programmer using CSI0 ...

Page 618: ...imer while the flash memory is being manipulated Because the internal timer is initialized after the flash memory has been used initialize the timer with the application program to use the timer again Stopping reset signal input Do not input the reset signal while the flash memory is being manipulated If the reset signal is input while the flash memory is being manipulated the contents of the flas...

Page 619: ...unction numbers are used as parameters when the device internal processing is called Table 15 9 Self Programming Function Number Function No Function Name 0 Acquiring flash information 1 Erasing area 2 to 4 RFU 5 Area write back 6 to 8 RFU 9 Erase byte verify 10 Erase verify 11 to 15 RFU 16 Continuous write in word units 17 to 19 RFU 20 Pre write 21 Internal verify Other Prohibited Remark RFU Rese...

Page 620: ...ify start address Number of bytes to be verified 0 Normal completion Other than 0 Error Erase verify 10 None acts on erase manipulation area immediately before 0 Normal completion Other than 0 Error Continuous write in word units Note 2 16 Write start address Note 3 Start address of write source data Note 3 Number of words to be written word units 0 Normal completion Other than 0 Error Pre write 2...

Page 621: ...ple If write back time is 1 ms 1 1 000 100 10 integer operation ep 0x10 2 bytes Input Timer set value for creating internal operation unit time unsigned 2 bytes Write a set value that makes the value of timer 4 the internal operation unit time 100 µs Set value Operating frequency Hz 1 000 000 Internal operation unit time µs Timer division ratio 4 1 Note 4 Example If the operating frequency is 40 M...

Page 622: ...ation For the flash information acquisition function function No 0 the option number r7 to be specified and the contents of the return value r10 are as follows To acquire all flash information call the function as many times as required in accordance with the format shown below Table 15 13 Flash Information Option No r7 Return Value r10 0 Specification prohibited 1 Specification prohibited 2 Bit r...

Page 623: ...a number The area numbers and memory map of the µPD70F3114 are shown below Figure 15 16 Area Configuration Area 1 64 KB Area 0 64 KB 0 x 1 F F F F End address of area 1 0 x 0 0 0 0 0 Start address of area 0 0 x 1 0 0 0 0 Start address of area 1 0 x 0 F F F F End address of area 0 ...

Page 624: ...s disables writing erasing on chip flash memory When this bit is 1 writing erasing on chip flash memory is disabled even if a high voltage is applied to the VPP pin 0 Enables writing erasing flash memory 1 Disables writing erasing flash memory 2 VPP Indicates the voltage applied to the VPP pin reaches the writing enabled level read only This bit is used to check whether writing is possible or not ...

Page 625: ...FLPMC r0 5 NOP 6 NOP 7 NOP 8 NOP 9 NOP 10 LDSR rY 5 Remark rX Value written to the PSW rY Value returned to the PSW No special sequence is required for reading a specific register Cautions 1 If an interrupt is acknowledged between when PHCMD is issued 3 and writing to a specific register 4 immediately after issuing PHCMD writing to the specific register may not be performed and a protection error ...

Page 626: ...flash memory FLSPM bit 0 to select normal operation mode 7 Wait for the internal manipulation setup time see 15 7 13 5 Internal manipulation setup parameter 1 Parameter r6 First argument sets a self programming function number r7 Second argument r8 Third argument r9 Fourth argument ep First address of RAM parameter 2 Return value r10 Return value return value from device internal processing of 4 b...

Page 627: ...nipulation setup parameter EntryProgram add 4 sp Prepare st w lp 0 sp Save return address movea lo 0x00a0 r0 r10 ldsr r10 5 PSW NP ID mov lo 0x0002 r10 st b r10 PHCMD r0 PHCMD 2 st b r10 FLPMC r0 VPPDIS 0 FLSPM 1 nop nop nop nop nop movea lo 0x0020 r0 r10 ldsr r10 5 PSW ID trap 0x1f Device Internal Process movea lo 0x00a0 r0 r6 ldsr r6 5 PSW NP ID mov lo 0x08 r6 st b r6 PHCMD r0 PHCMD 8 st b r6 FL...

Page 628: ...ash memory In the program example in 4 above the elapse of this wait time is ensured by setting ISETUP to 104 40 MHz operation The total number of execution clocks in this example is 39 clocks divh instruction 35 clocks add instruction 1 clock jne instruction 3 clocks Ensure that a wait time of 100 µs elapses by using the following expression 39 clocks total number of execution clocks 25 ns 40 MHz...

Page 629: ...Set RAM parameter Mask interrupts Pre write Erase area Erase byte verify Erase verify Area write back Erase verify Clear number of times write back is repeated Erase byte verify Write error Undererase Maximum number of times of repeating erasure is exceeded Maximum number of times of repeating write back is exceeded Overerase Overerase Undererase Set VPP voltage Clear VPP voltage Unmask interrupts...

Page 630: ...e data in word units is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 15 18 Continuous Writing Flow Function No 16 Yes No Continuous writing Mask interrupts Set VPP voltage Continuous writing Error Clear VPP voltage Unmask interrupts Write error Clear VPP voltage Unmask interrupts Normal completion Set RAM parame...

Page 631: ...e processing of each function number must be executed in accordance with the specified calling procedure Figure 15 19 Internal Verify Flow Function No 21 Yes No Internal verify Mask interrupts Set VPP voltage Internal verify Error Clear VPP voltage Unmask interrupts Internal verify error Clear VPP voltage Unmask interrupts Normal completion Set RAM parameter ...

Page 632: ...information is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 15 20 Acquiring Flash Information Flow Function No 0 Acquiring flash information Mask interrupts Set VPP voltage Acquiring flash information Clear VPP voltage Unmask interrupts End Set RAM parameter ...

Page 633: ...module is located in area 0 and the data in area 1 is rewritten or erased The rewriting module is a user program to rewrite the flash memory The other areas can be also rewritten by using the flash functions included in this self programming library The flash functions expand the entry program in the external memory or internal RAM and call the device internal processing When using the self progra...

Page 634: ... the self programming library is outlined below Figure 15 22 Outline of Self Programming Library Configuration Application program Entry program RAM parameter Device internal processing Flash memory Self programming interface Self programming library Flash memory manipulation C interface ...

Page 635: ...OP 8 NOP 9 LDSR rY 5 10 TST1 3 FLPMC r0 BNZ Start address of self programming routine BR Routine when writing is not performed Remark rX Value written to the PSW rY Value returned to the PSW Cautions 1 If an interrupt is acknowledged between when PHCMD is issued 2 and writing to a specific register 3 immediately after issuing PHCMD writing to a specific register may not be performed and a protecti...

Page 636: ...pins 0 5 to VDD 0 5 Note 1 V Input voltage VI2 VPP pin µPD70F3114 only Note 2 0 5 to 8 5 V Clock input voltage VK X1 pin 0 5 to REGIN 1 0 Note 1 V AVDD VDD 0 5 to VDD 0 5 Note 1 V Analog input voltage VIAN ANI00 to ANI05 pins ANI10 to ANI17 pins VDD AVDD 0 5 to AVDD 0 5 Note 1 V Per pin for the TO000 to TO005 and TO010 to TO015 pins 20 mA Per pin other than for the TO000 to TO005 and TO010 to TO01...

Page 637: ...ut pins can be set to the high impedance state and the output timing of the external circuit is designed to avoid output conflict 2 Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used unde...

Page 638: ...d to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation b External clock input Open External clock High speed CMOS inverter X2 X1 Cautions 1 Connect the high speed CMOS inverter as close to the X1 pin as possible 2 Thoroughly evaluate the matching between the V850E IA2 and the high speed CMOS inverter 3 When an internal regulator is used the external c...

Page 639: ...CSTCR6M00G55 R0 6 0 On chip On chip 0 3 0 3 6 Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer If optimization of oscillator characteristics is necessary in the actual application apply to the resonator manufacturer for evaluation on the implementation circuit The oscillation voltage and oscillation frequency indic...

Page 640: ...akage current low ILIL VI 0 V 10 µA Output leakage current high ILOH VO VDD 10 µA Output leakage current low ILOL VO 0 V 10 µA Analog pin input leakage current ILIAN ANI00 to ANI05 ANI10 to ANI17 pins 10 µA Note 5 µPD703114 1 8fXX 15 3 0fXX 30 mA REGIN Note 5 µPD70F3114 2 0fXX 15 3 2fXX 30 mA During normal operation IDD1 VDD RVDD Note 6 30 45 mA REGIN Note 5 0 8fXX 10 1 2fXX 15 mA In HALT mode IDD...

Page 641: ...DR V Data retention input voltage low VILDR Note 2 0 0 2HVDDDR V Notes 1 The current of the TO000 to TO005 and TO010 to TO015 pins is not included 2 P00 NMI P01 ESO0 INTP0 P02 ESO1 INTP1 P03 ADTRG0 INTP2 P04 ADTRG1 INTP3 P05 INTP4 TO3OFF P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P20 TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 P27 TO3 INTP31 P30 R...

Page 642: ...nd d below VDD 0 V 0 8 VDD 0 2 VDD 0 8 VDD 0 2 VDD Test points b P31 TXD0 P33 SO1 TXD1 P41 SO0 VDD 0 V 0 7 VDD 0 3 VDD 0 7 VDD 0 3 VDD Test points c AD0 PDL0 to AD15 PDL15 A16 PDH0 to A21 PDH5 LWR PCT0 UWR PCT1 RD PCT4 ASTB PCT6 WAIT PCM0 CLKOUT PCM1 VDD 0 V 2 2 V 0 8 V 2 2 V 0 8 V Test points d X1 REGIN 0 V 0 8 REGIN 0 15 REGIN 0 8 REGIN 0 15 REGIN Test points AC test output test points VDD 0 V 0...

Page 643: ...ual U15195EJ5V0UD Load condition DUT Device under test CL 50 pF Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration insert a buffer or other element to reduce the device s load capacitance to 50 pF or lower ...

Page 644: ...ut rise time tXR 4 PLL mode 10 ns Direct mode 4 ns X1 input fall time tXF 5 PLL mode 10 ns 4 40 MHz CPU operation frequency fXX CLKOUT signal used Note 4 32 MHz 25 250 ns CLKOUT output cycle tCYK 6 CLKOUT signal used Note 31 25 250 ns CLKOUT high level width tWKH 7 0 5T 9 ns CLKOUT low level width tWKL 8 0 5T 11 ns CLKOUT rise time tKR 9 11 ns CLKOUT fall time tKF 10 9 ns Delay time from X1 to CLK...

Page 645: ...ator output stabilization time TA 40 to 85 C REGIN 3 0 to 3 6 V VDD RVDD 5 0 V 0 5 V VSS3 VSS CVSS 0 V Parameter Symbol Conditions MIN MAX Unit Regulator output stabilization time tRG 14 External NPN transistor 2SD1950 VL compliant product or 2SD1581 Stabilization capacitance C 22 µF electrolytic capacitor Bias resistance between B and E R 110 kΩ 2 ms Caution The regulator output stabilization tim...

Page 646: ...vel width tWRSH 15 500 ns At power on 500 TOS tRG ns At STOP mode release Note 500 TOS ns RESET pin low level width tWRSL 16 Other than at power on and at STOP mode release 500 ns Note Release the STOP mode in the range of REGIN 3 0 to 3 6 V VDD RVDD 5 0 V 0 5 V Caution Thoroughly evaluate the oscillation stabilization time Remark TOS Oscillation stabilization time tRG Regulator output stabilizati...

Page 647: ...STB high level width tWSTH 28 1 wAS T 15 ns Data output time from LWR UWR tDWROD 29 10 ns Data output setup time to LWR UWR tSODWR 30 1 w T 25 ns Data output hold time from LWR UWR tHWROD 31 T 20 ns tSAWT1 32 w 1 1 5 wAS wAH T 40 ns WAIT data output hold time to address tSAWT2 33 1 5 w wAS wAH T 40 ns tHAWT1 34 w 1 0 5 w wAS wAH T ns WAIT hold time from address tHAWT2 35 1 5 w wAS wAH T ns tSSTWT1...

Page 648: ...UT to address float tFKA 41 12 15 ns Delay time from CLKOUT to ASTB tDKST 42 3 wAHT 19 wAHT ns Delay time from CLKOUT to RD LWR UWR tDKRDWR 43 5 19 ns Data input setup time to CLKOUT tSIDK 44 21 ns Data input hold time from CLKOUT tHKID 45 5 ns Delay time from CLKOUT to data output tDKOD 46 19 ns WAIT setup time to CLKOUT tSWTK 47 21 ns WAIT hold time from CLKOUT tHKWT 48 5 ns Remarks 1 T tCYK 2 w...

Page 649: ...put RD output AD0 to AD15 I O ASTB output WAIT input T1 T2 TW T3 Address Hi Z 40 20 41 42 17 28 43 22 36 38 37 39 32 34 33 35 47 47 48 21 27 19 18 44 45 42 23 43 24 26 25 48 Data Caution When using the CLKOUT signal for interfacing with external devices set the internal system clock frequency fXX to 32 MHz or lower Remark LWR and UWR are high level ...

Page 650: ...to AD15 I O ASTB output LWR output UWR output A16 to A21 output WAIT input T1 T2 TW T3 Data Address 40 46 42 17 18 28 42 43 22 36 47 38 37 39 32 34 33 35 48 47 48 29 30 27 43 25 31 Caution When using the CLKOUT signal for interfacing with external devices set the internal system clock frequency fXX to 32 MHz or lower Remark RD is high level ...

Page 651: ... filter specified 5T 10 ns Remark T Digital filter sampling clock T can be selected by setting the following registers INTP100 INTP101 Can be selected from fXX 2 fXX 4 fXX 8 and fXX 16 by setting the NRC101 and NRC100 bits of the timer 10 noise elimination time select register NRC10 fXX Internal system clock INTP30 Can be selected from fXXTM3 2 fXXTM3 4 fXXTM3 8 and fXXTM3 16 by setting the NRC31 ...

Page 652: ...ng the CESE1 and CESE0 bits of timer 2 count clock control edge selection register 0 CSE0 to 1 and 0 respectively Remarks 1 T Digital filter sampling clock T can be selected by setting the following registers TIUD10 TCUD10 TCLR10 Can be selected from fXX 2 fXX 4 fXX 8 and fXX 16 by setting the NRC101 and NRC100 bits of the timer 10 noise elimination time select register NRC10 TCLR2 TI2 Fixed to fX...

Page 653: ...cy 9 CSI timing 1 2 a Master mode TA 40 to 85 C REGIN 3 0 to 3 6 V VDD RVDD 5 0 V 0 5 V VSS3 VSS CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit SCKn cycle tCYSK1 57 Output 200 ns SCKn high level width tWSK1H 58 Output 0 5tCYSK1 25 ns SCKn low level width tWSK1L 59 Output 0 5tCYSK1 25 ns SIn setup time to SCKn tSSISK 60 35 ns SIn hold time from SCKn tHSKSI 61...

Page 654: ... 3 0 to 3 6 V VDD RVDD 5 0 V 0 5 V VSS3 VSS CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit UART0 baud rate generator input frequency fBRG 20 MHz Remarks 1 UART0 baud rate generator input frequency fBRG Can be selected from fXX fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1024 and fXX 2048 by setting the TPS3 to TPS0 bits of clock select...

Page 655: ...T 10 ns TXD1 output hold time from ASCK1 tHSKTX 70 k 1 T 20 ns Remarks 1 T 2tCYK 2 k Setting value of prescaler compare register 1 PRSCM1 of UART1 b Clocked slave mode TA 40 to 85 C REGIN 3 0 to 3 6 V VDD RVDD 5 0 V 0 5 V VSS3 VSS CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit ASCK1 cycle tCYSK0 64 Input 1000 ns ASCK1 high level width tWSK0H 65 Input 4T 80 n...

Page 656: ...CHAPTER 16 ELECTRICAL SPECIFICATIONS 656 User s Manual U15195EJ5V0UD 11 UART1 timing 2 2 64 66 65 67 68 69 70 RXD1 input TXD1 output ASCK1 I O Output data Input data ...

Page 657: ...2 LSB Conversion time tCONV 5 10 µs Sampling time tSAMP 833 ns Zero scale error Note 1 4 LSB Full scale error Note 1 4 LSB Differential linearity error Note 1 4 LSB Integral linearity error Note 1 4 LSB Analog input voltage VIAN 0 3 AVDD 0 3 V Analog reference voltage AVDD 4 5 5 5 V AVDD power supply current Note 2 AIDD 4 8 mA Notes 1 Quantization error 0 5 LSB is not included 2 The V850E IA2 inco...

Page 658: ...5 18 20 22 µs Overall writing time per word tWTW When the step writing time 20 µs 1 word 4 bytes Note 6 20 200 µs word Number of rewrites CERWR 1 erase 1 write after erase 1 rewrite Note 7 100 Count Notes 1 The recommended setting value of the step erase time is 0 4 s 2 The prewrite time prior to erasure and the erase verify time write back time are not included 3 The recommended setting value of ...

Page 659: ...o RESET set time 72 tPSRRF 1 µs RESET to VPP count start time 73 tRFOF VPP 7 8 V 10T 1500 ns Count execution time 74 tCOUNT 15 ms VPP counter high level width 75 tCH 1 µs VPP counter low level width 76 tCL 1 µs VPP counter rise time 77 tR 1 µs VPP counter fall time 78 tF 1 µs VPP to REGIN reset time 79 tPFDR 10 µs Remarks 1 tRG Regulator output stabilization time 2 T tCYK 73 76 75 74 78 77 0 V 0 V...

Page 660: ...true position T P at maximum material condition ITEM MILLIMETERS A B D G 16 00 0 20 14 00 0 20 0 50 T P 1 00 J 16 00 0 20 K C 14 00 0 20 I 0 08 1 00 0 20 L 0 50 0 20 F 1 00 N P Q 0 08 1 40 0 05 0 10 0 05 S100GC 50 8EU 8EA 2 S 1 60 MAX H 0 22 0 05 0 04 M 0 17 0 03 0 07 R 3 7 3 1 25 26 50 100 76 75 51 S S N J detail of lead end C D A B R K M L P I S Q G F M H ...

Page 661: ...Q R K M L P S S N G F NOTE Each lead centerline is located within 0 15 mm of its true position T P at maximum material condition ITEM MILLIMETERS A B D G 23 6 0 4 20 0 0 2 0 30 0 10 0 6 H 17 6 0 4 I C 14 0 0 2 0 15 J 0 65 T P K 1 8 0 2 L 0 8 0 2 F 0 8 P100GF 65 3BA1 4 N P Q 0 10 2 7 0 1 0 1 0 1 R 5 5 S 3 0 MAX M 0 15 0 10 0 05 C D A B S ...

Page 662: ...emperature 215 C Time 25 to 40 seconds at 200 C or higher Count Twice or less Exposure limit 7 days Note after that prebake at 125 C for 10 to 72 hours VP15 107 2 Partial heating Pin temperature 350 C max Time 3 seconds max per pin row 2 µPD703114GF 3BA 100 pin plastic QFP 14 20 µPD70F3114GF 3BA 100 pin plastic QFP 14 20 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared r...

Page 663: ... Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max at 220 C or higher Count Three times or less Exposure limit 3 days Note after that prebake at 125 C for 20 to 72 hours IR60 203 3 Wave soldering For details consult an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 seconds max per pin r...

Page 664: ...astic LQFP Fine Pitch 14 14 Side view Target system NQPACK100SD YQPACK100SD 231 26 mm Note In circuit emulator option board Conversion connector IE 703114 MC EM1 In circuit emulator IE V850E MC YQGUIDE Note YQSOCKET100SDN sold separately can be inserted here to adjust the height height 3 2 mm Top view Target system YQPACK100SD NQPACK100SD YQGUIDE IE 703114 MC EM1 IE V850E MC Connection condition d...

Page 665: ...d IE 703114 MC EM1 In circuit emulator IE V850E MC Note YQSOCKET100SDN sold separately can be inserted here to adjust the height height 3 2 mm Top view Target system YQPACK100RB NQPACK100RB YQGUIDE IE 703114 MC EM1 IE V850E MC NEXB 2R100SD RB 8 mm 20 7 mm Pin 1 position Connection condition diagram 33 2 mm 28 7 mm 18 5 mm 20 mm 38 mm Target system NQPACK100RB YQPACK100RB IE 703114 MC EM1 Connect t...

Page 666: ...ADETM0L A D voltage detection mode register 0L ADC 520 ADETM1 A D voltage detection mode register 1 ADC 520 ADETM1H A D voltage detection mode register 1H ADC 520 ADETM1L A D voltage detection mode register 1L ADC 520 ADIC0 Interrupt control register INTC 150 ADIC1 Interrupt control register INTC 150 ADSCM00 A D scan mode register 00 ADC 517 ADSCM00H A D scan mode register 00H ADC 517 ADSCM00L A D...

Page 667: ... Baud rate generator control register 0 UART0 433 BSC Bus size configuration register BCU 87 CC100 Capture compare register 100 TM10 308 CC101 Capture compare register 101 TM10 309 CC10IC0 Interrupt control register INTC 150 CC10IC1 Interrupt control register INTC 150 CC2IC0 Interrupt control register INTC 150 CC2IC1 Interrupt control register INTC 150 CC2IC2 Interrupt control register INTC 150 CC...

Page 668: ... TM10 307 CM101 Compare register 101 TM10 307 CM10IC0 Interrupt control register INTC 150 CM10IC1 Interrupt control register INTC 150 CM4 Compare register 4 TM4 398 CM4IC0 Interrupt control register INTC 150 CMSE050 Timer 2 subchannel 0 5 capture compare control register TM2 338 CMSE120 Timer 2 subchannel 1 2 capture compare control register TM2 339 CMSE340 Timer 2 subchannel 3 4 capture compare c...

Page 669: ...C0 DMA transfer count register 0 DMAC 111 DBC1 DMA transfer count register 1 DMAC 111 DBC2 DMA transfer count register 2 DMAC 111 DBC3 DMA transfer count register 3 DMAC 111 DCHC0 DMA channel control register 0 DMAC 114 DCHC1 DMA channel control register 1 DMAC 114 DCHC2 DMA channel control register 2 DMAC 114 DCHC3 DMA channel control register 3 DMAC 114 DDA0H DMA destination address register 0H ...

Page 670: ...WC0 Data wait control register 0 BCU 94 DWC1 Data wait control register 1 BCU 94 FEM0 Timer 2 input filter mode register 0 TM2 160 586 FEM1 Timer 2 input filter mode register 1 TM2 160 586 FEM2 Timer 2 input filter mode register 2 TM2 160 586 FEM3 Timer 2 input filter mode register 3 TM2 160 586 FEM4 Timer 2 input filter mode register 4 TM2 160 586 FEM5 Timer 2 input filter mode register 5 TM2 160...

Page 671: ...er 0L TM2 345 P0 Port 0 Port 563 P0IC0 Interrupt control register INTC 150 P0IC1 Interrupt control register INTC 150 P0IC2 Interrupt control register INTC 150 P0IC3 Interrupt control register INTC 150 P0IC4 Interrupt control register INTC 150 P1 Port 1 Port 564 P2 Port 2 Port 566 P3 Port 3 Port 568 P4 Port 4 Port 570 PCM Port CM Port 579 PCT Port CT Port 576 PDH Port DH Port 572 PDL Port DL Port 5...

Page 672: ...TM3 373 PRM10 Prescaler mode register 10 TM10 305 PRSCM1 Prescaler compare register 1 UART1 469 PRSCM3 Prescaler compare register 3 CSI0 CSI1 510 PRSM1 Prescaler mode register 1 UART1 467 PRSM3 Prescaler mode register 3 CSI0 CSI1 509 PSC Power save control register CPU 185 PSMR Power save mode register CPU 184 PSTO0 PWM software timing output register 0 TM00 219 PSTO1 PWM software timing output re...

Page 673: ...ansmit buffer register L0 CSI1 489 SOTBFL1 Clocked serial interface initial transmit buffer register L1 CSI0 489 SOTBL0 Clocked serial interface transmit buffer register L0 CSI1 487 SOTBL1 Clocked serial interface transmit buffer register L1 CSI0 487 SPEC0 TOMR write enable register 0 TM00 228 SPEC1 TOMR write enable register 1 TM01 228 SRIC0 Interrupt control register INTC 150 SRIC1 Interrupt con...

Page 674: ...6 TMC10 Timer control register 10 TM10 301 TMC30 Timer control register 30 TM3 374 TMC31 Timer control register 31 TM3 376 TMC4 Timer control register 4 TM4 400 TMIC0 Timer connection selection register 0 TM1 TM2 405 TO3C Timer 3 output control register TM3 379 TOMR0 Timer output mode register 0 TM00 213 TOMR1 Timer output mode register 1 TM01 213 TUC00 Timer unit control register 00 TM00 212 TUC0...

Page 675: ... 5 bit data that specifies a trap vector 00H to 1FH cccc 4 bit data that shows a condition code sp Stack pointer r3 ep Element pointer r30 list X item register list 2 Symbols used in operands Symbol Explanation R 1 bit of data of code that specifies reg1 or regID r 1 bit of data of code that specifies reg2 w 1 bit of data of code that specifies reg3 d 1 bit of data of a displacement I 1 bit of imm...

Page 676: ... If n is a computation result and n 80000000H make n 80000000H result Reflect result in flag Byte Byte 8 bits Half word Halfword 16 bits Word Word 32 bits Addition Subtraction Bit concatenation Multiplication Division Remainder of division result AND Logical product OR Logical sum XOR Exclusive logical sum NOT Logical negation logically shift left by Logical shift left logically shift right by Log...

Page 677: ...ow NV 1000 OV 0 No overflow C L 0001 CY 1 Carry Lower Less than NC NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY or Z 1 Not higher Less than equal H 1011 CY or Z 0 Higher Greater than N 0100 S 1 Negative P 1100 S 0 Positive T 0101 Always Unconditional SA 1101 SAT 1 Saturated LT 0110 S xor OV 1 Less then signed GE 1110 S xo...

Page 678: ...eturn PC CTPSW PSW adr CTBP zero extend imm6 logically shift left by 1 PC CTBP zero extend Load memory adr Halfword 5 5 5 1 0 b b b 1 1 1 1 1 0 R R R R R bit 3 disp16 reg1 d d d d d d d d d d d d d d d d adr GR reg1 sign extend disp 16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 0 3 Note 3 3 Note 3 3 Note 3 1 0 b b b 1 1 1 1 1 0 R R R R R CLR1 reg2 reg1 d d d d d d d d d d d d ...

Page 679: ...2 GR reg2 GR reg1 GR reg3 GR reg2 GR reg1 34 34 34 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 EI 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 PSW ID 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 HALT 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 Stop 1 1 1 r r r r r 1 1 1 1 1 1 0 0 0 0 0 HSW reg2 reg3 w w w w w 0 1 1 0 1 0 0 0 1 0 0 GR reg3 GR reg2 15 0 GR reg2 31 16 1 1 1 0 r r r r r 1 1 1 1 0 d d d d d d JARL disp22 reg2 d d d d d d d d d...

Page 680: ... 1 1 1 1 1 R R R R R reg1 reg2 reg3 w w w w w 0 1 0 0 0 1 0 0 0 1 0 GR reg3 GR reg2 GR reg2 GR reg1 reg1 reg2 reg3 reg3 r0 1 2 Note 14 2 r r r r r 1 1 1 1 1 1 i i i i i MULU Note 22 imm9 reg2 reg3 w w w w w 0 1 0 0 1 I I I I 1 0 GR reg3 GR reg2 GR reg2 zero extend imm9 1 2 Note 14 2 NOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Passes at least 1 cycle doing nothing 1 1 1 NOT reg1 reg2 r r r r r 0 0 0 0 0 1 ...

Page 681: ...reg2 saturated GR reg1 GR reg2 1 1 1 r r r r r 1 1 1 1 1 1 0 c c c c SETF cccc reg2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H 1 1 1 0 0 b b b 1 1 1 1 1 0 R R R R R bit 3 disp16 reg1 d d d d d d d d d d d d d d d d adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 1 3 Note 3 3 Note 3 3 Note ...

Page 682: ... GR reg2 GR reg1 1 1 1 SUBR reg1 reg2 r r r r r 0 0 1 1 0 0 R R R R R GR reg2 GR reg1 GR reg2 1 1 1 SWITCH reg1 0 0 0 0 0 0 0 0 0 1 0 R R R R R adr PC 2 GR reg1 logically shift left by 1 PC PC 2 sign extend Load memory adr Halfword logically shift left by 1 5 5 5 SXB reg1 0 0 0 0 0 0 0 0 1 0 1 R R R R R GR reg1 sign extend GR reg1 7 0 1 1 1 SXH reg1 0 0 0 0 0 0 0 0 1 1 1 R R R R R GR reg1 sign ext...

Page 683: ...opcode Therefore the meanings of register specifications assigned in the mnemonic description and in the opcode differ from those in other instructions rrrrr regID specification RRRRR reg2 specification 13 iiiii Lower 5 bits of imm9 IIII Higher 4 bits of imm9 14 Shortened by 1 clock if reg2 reg3 lower 32 bits of result are not written to register or reg3 r0 higher 32 bits of result are not written...

Page 684: ...ties pp 125 126 Modification of description in 6 8 Next Address Setting Function p 129 Addition of Figure 6 9 Example of Forcible Termination of DMA Transfer p 132 Modification of descriptions in 6 14 2 Transfer of misaligned data and 4 DMA start factors p 132 Addition of 6 14 5 Program execution and DMA transfer with internal RAM p 134 Addition of Caution to 7 1 Features pp 135 137 Addition of No...

Page 685: ...9 Modification of Figure 10 20 Asynchronous Serial Interface Reception Completion Interrupt Timing p 583 Addition of Caution to 12 5 2 1 Timer 10 noise elimination time selection register NRC10 p 584 Addition of Caution to 12 5 2 2 Timer 3 noise elimination time selection register NRC3 p 586 Addition of Caution to 12 5 3 1 Timer 2 input filter mode registers 0 to 5 FEM0 to FEM5 p 611 Addition of 1...

Page 686: ...description in 4 2 1 Pin status during internal ROM internal RAM and peripheral I O access Addition and modification of description in 4 3 Memory Block Function Addition of 4 3 1 Chip select control function Addition of description in 4 4 1 1 Bus cycle type configuration registers 0 1 BCT0 BCT1 Addition of indication of Note in 4 5 1 Number of access clocks Addition of 4 5 2 Bus sizing function Ad...

Page 687: ...on of Caution in Table 9 2 Operation Modes of Timer 0 Addition and modification of description in 9 1 5 3 Timer unit control registers 00 01 TUC00 TUC01 Modification of description in 9 1 5 4 Timer output mode registers 0 1 TOMR0 TOMR1 Addition and modification of description in 9 1 5 6 PWM software timing output registers 0 1 PSTO0 PSTO1 and addition of Figures 9 9 to 9 14 Addition of Remark in 9...

Page 688: ...ace Reception Completion Interrupt Timing Change of description on bits that can be manipulated and addition of Caution in 10 2 6 2 a Clock select register 0 CKSR0 Change of description on bits that can be manipulated in 10 2 6 2 b Baud rate generator control register 0 BRGC0 Addition of 2 in 10 2 7 Cautions Change of description on bits that can be manipulated in 10 3 3 4 2 frame continuous recep...

Page 689: ...on in 14 2 Functional Outline Modification of Figure 14 1 Example of Connection When Using N ch Transistor Addition of Figure 14 2 Mount Pad Dimensions When Mounted on 2SD1950 VL Standard Product Glass Epoxy Board Unit mm Addition of Figure 14 3 Connection When Using External Regulator Addition and modification of description in Caution in 14 4 1 Regulator control register REGC CHAPTER 14 REGULATO...

Page 690: ... of Timer 0 Modification of description in Table 9 4 Operation Modes of Timer 0 TM0n Modification of description in Remark in 9 1 6 2 PWM mode 0 Triangular wave modulation right left symmetric waveform control Modification of Figures 9 15 9 17 to 9 20 9 22 to 9 30 and 9 32 to 9 35 CHAPTER 9 TIMER COUNTER FUNCTION REAL TIME PULSE UNIT Modification of maximum transfer rate in 10 2 1 Features Additio...

Page 691: ...ng Function Addition of Cautions 1 and 2 to 6 10 DMA Transfer Start Factors Modification of description in 6 11 Forcible Suspension Addition of 6 13 1 Restrictions on forcible termination of DMA transfer Modification of description in 6 14 Time Required for DMA Transfer Addition of 6 15 5 Restrictions related to automatic clearing of TCn bit of DCHCn register and 6 Read values of DSAn and DDAn reg...

Page 692: ...o AC test input test points in 16 1 Normal Operation Mode Change of description of Stabilization capacitance in the Conditions column in 16 1 3 Regulator output stabilization time Modification of description of tHSTWT1 in 16 1 5 a CLKOUT asynchronous Addition of Caution to 16 1 5 c Read cycle CLKOUT synchronous asynchronous 1 wait Addition of Caution to 16 1 5 d Write cycle CLKOUT synchronous asyn...

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