CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U15195EJ5V0UD
430
(7) Receive data noise filter
The RXD0 signal is sampled at the rising edge of the prescaler output base clock (f
CLK
). If the same sampling
value is obtained twice, the match detector output changes, and this output is sampled as input data.
Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit
(see
Figure 10-12
). Refer to
10.2.6 (1) (a) Base clock (Clock)
regarding the base clock.
Also, since the circuit is configured as shown in Figure 10-11, internal processing during a receive operation
is delayed by up to 2 clocks according to the external signal status.
Figure 10-11. Noise Filter Circuit
RXD0
f
CLK
Q
Clock
In
LD_EN
Q
In
Internal signal A
Internal signal B
Match detector
Figure 10-12. Timing of RXD0 Signal Judged as Noise
Internal signal A
Clock
RXD0 (input)
Internal signal B
Match
Mismatch
(judged as noise)
Mismatch
(judged as noise)
Match
