CHAPTER 9 TIMER/COUNTER FUNCTION
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User’s Manual U15195EJ5V0UD
Figure 9-74. Capture Operation: Mode with 16-Bit Buffer
Note 1
(When CMSEx0 Register’s TByE1
Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1, EEVEy Bit = 1,
and CSCE0 Register’s SEVEy Bit = 0)
f
CLK
MUXTB0
MUXTB1
BUFFER
READ_ENABLE_P
CVPEm0 register
CVSEm0 register
MUXCNT
ED1
CAPTURE_P
CAPTURE_S
TB0
TB1
TB0
TB1
TB0
TB1
TB0
TB1
TB0
TB1
TB0
TB1
TB0
TB1
TB0
TB1
TB0
TB1
TB0
TB1
1
5
6
2
3
4
7
8
5
9
10
6
11
7
8
9
10
12
13
New event
14
Note 2
Note 3
Undefined
Undefined
2
4
Capture
2
3
4
8
Shift
L
Event
Notes 1.
To operate TM2n in the mode with 16-bit buffer, perform a capture at least twice at the start of an
operation and read the CVPEm0 register. Also, read the CVPEm0 register after performing a capture
at least once.
2.
A write operation to the CVPEn0 register is not performed at these signal inputs because the CVSEm0
register operates as a buffer.
3.
After this timing, a write operation from the CVSEm0 register to the CVPEm0 register is enabled.
Remarks 1.
f
CLK
: Base clock
2.
BUFFER: Timing of write operation from CVSEm0 register to CVPEm0 register
CAPTURE_P: Capture trigger signal of main capture register
CAPTURE_S: Capture trigger signal of sub capture register
ED1: Capture event signal input from edge selector
MUXCNT: Count value to subchannel m
MUXTB0, MUXTB1: Multiplex signal of TM20, TM21
READ_ENABLE_P: Read timing of CVPEm0 register
TB0: Count value of TM20; TB1: Count value of TM21
3.
m = 1 to 4, x = 12, 34
y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4
