CHAPTER 9 TIMER/COUNTER FUNCTION
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User’s Manual U15195EJ5V0UD
(1) Timer 3 (TM3)
TM3 functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being
mainly used for cycle measurement, TM3 can be used as pulse output.
TM3 is read-only, in 16-bit units.
Cautions 1. The TM3 register can only be read. If writing is performed to the TM3 register, the
subsequent operation is undefined.
2. If the TM3CAE bit of the TMC30 register is cleared (0), a reset is performed
asynchronously.
3. Continuous reading of TM3 is prohibited. If TM3 is continuously read, the second read
value may differ from the actual value.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TM3
FFFFF680H
0000H
Address
After reset
0
TM3 performs the count-up operations of an internal count clock or external count clock. Timer starting and
stopping are controlled by the TM3CE bit of timer control register 30 (TMC30).
The internal or external count clock is selected by the ETI bit of timer control register 31 (TMC31).
(a) Selection of the external count clock
TM3 operates as an event counter.
When the ETI bit of timer control register 31 (TMC31) is set (1), TM3 counts the valid edges of the
external clock input (TI3), synchronized with the internal count clock. The valid edge is specified by valid
edge selection register (SESC).
Caution When using the INTP30, TI3, and TCLR3 pins as TI3 andTCLR3, either mask the
interrupt signal to INTP30 or set CC3n in compare mode (n = 0 or 1).
(b) Selection of the internal count clock
TM3 operates as a free-running timer.
When an internal clock is specified as a count clock by timer control register 31 (TMC31), TM3 is counted
up for each input clock cycle specified by the CS2 to CS0 bits of the TMC30 register.
Division by the prescaler can be selected for the count clock from among f
CLK
/2, f
CLK
/4, f
CLK
/8, f
CLK
/16,
f
CLK
/32, f
CLK
/64, f
CLK
/128 and f
CLK
/256 by the TMC30 register (f
CLK
: base clock).
An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following an
overflow by setting the OST bit of the TMC31 register to 1.
Caution The count clock cannot be changed while the timer is operating.
The conditions when the TM3 register becomes 0000H are shown below.
(i) Asynchronous
reset
•
TM3CAE bit of TMC30 register = 0
•
Reset
input
(ii) Synchronous reset
•
TM3CE bit of TMC30 register = 0
•
The CC30 register is used as a compare register, and the TM3 and CC30 registers match when
clearing the TM3 register is enabled (CCLR bit of the TMC31 register = 1)
