CHAPTER 9 TIMER/COUNTER FUNCTION
334
User’s Manual U15195EJ5V0UD
(1/2)
<14>
CLRE1
<13>
CEE1
12
ECRE1
2
OSTE0
3
ECEE0
4
ECRE0
<5>
CEE0
<6>
CLRE0
7
0
8
UDSE10
9
UDSE11
10
OSTE1
11
ECEE1
15
CASE1
1
UDSE01
0
UDSE00
TCRE0
Address
FFFFF646H
After reset
0000H
Bit position
Bit name
Function
15
CASE1
Specifies 32-bit cascade operation mode for TM21 (TM21 counts upon overflow of
TM20 (carry count)).
0: Not connected in cascade
Note 1
1: 32-bit cascade operation mode
Notes 2, 3
Notes 1.
TM21 counts at CT signal input in the count enabled state.
2.
TM21 counts at CTC and CASC signal inputs in the count enabled state.
3.
Only the capture register mode can be used for the capture/compare
register.
Cautions 1. When CASE1 = 1, set the TByE1 and TByE0 bits of the CMSEx0
register to 11 (x = 12, 34, y: When x = 12, y = 1, 2, and when x =
34, y = 3, 4).
2. When CASE1 = 0, TCOUNTE1 is selected as the count of TM21.
When CASE1 = 1, TCOUNTE0 and the TM20 overflow signal are
selected as the count of TM21.
14, 6
CLREn
Specifies software clear for TM2n.
0: TM2n operation continued
1: TM2n count value cleared (0)
Caution Do not perform the software clear and hardware clear operations
simultaneously.
13, 5
CEEn
Specifies TM2n count operation enable/disable.
0: Count operation stopped
1: Count operation enabled
12, 4
ECREn
Specifies TM2n external clear (TCLR2) operation enable/disable via ECLR signal
input.
0: TM2n external clear (TCLR2) operation not enabled
1: TM2n external clear (TCLR2) operation enabled
Cautions 1.
In the 32-bit cascade operation mode (CASE1 = 1), the TM2n
external clear operation is not performed.
2. When the count value is cleared by inputting the ECLR signal
while ECREn = 1, the ECREn = 1 setting must be held for at least
one of the internal count clocks set by the CSEn2 to CSEn0 bits
of the CSE0 register.
3. In the 32-bit cascade operation mode (CASE1 = 1), only TM21 is
affected by the ECREn bit setting.
Remark
n = 0, 1
