CHAPTER 4 BUS CONTROL FUNCTION
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User’s Manual U15195EJ5V0UD
4.8 Bus Priority Order
There are three external bus cycles: DMA cycle, operand data access, and instruction fetch.
In order of priority, DMA cycle is the highest, followed by operand data access and instruction fetch, in that order.
An instruction fetch may be inserted between a read access and write access during a read modify write access.
Also, an instruction fetch may be inserted between bus accesses when the CPU bus is locked.
Table 4-1. Bus Priority Order
Priority
Order
External Bus Cycle
Bus Master
DMA cycle
DMA controller
Operand data access
CPU
High
Low
Instruction fetch
CPU
