APPENDIX D REVISION HISTORY
691
User's Manual U15195EJ5V0UD
(6/7)
Edition
Major Revision up to Previous Edition
Applied to:
•
Addition of the following products
µ
PD703114GC(A)-
×××
-8EU, 70F3114GC(A)-8EU
Throughout
Addition of
Note 2
to
1.5 Pin Configuration (Top View)
CHAPTER 1
INTRODUCTION
Addition of description to
6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
Addition of
Caution 2
to
6.3.1 DMA source address registers 0H to 3H (DSA0H to DSA3H)
Addition of description to
6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)
Addition of
Caution 2
to
6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to
DDA3H)
Addition of description and
Cautions 1
and
2
to
6.3.3 DMA transfer count registers 0 to 3
(DBC0 to DBC3)
Addition of
Caution 2
to
6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)
Modification/addition of description of
Caution
in
6.3.5 DMA channel control registers 0 to 3
(DCHC0 to DCHC3)
Modification of description in
6.3.7 DMA restart register (DRST)
Addition of description to
6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
Addition of description to
Remark
in
6.7.1 Transfer type and transfer target
Deletion of
Note
from
Table 6-2 External Bus Cycles During DMA Transfer (Two-Cycle
Transfer)
Modification of description in
6.9 Next Address Setting Function
Addition of
Cautions 1
and
2
to
6.10 DMA Transfer Start Factors
Modification of description in
6.11 Forcible Suspension
Addition of
6.13.1 Restrictions on forcible termination of DMA transfer
Modification of description in
6.14 Time Required for DMA Transfer
Addition of
6.15 (5) Restrictions related to automatic clearing of TCn bit of DCHCn register
and
(6) Read values of DSAn and DDAn registers
CHAPTER 6 DMA
FUNCTIONS (DMA
CONTROLLER)
Modification of description in
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING
FUNCTION
CHAPTER 7
INTERRUPT/
EXCEPTION
PROCESSING
FUNCTION
Addition of
Caution 2
to
9.1.6 (2) PWM mode 0: Triangular wave modulation (right-left
symmetric waveform control)
Addition of
Note
to
9.3.4 (3) Timer 2 count clock/control edge selection register 0 (CSE0)
Addition of
9.3.6 PWM output operation in timer 2 compare mode
Modification of description in
Figure 9-91 TM3 Compare Operation Example (Set/Reset
Output Mode)
CHAPTER 9
TIMER/COUNTER
FUNCTION (REAL-
TIME PULSE UNIT)
Addition of
Caution 2
to
10.2.3
(1) Asynchronous serial interface mode register 0 (ASIM0)
Addition of
Caution
to
10.2.5 (3) Continuous transmission operation
Addition of description of transfer rate to
10.3.1 Features
Addition of
Cautions 1
and
2
to
10.3.3 (1) Asynchronous serial interface mode register 10
(ASIM10)
Addition of
Caution 3
to
10.3.7 (2) (c) Prescaler compare register 1 (PRSCM1)
4th
Modification of description in
Table 10-8 Baud Rate Generator Setting Data (BRG = f
XX
/2)
CHAPTER 10
SERIAL INTERFACE
FUNCTION
