CHAPTER 9 TIMER/COUNTER FUNCTION
233
User’s Manual U15195EJ5V0UD
[Output waveform width with respect to set value]
•
PWM cycle = BFCMn3
×
2
×
T
TM0n
•
Dead-time width T
Dnm
= (DTRRn + 1)/f
CLK
•
Active width of positive phase (TO0n0, TO0n2, TO0n4 pins)
= { (CM0n3
−
CM0nX
up
) + (CM0n3
−
CM0nX
down
) }
×
T
TM0n
−
T
Dnm
•
Active width of negative phase (TO0n1, TO0n3, TO0n5 pins)
=
(CM0nX
down
+ CM0nX
up
)
×
T
TM0n
−
T
Dnm
•
In this mode, CM0nX
up
= CM0nX
down
(however, within the same PWM cycle).
Since CM0nX
up
and CM0nX
down
in the negative phase formula are prepared in a separate PWM cycle,
CM0nX
up
≠
CM0nX
down
.
f
CLK
:
Base clock
T
TM0n
:
TM0n count clock
CM0nX
up
: Set value of CM0n0 to CM0n2 while TM0n is counting up
CM0nX
down
: Set value of CM0n0 to CM0n2 while TM0n is counting down
The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state. When the control mode
is selected thereafter, the following levels are output until TM0n is started.
•
TO0n0, TO0n2, TO0n4… When active low
→
High level
When active high
→
Low level
•
TO0n1, TO0n3, TO0n5… When active low
→
Low level
When active high
→
High level
The active level is set with the ALVTO bit of the TOMRn register. The default is active low.
Caution If a value such that the positive phase or negative phase active width is “0” or a negative
value is set in the above formula, the TO0n0 to TO0n5 pins output a waveform fixed to the
inactive level waveform with active width “0”.
Remarks. 1
m = 0 to 2
n = 0, 1
2.
The interrupt request signal occurrence conditions of INTCM010 to INTCM012, INTCM0n4,
and INTCM0n5 are shown below.
Setting Condition
INTCM010 to INTCM012, INTCM0n4,
INTCM0n5 Signal Occurrence Status
CM010 to CM012, CM0n4, CM0n5
≤
CM0n3
Occurs
CM010 to CM012, CM0n4, CM0n5 = 0000H
Occurs
CM010 to CM012, CM0n4, CM0n5 > CM0n3
Does not occur
