CHAPTER 16 ELECTRICAL SPECIFICATIONS
644
User’s Manual U15195EJ5V0UD
(1) Clock timing
(T
A
= –40 to +85
°
C, REGIN = 3.0 to 3.6 V, V
DD
= RV
DD
= 5.0 V
±
0.5 V, V
SS3
= V
SS
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
Direct mode
20
125
ns
X1 input cycle
t
CYX
<1>
PLL mode
156 250 ns
Direct mode
6
ns
X1 input high-level width
t
WXH
<2>
PLL mode
50
ns
Direct mode
6
ns
X1 input low-level width
t
WXL
<3>
PLL mode
50
ns
Direct mode
4
ns
X1 input rise time
t
XR
<4>
PLL mode
10
ns
Direct mode
4
ns
X1 input fall time
t
XF
<5>
PLL mode
10
ns
4
40
MHz
CPU operation frequency
f
XX
–
CLKOUT signal used
Note
4
32
MHz
25
250
ns
CLKOUT output cycle
t
CYK
<6>
CLKOUT signal used
Note
31.25
250
ns
CLKOUT high-level width
t
WKH
<7>
0.5T – 9
ns
CLKOUT low-level width
t
WKL
<8>
0.5T – 11
ns
CLKOUT rise time
t
KR
<9>
11
ns
CLKOUT fall time
t
KF
<10>
9
ns
Delay time from X1
↓
to CLKOUT
t
DXK
<11>
Direct
mode
40
ns
Note
When interfacing to the external devices using the CLKOUT signal, make the internal system clock frequency
(f
XX
) 32 MHz or lower.
Remark
T
=
t
CYK
X1
<3>
<1>
<2>
<4>
<5>
X1
(Direct mode)
(
PLL
mode)
<5>
<1>
<2>
<3>
<4>
<11>
<11>
CLKOUT
(output)
<8>
<9>
<7>
<10>
<6>
