CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U15195EJ5V0UD
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(5) Transfer rate during continuous transmission
During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of
the base clock longer than normal. However, on the reception side, the transfer result is not affected since
the timing is initialized by the detection of the start bit.
Figure 10-15. Transfer Rate During Continuous Transmission
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FL
1 data frame
Bit 0
FL
FL
FL
FL
FL
FL
FLstp
Start bit of
second byte
Start bit
Representing the 1-bit data length by FL, the stop bit length by FLstp, and the base clock frequency by f
CLK
yields the following equation.
FLstp = FL + 2/f
CLK
Therefore, the transfer rate during continuous transmission is as follows. (when stop bit length = 1)
Transfer rate = 11
×
FL + (2/f
CLK
)
10.2.7 Cautions
Cautions to be observed when using UART0 are shown below.
(1) When the supply of clocks to UART0 is stopped (for example, in IDLE or software STOP mode), operation
stops with each register retaining the value it had immediately before the supply of clocks was stopped. The
TXD0 pin output also holds and outputs the value it had immediately before the supply of clocks was stopped.
However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of
clocks is restarted, the circuits should be initialized by setting UARTCAE0 = 0, RXE0 = 0, and TXE0 = 0 in
the ASIM0 register.
(2) UART0 has a 2-stage buffer configuration consisting of transmit buffer register 0 (TXB0) and the transmit shift
register, and has status flags (the TXBF0 and TXSF0 bits of the ASIF0 register) that indicate the status of
each buffer. When the TXBF0 and TXSF0 bits are read at the same time during continuous transmission, the
read values change “10”
→
“11”
→
“01”. Judge the timing for writing the next data to the TXB0 register by
reading only the TXBF0 bit when performing continuous transmission.
